CN203981764U - High speed pulse peak identifying and sampling circuit - Google Patents

High speed pulse peak identifying and sampling circuit Download PDF

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Publication number
CN203981764U
CN203981764U CN 201420235398 CN201420235398U CN203981764U CN 203981764 U CN203981764 U CN 203981764U CN 201420235398 CN201420235398 CN 201420235398 CN 201420235398 U CN201420235398 U CN 201420235398U CN 203981764 U CN203981764 U CN 203981764U
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China
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peak
holding
sampling
trigger
unit
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CN 201420235398
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Chinese (zh)
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刘南
农永光
胡刚
唐丽
刘明辉
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中节能六合天融环保科技有限公司
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Abstract

A high speed pulse peak identifying and sampling circuit comprises a voltage comparator LM311, a sampling and holding chip LF398, a trigger SN74LS74, an analog switch MAX4541, a resistor and a capacitor, and is characterized in that a pulse peak determining and holding circuit takes the high speed voltage comparator LM311, the sampling and holding chip LF398 and the trigger SN74LS74 as the core elements, wherein the voltage comparator LM311 is used to determine whether a pulse reaches a peak, the sampling and holding chip LF398 holds a peak voltage for a period of time, and the trigger SN74LS74 triggers a micro control unit (MCU) to finish the AD sampling; the MCU takes a C8051F410 single-chip microcomputer as the core, receives a sampling signal coming from the trigger, sends a command of the AD sampling, and controls the charging and discharging of a holding capacitor. The high speed pulse peak identifying and sampling circuit of the utility model is simple in structure design, is easy to debug, and satisfies the AD sampling requirement of a pulse-height analyzer in the energy spectrum analysis.

Description

高速脉冲峰值甄别采样电路 High-speed sampling pulse peak discriminating circuit

技术领域 FIELD

[0001] 本实用新型涉及一种高速脉冲峰值甄别采样电路,特别是涉及一种应用在能谱分析中脉冲幅度分类及计数的电路中。 [0001] The present invention relates to a high-speed pulse peak discrimination sampling circuit, particularly to an application in the pulse amplitude spectrum analysis classification and counting circuit.

背景技术 Background technique

[0002] 峰值保持电路具有保持和采样两个状态。 [0002] The peak hold circuit having a sampling and holding two states. 处于采样状态时,电路的输出始终跟随输入信号;处于保持状态时,电路的输出保持着前一次米样结束前瞬间的输入量。 When the sampling state, always follow the output of the circuit input signal; when in the holding state, the output circuit is maintained previous input end of the instant rice samples. 在高速峰值采集过程中,为了保证AD转换的精度,在转换过程中其输入信号变化量不能大于 Peak acquisition process in a high speed, in order to ensure the precision of AD conversion, the conversion process in which the amount of change is not greater than the input signal

dVin dVin

1/2LSB。 1 / 2LSB. 假设输入信号Vin = Vm.sincot,则Vin的最大变化率为= 当AD转换器的分辨率为η位,转换时间为t时,为保证AD转换器的正常工作,则可得输入信号所允许的最大频率为Zmax =-^设8位AD转换器的转换时间t = lOOus,代入上式计算可 Assuming that the input signal Vin = Vm.sincot, then Vin = the maximum rate of change when the resolution of the AD converter η bits, conversion time t, for the proper operation of the AD converter, the input signal may have allowed the maximum frequency of Zmax = - ^ 8 disposed AD converter conversion time t = lOOus, may be substituted into the equation above

2 'K't 2 'K't

得,AD转换器的所允许的最大输入信号频率fmax = 6Hz。 Too, AD converter of maximum allowable input frequency fmax = 6Hz. 为获取高频的脉冲信号峰值,必须在信号AD转换器之前对其峰值进行保持。 To obtain a high frequency pulse signal peak must be kept until its peak signal AD converter.

[0003] 传统的峰值保持电路原理图如图1所示,由集成运算放大器,二极管和电容构成。 [0003] The conventional peak hold circuit diagram, by an integrated operational amplifier, a diode and a capacitor shown in FIG. 在传统的峰值保持电路中,输入信号通过由运算放大器组成的电压跟随器后向保持电容充电,直到充到输入电压的最大值。 In the conventional peak hold circuit, the input signal to the charge storage capacitor of the operational amplifier through a voltage follower until charged to a maximum voltage at the input. 在理想情况下,保持电容可以保持输入信号的峰值电压,但是实际中二极管的反向电阻不是无穷大,电路下一级也存在电阻并且保持电容存在漏电。 Ideally, a peak voltage holding capacitor can maintain an input signal, but in practice the reverse resistance of the diode is not infinite, but also the presence of a resistor and storage capacitor circuit there is a leakage. 从频域来看,二极管和保持电容组成的网络积分非线性大、动态范围小且存在极点,由于二极管内部电阻不是恒定值,极点的位置不固定。 From the frequency domain point of view, the network and the storage capacitor integral nonlinearity diode composed of large and small dynamic range and there is extreme, since the internal resistance of the diode is not constant, the pole position is not fixed. 通过这样的电路采集到的峰值信号,不能满足高速脉冲信号处理的要求。 Collected by such a circuit to peak signal, can not meet the requirements of high-speed pulse signal processing.

发明内容 SUMMARY

[0004] 本实用新型为了克服上述现有技术的不足,提供了一种高速脉冲峰值甄别采样电路。 [0004] The present invention is to overcome the disadvantages of the prior art described above, there is provided a high-speed pulse peak discrimination sampling circuit.

[0005] 本实用新型提出的技术方案是,一种高速脉冲峰值甄别采样电路,包括高速电压比较器LM311、采样保持芯片LF398、触发器SN74LS74、模拟开关MAX4541及电阻、电容,构成信号过滤单元、峰值甄别单元、触发单元、峰值保持单元、采样单元组成,其特征在于: [0005] The present invention proposed solution is a high-speed sampling pulse peak discriminating circuit, comprising a high-speed voltage comparator LM311, sample and hold chip LF398, trigger SN74LS74, MAX4541 analog switch and a resistor, capacitor, constitute a signal filtering unit, peak discriminating means, the trigger means, the peak holding unit, a sampling unit, and is characterized in that:

[0006] 信号过滤单元由两个高速电压比较器LM311和两个BOURNS精密电位器构成,信号过滤单元的输出端与峰值甄别单元的输入端连接; [0006] The signal filtering means comprises a high-speed voltage comparator LM311, two and two BOURNS precision potentiometers, filtered input signal to the peak output terminal unit connected to the screening unit;

[0007] 峰值甄别单元由I个高速电压比较器LM311和信号保持电路构成,峰值甄别单元的命令输出端作为所述触发单元的控制端;峰值甄别单元的信号输出端与所述峰值保持单元的输入端连接; [0007] I peak discriminating means is held by a high-speed voltage comparator LM311, and a signal circuit, the peak discriminating unit command output terminal as the control terminal of the trigger unit; screening peak signal output unit and the peak holding unit an input terminal;

[0008] 触发单元即SN74LS74触发器,与峰值保持单元的控制端连接; [0008] The trigger unit triggers SN74LS74 i.e., a control terminal connected to the peak holding means;

[0009] 峰值保持单元由采样保持芯片LF398、保持充电电容、模拟开关MAX4541构成,所述信号保持电路的信号保持端与保持充电电容的一端连接,保持充电电容的另一端接地;所述保持充电电容接地端与模拟开关的公共端连接,所述保持充电电容的另一端与模拟开关的常开端连接; [0009] peak value held by the sample holding means LF398 chips, capacitor remains charged, constituting an analog switch MAX4541, the signal holding circuit holding one end connected with the end of the holding capacitor charging, holding the other end of the charging capacitor; the remains charged the common ground terminal of the capacitor is connected to analog switches, the capacitor remains charged normally open and the other end is connected to the analog switch;

[0010] 采样单元由AD电路和参考电压基准电路构成,采样单元与峰值保持单元连接。 [0010] AD sampling unit is constituted by a reference voltage circuit and a reference circuit, a sampling unit connected to the peak holding means.

[0011] 以高速电压比较器LM311、采样保持芯片LF398和触发器SN74LS74为核心元件的脉冲峰值判断保持电路,其中高速电压比较器LM311用来判断脉冲是否达到峰值,采样保持芯片LF398将峰值电压保持一段时间,触发器SN74LS74触发MCU控制单元完成AD的采样;MCU控制单元以C8051F410单片机为核心,接收来自触发器的采样信号,发送AD采样的命令以及控制保持电容的充放电。 [0011] In a high-speed voltage comparator LM311, and trigger a sample and hold chip LF398 SN74LS74 core element for the determination pulse peak hold circuit, wherein the high-speed voltage comparator LM311 pulse is used to determine whether a peak sample and hold the peak voltage holding chip LF398 period of time, the control unit MCU trigger trigger SN74LS74 completion of sampling AD; control unit MCU C8051F410 microcontroller core, received samples from the trigger signal and transmits a control command AD sampling and holding the capacitor charging and discharging. 采样电路选用高速AD采样芯片TLC4545,当收到MCU的采样命令后,迅速完成AD采样任务。 A sampling circuit used high-speed AD sampling chip TLC4545, when the MCU receives the sampling command, sampling task AD completed quickly.

[0012] 本实用新型提出的一种高速脉冲峰值甄别采样电路,其优点在于:采用高速低功耗电压比较器LM311判别脉冲幅度,电压上阈、下阈由可调精密电位器分压获得,采用Nat1nal Semiconductor公司的采样保持芯片LF398实现采样保持功能,其控制端可直接接于TTL、CM0S L逻辑电平,LOGIC引脚电平决定电路处于采样或者保持状态,采用触发器SN74LS74发送信号给MCU控制AD采样。 [0012] a high-speed pulse peak discrimination present sampling circuit proposed invention, which is advantageous in that: the use of high speed low power voltage pulse amplitude discriminating LM311 comparator, the threshold voltage, the threshold obtained by dividing by an adjustable precision potentiometers, Nat1nal Semiconductor companies using sample and hold chip LF398 implemented sample and hold function, which can be directly connected to the control terminal TTL, CM0S L logic level, the level determining circuit lOGIC pin or held in the sampling state, the flip-flop using the transmission signal to the MCU SN74LS74 control AD ​​samples. 采用C8051F410单片机作为控制器,其功耗低响应快,很好地实现了电路开发需求。 C8051F410 microcontroller employed as the controller, fast response low power consumption, the circuit to achieve a good development needs. 可以对高速脉冲进行峰值展宽,从而保证AD采样的准确性。 It can be stretched to a peak speed pulse, in order to ensure the accuracy of the AD samples. 本实用新型选用感应吸收与漏电流均较小的聚苯乙烯电容作为保持电容,降低了误差,提高了采样的精度。 Inductive limit the present invention and leakage current are small absorption polystyrene as a storage capacitor capacitance, reduce errors and improve the accuracy of sampling. 本实用新型提出的设计方法简单易懂,能够被设计者很容易的掌握并应用在集成电路设计中。 Design method of the present invention proposes a simple and easy to understand, can be easily mastered and applied in the design of integrated circuit designers.

附图说明 BRIEF DESCRIPTION

[0013] 以下结合附图及实施例,对本实用新型作进一步说明: [0013] accompanying drawings and the following embodiments, the present invention is further described as:

[0014] 图1为传统峰值保持电路原理图 [0014] FIG. 1 is a schematic circuit diagram of a conventional holding peak

[0015] 图2为高速脉冲采样流程图 [0015] FIG 2 is a flowchart of high speed sampling pulses

[0016] 图3为高速脉冲峰值甄别采样电路原理图 [0016] FIG. 3 is a high-speed sampling pulse peak discriminating circuit schematics

具体实施方式 Detailed ways

[0017]由图1所示,传统的峰值保持电路由集成运算放大器,二极管和电容构成。 [0017] shown in FIG. 1, a conventional peak hold circuit by an integrated operational amplifier, a diode and a capacitor.

[0018] 由图2可见,高速脉冲采样流程为,首先判断脉冲峰值的到来,然后触发脉冲峰值保持电路,随后触发MCU发布采样命令,最后采样电路完成峰值信号采样。 [0018] Figure 2 shows, high speed pulse of the sampling process, the arrival of the pulse peak is first determined, and then the trigger pulse peak holding circuit, and then release the trigger MCU sample command, the last peak signal sampling circuit performs the sampling.

[0019] 由图3可见,一种高速脉冲峰值甄别采样电路,它包括电压比较器LM311、采样保持芯片LF398、触发器SN74LS74、模拟开关MAX4541及其他电阻电容。 [0019] seen in Figure 3, a high-speed sampling pulse peak discriminating circuit which comprises a voltage comparator LM311, sample and hold chip LF398, trigger SN74LS74, MAX4541 analog switches and other resistance and capacitance. 图中,电压比较器U3和U4共同完成脉冲幅度检测范围的确定,当输入的脉冲信号在幅度检测范围内时,电压比较器U3和U4输出端实现线与功能;此时采样保持芯片U5工作在采样状态,输出OUTl跟随输入信号INPUT变化;峰值没有到来时,OUTl电压值小于输入信号INPUT的电压值,电压比较器U6输出低电平,触发器U7不触发;当峰值到来时,电压比较器U3、U4和采样保持芯片U5状态保持不变,而由于OUTl电压值大于输入信号INPUT的电压值,电压比较器U6输出高电平,产生上升沿,触发器U7触发,运输出低电平,采样保持芯片U8工作于电压保持状态, FIG., The voltage comparator U3 and U4 together to complete the detection range determined pulse amplitude, when the input pulse signal within the detection range of the amplitude, the voltage comparator U3 and U4 and the output end of the line to achieve the function; In this case the sample and hold chip U5 work in the sample state, the output follows the input signal iNPUT OUTl change; no peak arrival, OUTl voltage smaller than the voltage of the input signal iNPUT, output low voltage comparator U6, U7 is not triggered flip-flop; when the peak arrival, the voltage comparator unit U3, U4 and U5 chip sample hold status remains unchanged, and because the voltage OUTl voltage is greater than the value of the input signal iNPUT, output of the voltage comparator U6 high, a rising edge, the flip-flop U7 is triggered, the low level transport sample and hold chip U8 working hold state voltage,

同时IQ输出高电平,向单片机发送中断信号,通知单片机峰值到来,单片机收到信号后,启动AD转换,完成最后的采样。 Meanwhile IQ output high, transmits an interrupt signal to the microcontroller, the microcontroller peak arrival notification, the microcontroller signal is received, the AD conversion starts, the last sample is completed. AD转换完成后,单片机向触发器发送清零信号,同时控制模拟开关SI闭合,保持电容Cl和C2进行放电,等待下一个脉冲的到来。 After the AD conversion is completed, the microcontroller transmits a clear signal to the flip-flop, while controlling the analog switch SI is closed, the storage capacitor Cl and C2 are discharged, waits for the next pulse.

Claims (1)

1.一种高速脉冲峰值甄别采样电路,由高速电压比较器LM311、采样保持芯片LF398、触发器SN74LS74、模拟开关MAX4541及电阻、电容构成信号过滤单元、峰值甄别单元、触发单元、峰值保持单元、采样单元组成,其特征在于: 信号过滤单元由两个高速电压比较器LM311和两个BOURNS精密电位器构成,信号过滤单元的输出端与峰值甄别单元的输入端连接; 峰值甄别单元由I个高速电压比较器LM311和采样保持芯片LF398构成,峰值甄别单元的命令输出端作为所述触发单元的控制端;峰值甄别单元的信号输出端与所述峰值保持单元的输入端连接; 触发单元即SN74LS74触发器,与峰值保持单元的控制端连接; 峰值保持单元由采样保持芯片LF398、保持充电电容、模拟开关MAX4541构成,所述采样保持芯片的信号保持端与保持充电电容的一端连接,保持充电电容的另一端接地;所述保 1. A high speed sampling pulse peak discriminating circuit, a high-speed voltage comparator LM311, sample and hold chip LF398, trigger SN74LS74, MAX4541 analog switch and the resistor, the signal filtering unit constituting the capacitor, the peak discriminating means, the trigger means, the peak holding unit, sampling units, wherein: signal filtering means comprises a high-speed voltage comparator LM311, two and two BOURNS precision potentiometers, the output of the peak input signal discrimination means connected to the filter means; peak screening unit consists of a high-speed I LM311 voltage comparator and a sample and hold chip LF398 configuration, the screening means commands the peak output terminal as the control terminal of the trigger unit; screening peak signal output unit and the input terminal of the peak holding unit is connected; i.e., the trigger unit triggers SN74LS74 , a peak holding unit is connected to a control terminal; peak holding means holding the chip LF398 by the sample holding capacitor charging, the analog switch MAX4541 configured, the chip sample hold signal holding capacitor connected to one end terminal of the charging and holding, holding the capacitor charging other end; the protection 充电电容接地端与模拟开关的公共端连接,所述保持充电电容的另一端与模拟开关的常开端连接; 采样单元由AD电路和参考电压基准电路构成,采样单元与峰值保持单元连接。 Charging capacitor and a ground terminal connected to a common terminal of the analog switch, the normally open holding the other end of the charging capacitor is connected to the analog switch; AD sampling unit is constituted by a reference voltage circuit and a reference circuit, a sampling unit connected to the peak holding means.
CN 201420235398 2014-05-09 2014-05-09 High speed pulse peak identifying and sampling circuit CN203981764U (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106405212A (en) * 2016-12-12 2017-02-15 重庆西南集成电路设计有限责任公司 Double-edge-triggered differential-method-based peak detector and peak detection method
WO2017133383A1 (en) * 2016-02-05 2017-08-10 广东欧珀移动通信有限公司 Adapter and charge control method

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017133383A1 (en) * 2016-02-05 2017-08-10 广东欧珀移动通信有限公司 Adapter and charge control method
WO2017133387A1 (en) * 2016-02-05 2017-08-10 广东欧珀移动通信有限公司 Adaptor and charge control method
WO2017133382A1 (en) * 2016-02-05 2017-08-10 广东欧珀移动通信有限公司 Adapter and charging control method
EP3282551A4 (en) * 2016-02-05 2018-05-23 Guangdong Oppo Mobile Telecommunications Corp., Ltd. Adapter and charging control method
EP3249779A4 (en) * 2016-02-05 2018-07-25 Guangdong Oppo Mobile Telecommunications Corp., Ltd. Adaptor and charge control method
US10291060B2 (en) 2016-02-05 2019-05-14 Guangdong Oppo Mobile Telecommunications Corp., Ltd. Adapter and charging control method
CN106405212A (en) * 2016-12-12 2017-02-15 重庆西南集成电路设计有限责任公司 Double-edge-triggered differential-method-based peak detector and peak detection method
CN106405212B (en) * 2016-12-12 2019-02-15 重庆西南集成电路设计有限责任公司 Double edge triggering differential method peak detectors and peak-value detection method

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