CN201528321U - Pulse-width signal duty ratio detector - Google Patents

Abstract

The utility model relates to a pulse-width signal duty ratio detector, which comprises a current source mirror circuit 1, a capacitor charging and discharging circuit 2, a divider 3 and a rising edge detection circuit 4 of pulse signals. Two capacitors are respectively charged by a mirror constant flow source; charging voltage peak values of a pulse-width signal high-level time interval and a periodic time interval are obtained from the two capacitors; and to-be-detected duty ratio is obtained by using the divider for deducting. Charging and discharging of the capacitors are used for respectively obtaining the charging voltage peak values of the pulse-width signal high-level time interval and the periodic time interval with no task of leaching ripple wave, thereby capacity ratio is one thousand times smaller than that of a traditional detector. Simultaneously, the detector needing no waiting for stability of the process of charging and discharging the capacitors is capable of realizing real-time detection of periodical duty ratio. The pulse-width signal duty ratio detector breaks design conception of a traditional duty ratio detector, and achieves optimized structure and excellent effect of real-time detection function.

Description

Pulse width signal duty factor detector

Technical field

The utility model relates to a kind of detector, particularly a kind of pulse width signal duty factor detector.

Background technology

In prior art, traditional duty cycle detector as shown in Figure 4, its course of work is: when tested pulse width signal Vi was high level, N1 turn-offed, the P1 conducting, capacitor C 1 charging, charge circuit is power supply V _DD-PMOS pipe P1-resistance R 1-capacitor C 1; When tested pulse width signal Vi is input as low level, the N1 conducting, P1 turn-offs, capacitor C 1 discharge, discharge path is capacitor C 1-resistance R 1-NMOS pipe N1-ground.If the duty ratio of tested pulse width signal Vi is fixed, and R1, C1 time constant for charging and discharging be during much larger than switch periods, and the voltage on the electric capacity remains unchanged, then output voltage V ₀Can represent to import the size of duty cycle square wave, it is calculated as follows:

Referring to Fig. 4,6, the cycle of supposing tested pulse width signal Vi is T, and its high level lasting time is Ton, and then the duty ratio D of Vi input is:

$D=\frac{\mathrm{Ton}}{T}$ ①

Work as output voltage V ₀After stable, V _DDDischarging and recharging of capacitor C 1 reached balance, and its charging charge equals discharge charge, that is:

$\mathrm{Ton}\·\frac{V_{\mathrm{DD}}-V_O}{R1}=(T-\mathrm{Ton})\·\frac{V_O}{R1}$ ②

To 2. formula of 1. formula substitution, put in order:

V _O＝DV _DD ③

$D=\frac{V_O}{V_{\mathrm{DD}}}$ ③，

The subject matter that this conventional detector exists is: the capacitor C 1 in the circuit is a filter capacitor, and it is undertaking the task of eliminating output voltage ripple, and therefore, it needs bigger capacitance, and its value is calculated as follows:

Referring to Fig. 6,7, work as output voltage V ₀After stable, the ripple Δ V of its output voltage ₀For:

$\mathrm{\Δ}{V}_O=\frac{\mathrm{Ton}\·(V_{\mathrm{DD}}-V_O)}{R1\·C1}$ ④

Will be 1., 3. 4. formula of formula substitution, put in order:

$\mathrm{\Δ}{V}_0=\frac{D\·T\·V_{\mathrm{DD}}\·(1-D)}{R1\·C1}$ ⑤

When D=1/2, the ripple numerical value maximum of output voltage, for:

$\mathrm{\Δ}{V}_O=\frac{T\·V_{\mathrm{DD}}}{4R1\·C1}$ ⑥

Calculate with maximum ripple: suppose T=20us, V _DDBe 5V, R1=100K Ω, C1=10nF obtains Δ V _O=25mV, the ripple of this ripple for allowing, ripple is the smaller the better, does not generally allow to surpass 50mV.Find out thus, under the ripple of a permission, the capacitance of this circuit is very big, and electric capacity is big more, and its volume is big more, the volume of 10nF electric capacity can't be integrated in this detector in this example, this just greatly reduces the integrated level of this detector, and detector need additionally provide a pin, is used for external capacitor, the volume of detector is increased, loosely organized.

It can also be seen that according to aforementioned calculation, this detector can only just can carry out the detection of duty ratio after charge and discharge enter stable state, if we need carry out the real-time detection of the duty ratio of Cycle by Cycle to tested pulse width signal, this detector just can not be suitable for, and this is its another shortcoming.

The utility model content

The purpose of this utility model is the shortcoming that overcomes in the prior art, and a kind of pulse width signal duty factor detector is provided, and makes it can reduce the electric capacity volume and with realizing tested pulse width signal is detected in real time.

For achieving the above object, the technical solution of the utility model is as follows:

This detector has a current source mirror image circuit that the two-way charging current can be provided; Also has a capacitor charge and discharge circuit, this capacitor charge and discharge circuit is by the charging paths and the second electric capacity charging paths of first electric capacity, these two charging paths are connected on respectively on two current output terminals of described current source mirror image circuit, on the charging paths of described first electric capacity, be connected in series one electronic switch K3, be used to control the charging of first electric capacity, the control end of this electronic switch and the input of tested pulse width signal join, on described first electric capacity and second electric capacity, be respectively equipped with a bypass discharge paths, and on these two bypass discharge paths, respectively be connected in series an electronic switch K1, K2 is used for controlling respectively first electric capacity and second capacitance discharges; This detector also has a divider, and the charging positive pole of described first, second electric capacity joins with two inputs of this divider respectively, and the output of described divider is drawn for detecting output; This detector also has the rising edge testing circuit of a pulse width signal, the input of this rising edge testing circuit and the input of tested pulse width signal join, its output respectively with first electric capacity and the second capacitive bypass discharge paths on electronic switch K1, the control end of K2 join.

The further improved technical scheme of the utility model is as follows:

PMOS transistor and nmos pass transistor that the rising edge testing circuit of described pulse width signal is connected by push-pull type, a current source, an electric capacity, a hysteresis comparator, reverser and one connect and compose with door, the control utmost point of described PMOS transistor and nmos pass transistor joins as the signal input part of this rising edge testing circuit and the input of tested pulse width signal, described current source is serially connected on the source electrode of nmos pass transistor, described electric capacity is connected in parallel on the drain electrode of PMOS transistor and nmos pass transistor and with reference between the ground, the positive pole of described electric capacity links to each other with the input of hysteresis comparator, the output of described hysteresis comparator by not gate with link to each other with an input of door, described another input and the input of tested pulse width signal with door joins, described with output as the output of rising edge testing circuit respectively with charge-discharge circuit in electronic switch K1, the control end of K2 joins.

By technique scheme as can be seen, the utility model adopts mirror-image constant flow source that the two-way charging current is provided, respectively two electric capacity are charged, with tested pulse width signal the charging process of this two-way electric capacity is carried out logic control simultaneously, the final charging voltage peak value that on two electric capacity, obtains pulse width signal high level period and one-period period, with divider this two charging voltages peak value is divided by then, promptly draws tested duty ratio.Because the electric capacity charge and discharge in the utility model are in order to obtain the charging voltage peak value of pulse width signal high level period and one-period period respectively, do not undertake the task of filtering ripple, therefore, do not need very big capacitance, its capacitance is littler 1000 times than prior art, in the pf level, make it can satisfy the integrated volume requirement of circuit fully.Simultaneously, as long as the utility model can access the charging voltage peak value of two-way electric capacity, just can obtain testing result, not need to wait for the stable of electric capacity charge and discharge process, therefore, it can realize the real-time detection of Cycle by Cycle duty ratio.The utility model has been broken the mentality of designing of traditional duty cycle detector, has obtained the good result of optimizing structure and increasing real-time detection function.

Description of drawings

Fig. 1, the utility model circuit theory diagrams.

The detection waveform figure of Fig. 2, rising edge testing circuit.

The charge and discharge waveform schematic diagram of Fig. 3, capacitor C 1, C2.

The schematic diagram of Fig. 4, traditional duty cycle detector.

The input of Fig. 5, traditional duty cycle detector, output wave figure.

The waveform schematic diagram of Fig. 6, tested pulse width signal.

The ripple schematic diagram of Fig. 7, traditional duty cycle detector output voltage.

Embodiment

Referring to Fig. 1, this detector has a current source mirror image circuit 1, it comprises the constant-current source and the current mirror circuit that is made of this constant-current source PMOS transistor MP3, MP4 that are connected and composed by PMOS transistor MP2 and resistance R, produce a constant current I by described constant-current source, produce two-way and the proportional mirror image constant current of I I1, I2 by current mirror circuit.

This detector also has a capacitor charge and discharge circuit 2, this capacitor charge and discharge circuit is made up of the charging paths and capacitor C 22 charging paths of capacitor C 11, these two charging paths are connected on respectively on two current output terminals of described current source mirror image circuit, on the charging paths of described capacitor C 11, be connected to one electronic switch K3, be used for the charging of control capacitance C11, the control end of this electronic switch K3 and the input of tested pulse width signal PWM join, on described capacitor C 11 and capacitor C 22, be respectively equipped with a bypass discharge paths, and on these two bypass discharge paths, respectively be connected to an electronic switch K1, K2, the discharge of control capacitance C11 and capacitor C 22 respectively.

This detector also has a divider 3, and the charging positive pole of described capacitor C 11, C22 joins with two inputs of this divider respectively, and the output of described divider 3 is drawn for detecting output end vo o.

This detector also has a rising edge testing circuit 4, it comprises PMOS transistor MP1 and the nmos pass transistor MN1 that push-pull type connects, current source Id, capacitor C 33, hysteresis comparator X1, reverser X2 and with door X3, the control utmost point of described MP1 and MN1 joins as the signal input part of this rising edge testing circuit and the input of tested pulse width signal PWM, described current source Id is serially connected on the source electrode of NM0S transistor MN1, described capacitor C 33 is connected in parallel between the drain electrode and ground of MN1 and MP1, the positive pole of capacitor C 33 links to each other with the input of hysteresis comparator X1, the output of hysteresis comparator X1 passes through not gate X2 and links to each other with the input of door X3, join with the input of another input of door X3 and tested pulse width signal PWM, with the output of door X3 as the output of rising edge testing circuit respectively with charge-discharge circuit 2 in electronic switch K1, the control end of K2 joins.

Referring to Fig. 1,2, as tested pulse width signal PWM (V _PWM) when being high level, the transistor MN1 conducting in the rising edge testing circuit 4, transistor MP1 end, capacitor C 33 is discharged over the ground by MN1, Id, and (its waveform is seen V _C33), hysteresis comparator X1 output high level (is V _X1Be height), output low level behind reverser X2 (is V _X2For low), the high level of this low level and measured pulse signal PWM mutually " with " after, export a rising edge and detect burst pulse V _RESET, this narrow arteries and veins signal makes electronic switch K1, K2 moment conducting, and then capacitor C 11, C22 discharge by bypass, and K1, K2 close subsequently; When the high level of tested pulse width signal PWM arrives, electronic switch K3 conducting, in capacitor C 11, after C22 sparks and finishes, two-way mirror image constant current I1, I2 begins immediately to capacitor C 11, the C22 charging, when measured pulse signal PWM transfers low level to by high level, K3 ends, capacitor C 11 stops charging, and keep current charging voltage, and capacitor C 22 continues charging, till when the high level of measured pulse signal PWM arrives once more, C11, the charge waveforms of C22 such as the VC11 among Fig. 3, shown in the VC22, then the charging peak value of high level period and the charging peak value of 22 periods in last cycle of capacitor C are divided by by divider 3 on the capacitor C 11, promptly draw the dutyfactor value of measured signal.

Specifically being calculated as follows of dutyfactor value:

According to the female law in Europe, the electric current I p2 that PMOS transistor MP2 branch road flows through in the current source mirror image circuit 1 is:

$\mathrm{Ip}2=\frac{\mathrm{Vr}}{R}---\left(1\right)$

Vr is the voltage drop on the resistance R in the formula (1).

According to the principle of current source mirror image, suppose that the wide Wp2 of MP2, the ratio of long Lp2 are

The wide Wp3 of MP3, the ratio of long Wp3 are , the wide Wp4 of MP4, the ratio of long Wp4 are

Then the electric current I p3, the Ip4 that flow through of PMOS transistor MP3, MP4 branch road is:

$\mathrm{Ip}3=\frac{\mathrm{Wp}3\·\mathrm{Lp}2}{\mathrm{Lp}3\·\mathrm{Wp}2}\·\mathrm{Ip}2---\left(2\right)$

$\mathrm{Ip}4=\frac{\mathrm{Wp}4\·\mathrm{Lp}2}{\mathrm{Lp}4\·\mathrm{Wp}2}\·\mathrm{Ip}2---\left(3\right)$

When the high level lasting time of tested pulse width signal PWM is Ton, charging voltage V on the capacitor C 11 _C11For:

$V_{C11}=\frac{\mathrm{Ip}3\·\mathrm{Ton}}{C1}---\left(4\right)$

When the cycle of input signal PWM is T, charging voltage V on the capacitor C 22 _C22For:

${\mathrm{<figure-callout\; id="22"\; label="V\; C"\; filenames="H200920035064XE00021.png"\; state="\{\{state\}\}">V</figure-callout>}}_C=\frac{\mathrm{Ip}4\&CenterDot;T}{C2}---\left(5\right)$

The coefficient that removes of supposing divider 3 is k ', and then the output voltage V oo of divider 3 is:

$\mathrm{Voo}=k^{\&prime;}\&CenterDot;\frac{V_{C11}}{V_{C22}}---\left(6\right)$

After (2), (3) substitution (4), (5) formula, substitution again (6), put in order:

$\mathrm{Voo}=k^{\&prime;}\&CenterDot;\frac{V_{C11}}{{\mathrm{<figure-callout\; id="22"\; label="V\; C"\; filenames="H200920035064XE00021.png"\; state="\{\{state\}\}">V</figure-callout>}}_C}=k^{\&prime;}\&CenterDot;\frac{\mathrm{Wp}3}{\mathrm{Lp}3}\&CenterDot;\frac{\mathrm{Lp}4}{\mathrm{Wp}4}\&CenterDot;\frac{C2}{C1}\&CenterDot;\frac{\mathrm{Ton}}{T}---\left(7\right)$

Order:

$k=k^{\&prime;}\&CenterDot;\frac{\mathrm{Wp}3}{\mathrm{Lp}3}\&CenterDot;\frac{\mathrm{Lp}4}{\mathrm{Wp}4}\&CenterDot;\frac{C2}{C1}$ D＝Ton/T

Then formula (7) is reduced to:

$\mathrm{Voo}=k\&CenterDot;\frac{\mathrm{Ton}}{T}=k\&CenterDot;D$

The calculation of capacity of charging capacitor C11, C22 that this is routine is as follows:

If image current Ip3, Ip4 are 2uA, still being that 20us is an example by the one-period T of lateral vein bandwidth signals, and the charging peak value of hypothesis C22 is 4V, then

C22＝I×T/U＝2u*20u/4＝10pf

From aforementioned calculation as can be seen, the charge and discharge capacitor C 22 of this detector maximum is littler 1000 times than the charge and discharge capacitor C 1 of above-mentioned conventional detector.

This be since two kinds to detect thinkings different, traditional method electric capacity is in order to filter ripple, therefore to be the bigger the better, and electric capacity of the present utility model is in order to obtain charging peak value, so electric capacity does not need so big.

Claims (2)

1. pulse width signal duty factor detector is characterized in that:

A, has a current source mirror image circuit (1) that the two-way charging current can be provided;

B, has a capacitor charge and discharge circuit (2), this capacitor charge and discharge circuit is by the charging paths and second electric capacity (C22) charging paths of first electric capacity (C11), these two charging paths are connected on respectively on two current output terminals of described current source mirror image circuit, on the charging paths of described first electric capacity, be connected in series one electronic switch K3, be used to control the charging of first electric capacity, the input of the control end of this electronic switch K3 and tested pulse width signal (PWM) joins, on described first electric capacity (C11) and second electric capacity (C22), be respectively equipped with a bypass discharge paths, and on these two bypass discharge paths, respectively be connected in series an electronic switch K1, K2 is used for controlling respectively first electric capacity and second capacitance discharges;

C, have a divider (3), the charging positive pole of described first, second electric capacity (C11, C22) joins with two inputs of this divider (3) respectively, and the output of described divider is drawn for detecting output;

D, has the rising edge testing circuit (4) of a pulse width signal, the input of the input of this rising edge testing circuit and tested pulse width signal (PWM) joins, its output respectively with first electric capacity and the second capacitive bypass discharge paths on electronic switch K1, the control end of K2 join.

2. pulse width signal duty factor detector according to claim 1, it is characterized in that: PMOS transistor (MP1) and nmos pass transistor (MN1) that the rising edge testing circuit of described pulse width signal is connected by push-pull type, a current source (Id), an electric capacity (C33), a hysteresis comparator (X1), a reverser (X2) and one connect and compose with door (X3), the control utmost point of described PMOS transistor (MP1) and nmos pass transistor (MN1) joins as the signal input part of this rising edge testing circuit and the input of tested pulse width signal (PWM), described current source (Id) is serially connected on the source electrode of nmos pass transistor (MN1), described electric capacity (C33) is connected in parallel on the drain electrode of PMOS transistor (MP1) and nmos pass transistor (MN1) and with reference between the ground, the positive pole of described electric capacity (C33) links to each other with the input of hysteresis comparator (X1), the output of described hysteresis comparator (X1) passes through not gate (X2) and links to each other with an input of door (X3), described another input and the input of tested pulse width signal (PWM) with door (X3) joins, the output of described and door (X3) as the output of rising edge testing circuit respectively with the middle electronic switch K1 of charge-discharge circuit (2), the control end of K2 joins.

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