CN205596084U - Be applied to hysteresis comparator of RS -485 receiving terminal - Google Patents

Abstract

The utility model discloses a do you be applied to RS 485 the hysteresis comparator of receiving terminal, including bleeder circuit, foldable cascode fortune is put, and polarity alteration switch and hysteresis voltage control circuit, bleeder circuit are used for carrying out electric flat line nature displacement to two incoming signal of hysteresis comparator, and the follow -up circuit of being convenient for is handled, foldable cascode fortune put with bleeder circuit links to each other, carries out the comparison to two signals behind the level shift, the polarity alteration switch is in corresponding exchange according to the digital output result of outside polarity detection system, is carried out to comparator polarity in putting to foldable cascode fortune, hysteresis voltage control circuit, with foldable cascode fortune is put continuously for it is interval to adjust hysteresis voltage. The utility model discloses a has hysteresis comparator solved nonpolarity RS 485 can the sluggish interval positive interval problem that is in comparator polarity exchange back guarantee that the sluggish interval of comparator is in around the polarity exchange in the receiving terminal 200mV ~ between the 50mV.

Description

It is applied to the hysteresis comparator of RS-485 receiving terminal

Technical field

This utility model relates to electric energy communication system of power grids field or Analogical Circuit Technique field, particularly relates to be applied to RS-485 and connects A kind of hysteresis comparator of receiving end.

Background technology

RS-485 is by Electronic Industries Association (EIA) and and a kind of serial interface standard of formulating of Telecommunications Industries Association (TIA). RS-485 interface has the features such as strong noise suppression, relatively high transfer rate, long transmission distance, wide common mode range, simultaneously RS-485 communication interface chip has the advantages such as easy to control, with low cost.

The pin definitions of RS-485 communication interface chip as shown in Figure 2, wherein: RO is receiving terminal output signal；RE is Receiving terminal enables signal；DE is that transmitting terminal enables signal；DI is transmitting terminal input signal；VDD is power supply；A/B is signal Pin, when DE, RE are high level " 1 ", as the output pin of balance driver, when DE, RE are 0, Signal input pin as receiving terminal；GND is ground.

Nonpolarity RS-485 communication interface chip can detect A, the polarity of B signal line automatically, and according to testing result at chip Inside adjusts, with original polarized RS-485 chip in pin definitions completely compatible, can realize substitute, do not increase into This.

No. 201220086354.9 utility model patents of China disclose a kind of non-polar 485 chip, and it mainly includes differential electrical Pressure testing circuit, 5ms integrating circuit, communication polarity identification switch circuit, the voltage when between communication A, the B foot of 485 chips In lasting 5ms, when keeping Vab > 0, communication polarity identification switch circuit is failure to actuate, and the communication A foot giving tacit consent to 485 chips connects Enter on the A circuit of communication bus, on the B circuit of the communication B foot incoming communication bus of 485 chips；Communication when 485 chips In the 5ms that voltage between A, B foot is lasting, < when 0, communication polarity identification circuit overturns, the communication A of 485 chips to keep Vab Foot is received in the B bus of communication bus, on the A circuit of the communication B foot incoming communication bus of 485 chips.

Although above-mentioned patented technology provides a kind of non-polar 485 chip, but it has the disadvantage that, when receiving terminal comparator When sluggish interval is between-200mV～-50mV, after the method, comparator hysteresis interval becomes+50mV～+200mV, A/B End when states such as short circuit, free time, open circuits, just connecing with reversal connection two kinds in the case of RO output can change.

Summary of the invention

In order to solve above-mentioned technical barrier, the purpose of this utility model is to provide a kind of sluggishness being applied to RS-485 receiving terminal Comparator, becomes positive interval problem with comparator hysteresis interval after solving polarity exchange.

For reaching above-mentioned purpose, a kind of hysteresis comparator being applied to RS-485 receiving terminal of the present utility model, including dividing potential drop Circuit, folded cascode Op Amp, polarity switch and hysteresis voltage control circuit, bleeder circuit is for comparing sluggishness Two input signals of device carry out level linear displacement, it is simple to subsequent conditioning circuit processes；Folded cascode Op Amp and described dividing potential drop Circuit is connected, and compares two signals after level shift；Polarity switch is in described folded cascode Op Amp In, according to the digital output results of outside polarity detection system, comparator polarity is exchanged accordingly；Hysteresis voltage controls electricity Road, is connected with described folded cascode Op Amp, is used for regulating hysteresis voltage interval.

Improving further is that described bleeder circuit contains: the first PMOS, the second PMOS, the 3rd PMOS, 4th PMOS, and four resistance: the first resistance, the second resistance, the 3rd resistance, the 4th resistance；Wherein, described The source electrode of one PMOS and the source electrode of the second PMOS all meet supply voltage VDD, and grid meets the first bias voltage VBP1, The drain electrode of this first PMOS is connected with the source electrode of described 3rd PMOS, the drain electrode of this second PMOS and described The source electrode of four PMOS is connected, and the grid of described 3rd PMOS and draining is connected, then with the first resistance, the second resistance One end is connected, and the grid of described 4th PMOS is connected with drain electrode, then is connected with the 3rd resistance, one end of the 4th resistance, institute State another termination input signal A of the first resistance, another termination GND of described second resistance, the other end of described 3rd resistance Connect input signal B, another termination GND of described 4th resistance.

Improving further is that described folded cascode Op Amp is by five PMOS: the 5th PMOS, the 6th PMOS Pipe, the 7th PMOS, the 8th PMOS, the 9th PMOS, four NMOS tube: the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube composition；

The source electrode of the source electrode of described 5th PMOS, the source electrode of described 8th PMOS and described 9th PMOS all connects power supply Voltage VDD, the grid of the 5th PMOS connects the first bias voltage VBP1, the source electrode of described 6th PMOS and substrate Being connected with each other, then be connected with the drain electrode of the 5th PMOS, source electrode and the substrate of described 7th PMOS are connected with each other, then with The drain electrode of the 5th PMOS is connected, the grid of the 6th PMOS and the drain electrode of the first PMOS and the 3rd PMOS Source electrode be connected, the source electrode of the grid of the 7th PMOS and the drain electrode of the second PMOS and the 4th PMOS is connected, The grid of described 7th NMOS tube and the grid of the 8th NMOS tube are connected, and are all connected on the second bias voltage VBN2, The source electrode of the 7th NMOS tube and the source electrode of the 8th NMOS tube are all connected with GND, the grid of described 5th NMOS tube It is connected with the grid of the 6th NMOS tube, is all connected on the 3rd bias voltage VBN3, the source electrode of described 5th NMOS tube Drain electrode with the 7th NMOS tube is connected, and the source electrode of described 6th NMOS tube and the drain electrode of the 8th NMOS tube are connected, described 8th PMOS is connected with the grid of described 9th PMOS, and the grid of described 8th PMOS is connected with drain electrode, then Drain electrode with described 5th NMOS tube is connected, the drain electrode of described 9th PMOS and the drain electrode phase of described 6th NMOS tube Even.

Improving further is that described polarity switch contains: the first NMOS tube, the second NMOS tube, the 3rd NMOS Pipe, the 4th NMOS tube；The digital output signal of described outside polarity detection system is CLK and CLK '；Wherein: described The drain electrode of one NMOS tube is connected with the drain electrode of described 3rd NMOS tube, then is connected with the drain electrode of the 6th PMOS, described The drain electrode of the second NMOS tube is connected with the drain electrode of described 4th NMOS tube, then is connected with the drain electrode of the 7th PMOS, institute The grid of the grid and the second NMOS tube of stating the first NMOS tube is connected, and is all connected on CLK, described 3rd NMOS The grid of pipe and the grid of the 4th NMOS tube are connected, and are all connected on CLK ', the source electrode of described first NMOS tube and the The source electrode of four NMOS tube is connected, then is connected with the drain electrode of the 8th NMOS tube, the source electrode and the 3rd of described second NMOS tube The source electrode of NMOS tube is connected, then is connected with the drain electrode of the 7th NMOS tube.

Improving further is that described hysteresis voltage control circuit contains: the 5th resistance, possibly together with five NMOS tube: the 9th NMOS tube, the tenth NMOS tube, the 11st NMOS tube, the 12nd NMOS tube, the 13rd NMOS tube, also contain There are three phase inverters: the first phase inverter, the second phase inverter, the 3rd phase inverter；Wherein: the grid of described 9th NMOS tube with 3rd bias voltage VBN3 connects, and the drain electrode of the 9th NMOS tube is connected with one end of the 5th resistance, described 5th resistance Another terminates supply voltage VDD, the source electrode of described 9th NMOS tube and the drain electrode of the 9th PMOS and the 6th NMOS tube Drain electrode be connected, then be connected with the input of the first phase inverter, the output of described first phase inverter is connected with the input of the second phase inverter, The output of described second phase inverter is connected with the input of described 3rd phase inverter, and described 3rd phase inverter is output as OUT, described The grid of the tenth NMOS tube and the outfan of the first phase inverter are connected, the drain electrode of the tenth NMOS tube and the 8th NMOS tube Drain electrode be connected, the source electrode of the tenth NMOS tube is connected with the drain electrode of described 12nd NMOS tube, described 11st NMOS The grid of pipe and the outfan of the second phase inverter are connected, the drain electrode of the 11st NMOS tube and the drain electrode phase of the 7th NMOS tube Even, the source electrode of the 11st NMOS tube is connected with the drain electrode of described 13rd NMOS tube, described 12nd NMOS tube Grid is connected with the grid of described 13rd NMOS tube, is all connected on the second bias voltage VBN2, described 12nd NMOS The source electrode of pipe is all connected with GND with the source electrode of described 13rd NMOS tube.

The beneficial effects of the utility model are: the sluggishness that the utility model proposes a kind of RS-485 of being applied to receiving terminal compares Device, solves the sluggish interval problem for positive interval after comparator polarity exchanges in nonpolarity RS-485 receiving terminal, before polarity exchange After can ensure that the sluggish interval of comparator is between-200mV～-50mV.

Accompanying drawing explanation

Fig. 1 is the circuit diagram of hysteresis comparator of the present utility model.

Fig. 2 is the pin definitions of RS-485 communication interface chip.

Detailed description of the invention

Describe this utility model below with reference to the accompanying drawings and in conjunction with the embodiments in detail.

Referring to the drawings shown in 1, a kind of hysteresis comparator being applied to RS-485 receiving terminal described in the utility model, including Bleeder circuit, folded cascode Op Amp, polarity switch and hysteresis voltage control circuit:

Described bleeder circuit contains: the first PMOS MP6, the second PMOS MP7, the 3rd PMOS MP4, the Four PMOS MP5, and four resistance: the first resistance r1, the second resistance r2, the 3rd resistance r3, the 4th resistance r4, Wherein, the source electrode of described first PMOS MP6 and the source electrode of the second PMOS MP7 all connect supply voltage VDD, grid Pole meets the first bias voltage VBP1, the drain electrode of this first PMOS MP6 and the source electrode phase of described 3rd PMOS MP4 Even, the drain electrode of this second PMOS MP7 is connected with the source electrode of described 4th PMOS MP5, described 3rd PMOS The grid of pipe MP4 is connected with drain electrode, then is connected with one end of the first resistance r1, the second resistance r2, described 4th PMOS The grid of MP5 is connected with drain electrode, then is connected with the 3rd resistance r3, one end of the 4th resistance r4, and described first resistance r1's is another One termination input signal A, another termination input letter of another termination GND, described 3rd resistance r3 of described second resistance r2 Another termination GND of number B, described 4th resistance r4.

Described folded cascode Op Amp and polarity switch circuit contain: five PMOS: the 5th PMOS MP3, the 6th PMOS MP1, the 7th PMOS MP2, the 8th PMOS MP8, the 9th PMOS MP9, Possibly together with: eight NMOS tube: the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN8, the Eight NMOS tube MN9, wherein: the source electrode of described 5th PMOS MP3, the source electrode of described 8th PMOS MP8 All meeting supply voltage VDD with the source electrode of described 9th PMOS MP9, the grid of the 5th PMOS MP3 connects first Bias voltage, source electrode and the substrate of described 6th PMOS MP1 be connected with each other, then with the drain electrode of the 5th PMOS MP3 Being connected, source electrode and the substrate of described 7th PMOS MP2 are connected with each other, then are connected with the drain electrode of the 5th PMOS MP3, The source electrode of the grid of the 6th PMOS MP1 and the drain electrode of the first PMOS MP6 and the 3rd PMOS MP4 is connected, The source electrode of the grid of the 7th PMOS MP2 and the drain electrode of the second PMOS MP7 and the 4th PMOS MP5 is connected, The drain electrode of described first NMOS tube MN1 is connected with the drain electrode of described 3rd NMOS tube MN3, then with the 6th PMOS The drain electrode of MP1 is connected, and the drain electrode of described second NMOS tube MN2 is connected with the drain electrode of described 4th NMOS tube MN4, Drain electrode with the 7th PMOS MP2 is connected again, the grid of described first NMOS tube MN1 and the second NMOS tube MN2 Grid be connected, be all connected on CLK, the grid of described 3rd NMOS tube MN3 and the grid of the 4th NMOS tube MN4 The most connected, all it is connected on CLK ', the source electrode of described first NMOS tube MN1 and the source electrode of the 4th NMOS tube MN4 It is connected, then is connected with the drain electrode of the 8th NMOS tube MN9, the source electrode of described second NMOS tube MN2 and the 3rd NMOS The source electrode of pipe MN3 is connected, then is connected with the drain electrode of the 7th NMOS tube MN8, the grid of described 7th NMOS tube MN8 It is connected with the grid of the 8th NMOS tube MN9, is all connected on the second bias voltage VBN2, the 7th NMOS tube MN8 Source electrode and the source electrode of the 8th NMOS tube MN9 be all connected with GND, the grid of described 5th NMOS tube MN5 and The grid of six NMOS tube MN6 is connected, and is all connected on the 3rd bias voltage VBN3, described 5th NMOS tube MN5 Source electrode and the 7th NMOS tube MN8 drain electrode be connected, the source electrode of described 6th NMOS tube MN6 and the 8th NMOS tube The drain electrode of MN9 is connected, and described 8th PMOS MP8 is connected with the grid of described 9th PMOS MP9, and described the The grid of eight PMOS MP8 is connected with drain electrode, then is connected with the drain electrode of described 5th NMOS tube MN5, and the described 9th The drain electrode of PMOS MP9 is connected with the drain electrode of described 6th NMOS tube MN6.

Described hysteresis voltage control circuit contains: the 5th resistance r5, possibly together with five NMOS tube: the 9th NMOS tube MN7, the tenth NMOS tube MN10, the 11st NMOS tube MN11, the 12nd NMOS tube MN12, the 13rd NMOS Pipe MN13, possibly together with three phase inverters: the first phase inverter inv1, the second phase inverter inv2, the 3rd phase inverter inv3, wherein: The grid of described 9th NMOS tube MN7 and the 3rd bias voltage VBN3 connect, the drain electrode of the 9th NMOS tube MN7 It is connected with one end of the 5th resistance r5, another termination supply voltage VDD of described 5th resistance r5, described 9th NMOS tube The drain electrode of the source electrode of MN7 and the drain electrode of the 9th PMOS MP9 and the 6th NMOS tube MN6 is connected, more anti-phase with first The input of device inv1 is connected, and the output of described first phase inverter inv1 is connected with the input of the second phase inverter inv2, and described second The output of phase inverter inv2 is connected with the input of described 3rd phase inverter inv3, and described 3rd phase inverter inv3 is output as OUT, The grid of described tenth NMOS tube MN10 and the outfan of the first phase inverter inv1 are connected, the tenth NMOS tube MN10 Drain electrode be connected with the drain electrode of the 8th NMOS tube MN9, the source electrode of the tenth NMOS tube MN10 and described 12nd NMOS The drain electrode of pipe MN12 is connected, and the grid of described 11st NMOS tube MN11 and the outfan of the second phase inverter inv2 are connected, The drain electrode of the 11st NMOS tube MN11 is connected with the drain electrode of the 7th NMOS tube MN8, the 11st NMOS tube MN11 Source electrode be connected with the drain electrode of described 13rd NMOS tube MN13, the grid of described 12nd NMOS tube MN12 and institute The grid stating the 13rd NMOS tube MN13 is connected, and is all connected on the second bias voltage VBN2, described 12nd NMOS The source electrode of pipe MN12 is all connected with GND with the source electrode of described 13rd NMOS tube MN13.

Referring to the drawings shown in 1, in order to seek the positive and negative turn threshold point of comparator, when CLK be high level make MN1 and MN2 turns on, and CLK ' is low level time MN3 and MN4 is turned off, allow A terminal voltage be fixed on 0V, B end input from The voltage that 12V to-7V is gradually reduced, MP1 conducting during beginning, MP2 almost ends, and the electric current of MP3 is nearly all from MP1 Flowing through, the drain terminal voltage of MN6 is high, and the electric current of MP9 and MN7 is all almost 0, and the electric current of MN5 all flows to MN8, The electric current of MN11 branch road is the least, and along with B terminal voltage continues to reduce, the electric current of MP2 slowly increases, and the electric current of MP1 reduces, MN5 drain terminal voltage is reduced, and the electric current of MP8 reduces, and the electric current of MP9, MN5 the most slowly increases, until MP8 and When the electric current of MP9 is equal, phase inverter overturns, and after upset, the electric current of MP9 reduces, and the electric current of MN7 increases, and correspondence can Trying to achieve positive turn threshold point is:

$V_{TH+}=\frac{\sqrt{I_{MP3}-I_{MN12}-I_{MN9}+I_{MN8}}-\sqrt{I_{MP3}+I_{MN12}+I_{MN9}-I_{MN8}}}{\sqrt{{\mathrm{\&mu;}}_p{C}_{ox}{(W/L)}_{MP1,MP2}}}$

In like manner can try to achieve negative turn threshold point is:

$V_{TH-}=\frac{\sqrt{I_{MP3}+I_{MN13}-I_{MN9}+I_{MN8}}-\sqrt{I_{MP3}-I_{MN13}+I_{MN9}-I_{MN8}}}{\sqrt{{\mathrm{\&mu;}}_p{C}_{ox}{(W/L)}_{MP1,MP2}}}$

When polarity needs upset, A/B port exchanges, and CLK should be low level MN1 and MN2 is turned off simultaneously, CLK ' should be high level and MN3 and MN4 turned on, and so can make the positive and negative turn threshold voltage after polarity upset still It it is all negative value.

It is understood that the foregoing is only preferred embodiment of the present utility model, it is not limited to this practicality new Type, as the alteration switch in this utility model is not limited to nmos switch, it is also possible to be PMOS switch or transmission gate switch etc., Those skilled in the art according to the technical solution of the utility model and inventive concept equivalent or change in addition thereof, and can own These change or replacement all should belong to the scope of the claims attached by this utility model.

Claims (5)

1. the hysteresis comparator being applied to RS-485 receiving terminal, it is characterised in that including:

Bleeder circuit, for carrying out level linear displacement to two input signals of hysteresis comparator, it is simple to subsequent conditioning circuit processes；

Folded cascode Op Amp, is connected with described bleeder circuit, compares two signals after level shift；

Polarity switch, is in described folded cascode Op Amp, according to the digital output results of outside polarity detection system, exchanges comparator polarity accordingly；

Hysteresis voltage control circuit, is connected with described folded cascode Op Amp, is used for regulating hysteresis voltage interval.

2. hysteresis comparator as claimed in claim 1, it is characterized in that: described bleeder circuit is by the first PMOS (MP6), second PMOS (MP7), 3rd PMOS (MP4), 4th PMOS (MP5), and four resistance: the first resistance (r1), the second resistance (r2), the 3rd resistance (r3), the 4th resistance (r4) composition；

nullThe source electrode of described first PMOS (MP6) and the source electrode of the second PMOS (MP7) all meet supply voltage VDD，Grid meets the first bias voltage VBP1，The drain electrode of this first PMOS (MP6) is connected with the source electrode of described 3rd PMOS (MP4)，The drain electrode of this second PMOS (MP7) is connected with the source electrode of described 4th PMOS (MP5)，The grid of described 3rd PMOS (MP4) is connected with drain electrode，Again with the first resistance (r1)、One end of second resistance (r2) is connected，The grid of described 4th PMOS (MP5) is connected with drain electrode，Again with the 3rd resistance (r3)、One end of 4th resistance (r4) is connected，Another termination input signal A of described first resistance (r1)，Another termination GND of described second resistance (r2)，Another termination input signal B of described 3rd resistance (r3)，Another termination GND of described 4th resistance (r4).

3. hysteresis comparator as claimed in claim 2, it is characterized in that: described folded cascode Op Amp is by five PMOS: the 5th PMOS (MP3), the 6th PMOS (MP1), the 7th PMOS (MP2), the 8th PMOS (MP8), the 9th PMOS (MP9), four NMOS tube: the 5th NMOS tube (MN5), the 6th NMOS tube (MN6), the 7th NMOS tube (MN8), the 8th NMOS tube (MN9) composition；

nullThe source electrode of described 5th PMOS (MP3)、The source electrode of described 8th PMOS (MP8) and the source electrode of described 9th PMOS (MP9) all meet supply voltage VDD，The grid of the 5th PMOS (MP3) meets the first bias voltage VBP1，Source electrode and the substrate of described 6th PMOS (MP1) are connected with each other，Drain electrode with the 5th PMOS (MP3) is connected again，Source electrode and the substrate of described 7th PMOS (MP2) are connected with each other，Drain electrode with the 5th PMOS (MP3) is connected again，The grid of described 6th PMOS (MP1) and the source electrode of the drain electrode of the first PMOS (MP6) and the 3rd PMOS (MP4) are connected，The grid of the 7th PMOS (MP2) and the source electrode of the drain electrode of the second PMOS (MP7) and the 4th PMOS (MP5) are connected，The grid of described 7th NMOS tube (MN8) and the grid of the 8th NMOS tube (MN9) are connected，All it is connected on the second bias voltage VBN2，The source electrode of the 7th NMOS tube (MN8) and the source electrode of the 8th NMOS tube (MN9) are all connected with GND，The grid of described 5th NMOS tube (MN5) and the grid of the 6th NMOS tube (MN6) are connected，All it is connected on the 3rd bias voltage VBN3，The source electrode of described 5th NMOS tube (MN5) and the drain electrode of the 7th NMOS tube (MN8) are connected，The source electrode of described 6th NMOS tube (MN6) and the drain electrode of the 8th NMOS tube (MN9) are connected，Described 8th PMOS (MP8) is connected with the grid of described 9th PMOS (MP9)，The grid of described 8th PMOS (MP8) is connected with drain electrode，Drain electrode with described 5th NMOS tube (MN5) is connected again，The drain electrode of described 9th PMOS (MP9) is connected with the drain electrode of described 6th NMOS tube (MN6).

4. hysteresis comparator as claimed in claim 3, it is characterized in that: described polarity switch is by the first NMOS tube (MN1), second NMOS tube (MN2), the 3rd NMOS tube (MN3), the 4th NMOS tube (MN4) composition；The digital output signal of described outside polarity detection system is CLK and CLK '；

nullThe drain electrode of described first NMOS tube (MN1) is connected with the drain electrode of described 3rd NMOS tube (MN3)，Drain electrode with the 6th PMOS (MP1) is connected again，The drain electrode of described second NMOS tube (MN2) is connected with the drain electrode of described 4th NMOS tube (MN4)，Drain electrode with the 7th PMOS (MP2) is connected again，The grid of described first NMOS tube (MN1) and the grid of the second NMOS tube (MN2) are connected，All it is connected on CLK，The grid of described 3rd NMOS tube (MN3) and the grid of the 4th NMOS tube (MN4) are connected，All it is connected on CLK '，The source electrode of described first NMOS tube (MN1) and the source electrode of the 4th NMOS tube (MN4) are connected，Drain electrode with the 8th NMOS tube (MN9) is connected again，The source electrode of described second NMOS tube (MN2) and the source electrode of the 3rd NMOS tube (MN3) are connected，Drain electrode with the 7th NMOS tube (MN8) is connected again.

5. the hysteresis comparator as described in claim 3 or 4, it is characterized in that: described hysteresis voltage control circuit is by the 5th resistance (r5), five NMOS tube: the 9th NMOS tube (MN7), the tenth NMOS tube (MN10), the 11st NMOS tube (MN11), the 12nd NMOS tube (MN12), the 13rd NMOS tube (MN13), three phase inverters: the first phase inverter (inv1), second phase inverter (inv2), the 3rd phase inverter (inv3) composition；

nullThe grid of described 9th NMOS tube (MN7) and the 3rd bias voltage VBN3 connect，The drain electrode of the 9th NMOS tube (MN7) is connected with one end of the 5th resistance (r5)，Another termination supply voltage VDD of described 5th resistance (r5)，The source electrode of described 9th NMOS tube (MN7) and the drain electrode of the drain electrode of the 9th PMOS (MP9) and the 6th NMOS tube (MN6) are connected，Input with the first phase inverter (inv1) is connected again，The output of described first phase inverter (inv1) is connected with the input of the second phase inverter (inv2)，The output of described second phase inverter (inv2) is connected with the input of described 3rd phase inverter (inv3)，Described 3rd phase inverter (inv3) is output as OUT，The grid of described tenth NMOS tube (MN10) and the outfan of the first phase inverter (inv1) are connected，The drain electrode of the tenth NMOS tube (MN10) is connected with the drain electrode of the 8th NMOS tube (MN9)，The source electrode of the tenth NMOS tube (MN10) is connected with the drain electrode of described 12nd NMOS tube (MN12)，The grid of described 11st NMOS tube (MN11) and the outfan of the second phase inverter (inv2) are connected，The drain electrode of the 11st NMOS tube (MN11) is connected with the drain electrode of the 7th NMOS tube (MN8)，The source electrode of the 11st NMOS tube (MN11) is connected with the drain electrode of described 13rd NMOS tube (MN13)，The grid of described 12nd NMOS tube (MN12) is connected with the grid of described 13rd NMOS tube (MN13)，All it is connected on the second bias voltage VBN2，The source electrode of described 12nd NMOS tube (MN12) is all connected with GND with the source electrode of described 13rd NMOS tube (MN13).