CN105680835A - Hysteresis comparator applied to RS-485 receiving end - Google Patents

Abstract

The invention discloses a hysteresis comparator applied to an RS-485 receiving end. The hysteresis comparator comprises a voltage dividing circuit, a folded cascade operational amplifier, a polarity exchange switch and a hysteresis voltage control circuit, wherein the voltage dividing circuit is used for performing level linear displacement of two input signals of the hysteresis comparator, and facilitating subsequent circuit processing; the folded cascade operational amplifier is connected with the voltage dividing circuit, and is used for comparing the two signals after level linear displacement; the polarity exchange switch is arranged in the folded cascade operational amplifier, and exchanges polarities of the comparator correspondingly according to digital output results of an external polarity detection system; and the hysteresis voltage control circuit is connected with the folded cascade operational amplifier, and used for adjusting a hysteresis voltage interval. The hysteresis comparator solves the problem that a hysteresis interval is a positive interval after comparator polarity exchange in the nonpolarity RS-485 receiving end, and can ensure that the hysteresis interval of the comparator to be positioned between -200mV and -50mV before and after polarity exchange.

Description

It is applied to the hysteresis comparator of RS-485 receiving terminal

Technical field

The present invention relates to electric energy communication system of power grids field or Analogical Circuit Technique field, particularly relate to a kind of hysteresis comparator being applied to RS-485 receiving terminal.

Background technology

RS-485 is by Electronic Industries Association (EIA) and and a kind of serial interface standard of formulating of Telecommunications Industries Association (TIA). The features such as the strong noise that has RS-485 interface suppresses, relatively high transfer rate, long transmission distance, wide common mode range, RS-485 communication interface chip has the advantages such as easy to control, with low cost simultaneously.

The pin definitions of RS-485 communication interface chip as shown in Figure 2, wherein: RO be receiving terminal output signal; RE is that receiving terminal enables signal; DE is that transmitting terminal enables signal; DI is transmitting terminal input signal; VDD is power supply; A/B is signal pins, when DE, RE are high level " 1 ", as the output pin of balance driver, when DE, RE are 0, as the signal input pin of receiving terminal; GND is ground.

Nonpolarity RS-485 communication interface chip can detect the polarity of A, B signal line automatically, and adjusts at chip internal according to testing result, with original polarized RS-485 chip in pin definitions completely compatible, it may be achieved substitute, do not increase cost.

No. 201220086354.9 utility model patents of China disclose a kind of non-polar 485 chip, it mainly includes differential voltage testing circuit, 5ms integrating circuit, communication polarity identification switch circuit, in the 5ms that voltage when between communication A, the B foot of 485 chips is lasting, when keeping Vab>0, communication polarity identification switch circuit is failure to actuate, and gives tacit consent on the A circuit of communication A foot incoming communication bus of 485 chips, on the B circuit of the communication B foot incoming communication bus of 485 chips; In the 5ms that voltage when between communication A, the B foot of 485 chips is lasting,<when 0, communication polarity identification circuit overturns, and the communication A foot of 485 chips is received in the B bus of communication bus, on the A circuit of the communication B foot incoming communication bus of 485 chips to keep Vab.

Although above-mentioned patented technology provides a kind of non-polar 485 chip, but it has the disadvantage that, when receiving terminal comparator hysteresis interval is between-200mV～-50mV, after the method, comparator hysteresis interval becomes+50mV～+200mV, A/B end, when states such as short circuit, free time, open circuits, is just connecing and can change with RO output in two kinds of situations of reversal connection.

Summary of the invention

In order to solve above-mentioned technical barrier, it is an object of the invention to provide a kind of hysteresis comparator being applied to RS-485 receiving terminal, become positive interval problem with comparator hysteresis interval after solving polarity exchange.

For reaching above-mentioned purpose, a kind of hysteresis comparator being applied to RS-485 receiving terminal of the present invention, including bleeder circuit, folded cascode Op Amp, polarity switch and hysteresis voltage control circuit, bleeder circuit is for carrying out level linear displacement to two of hysteresis comparator input signals, it is simple to subsequent conditioning circuit processes; Folded cascode Op Amp is connected with described bleeder circuit, and two signals after level shift are compared; Polarity switch is in described folded cascode Op Amp, the digital output results according to outside polarity detection system, and comparator polarity is exchanged accordingly; Hysteresis voltage control circuit, is connected with described folded cascode Op Amp, is used for regulating hysteresis voltage interval.

Improving further is that described bleeder circuit contains: the first PMOS, the second PMOS, the 3rd PMOS, the 4th PMOS, and four resistance: the first resistance, the second resistance, the 3rd resistance, the 4th resistance, wherein, the source electrode of described first PMOS and the source electrode of the second PMOS all meet supply voltage VDD, grid meets the first bias voltage VBP1, the drain electrode of this first PMOS is connected with the source electrode of described 3rd PMOS, the drain electrode of this second PMOS is connected with the source electrode of described 4th PMOS, the grid of described 3rd PMOS is connected with drain electrode, again with the first resistance, one end of second resistance is connected, the grid of described 4th PMOS is connected with drain electrode, again with the 3rd resistance, one end of 4th resistance is connected, another termination input signal A of described first resistance, another termination GND of described second resistance, another termination input signal B of described 3rd resistance, another termination GND of described 4th resistance.

Improving further is that described folded cascode Op Amp is by five PMOS: the 5th PMOS, the 6th PMOS, the 7th PMOS, the 8th PMOS, 9th PMOS, four NMOS tube: the 5th NMOS tube, the 6th NMOS tube, 7th NMOS tube, the 8th NMOS tube composition;

The source electrode of described 5th PMOS, the source electrode of described 8th PMOS and the source electrode of described 9th PMOS all meet supply voltage VDD, the grid of the 5th PMOS meets the first bias voltage VBP1, source electrode and the substrate of described 6th PMOS are connected with each other, it is connected with the drain electrode of the 5th PMOS again, source electrode and the substrate of described 7th PMOS are connected with each other, it is connected with the drain electrode of the 5th PMOS again, the source electrode of the grid of the 6th PMOS and the drain electrode of the first PMOS and the 3rd PMOS is connected, the source electrode of the grid of the 7th PMOS and the drain electrode of the second PMOS and the 4th PMOS is connected, the grid of described 7th NMOS tube and the grid of the 8th NMOS tube are connected, all it is connected on the second bias voltage VBN2, the source electrode of the 7th NMOS tube and the source electrode of the 8th NMOS tube are all connected with GND, the grid of described 5th NMOS tube and the grid of the 6th NMOS tube are connected, all it is connected on the 3rd bias voltage VBN3, the source electrode of described 5th NMOS tube and the drain electrode of the 7th NMOS tube are connected, the source electrode of described 6th NMOS tube and the drain electrode of the 8th NMOS tube are connected, described 8th PMOS is connected with the grid of described 9th PMOS, the grid of described 8th PMOS is connected with drain electrode, it is connected with the drain electrode of described 5th NMOS tube again, the drain electrode of described 9th PMOS is connected with the drain electrode of described 6th NMOS tube.

Improving further is that described polarity switch contains: the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube, the digital output signal of described outside polarity detection system is CLK and CLK ', wherein: the drain electrode of described first NMOS tube is connected with the drain electrode of described 3rd NMOS tube, it is connected with the drain electrode of the 6th PMOS again, the drain electrode of described second NMOS tube is connected with the drain electrode of described 4th NMOS tube, it is connected with the drain electrode of the 7th PMOS again, the grid of described first NMOS tube and the grid of the second NMOS tube are connected, all it is connected on CLK, the grid of described 3rd NMOS tube and the grid of the 4th NMOS tube are connected, all it is connected on CLK ', the source electrode of described first NMOS tube and the source electrode of the 4th NMOS tube are connected, it is connected with the drain electrode of the 8th NMOS tube again, the source electrode of described second NMOS tube and the source electrode of the 3rd NMOS tube are connected, it is connected with the drain electrode of the 7th NMOS tube again.

Improve further and be, described hysteresis voltage control circuit contains: the 5th resistance, possibly together with five NMOS tube: the 9th NMOS tube, the tenth NMOS tube, the 11st NMOS tube, the 12nd NMOS tube, the 13rd NMOS tube, possibly together with three phase inverters: the first phase inverter, the second phase inverter, the 3rd phase inverter, wherein: the grid of described 9th NMOS tube and the 3rd bias voltage VBN3 connect, the drain electrode of the 9th NMOS tube is connected with one end of the 5th resistance, another termination supply voltage VDD of described 5th resistance, the drain electrode of the source electrode of described 9th NMOS tube and the drain electrode of the 9th PMOS and the 6th NMOS tube is connected, it is connected with the input of the first phase inverter again, the output of described first phase inverter is connected with the input of the second phase inverter, the output of described second phase inverter is connected with the input of described 3rd phase inverter, described 3rd phase inverter is output as OUT, the grid of described tenth NMOS tube and the outfan of the first phase inverter are connected, the drain electrode of the tenth NMOS tube is connected with the drain electrode of the 8th NMOS tube, the source electrode of the tenth NMOS tube is connected with the drain electrode of described 12nd NMOS tube, the grid of described 11st NMOS tube and the outfan of the second phase inverter are connected, the drain electrode of the 11st NMOS tube is connected with the drain electrode of the 7th NMOS tube, the source electrode of the 11st NMOS tube is connected with the drain electrode of described 13rd NMOS tube, the grid of described 12nd NMOS tube is connected with the grid of described 13rd NMOS tube, all it is connected on the second bias voltage VBN2, the source electrode of described 12nd NMOS tube is all connected with GND with the source electrode of described 13rd NMOS tube.

The invention has the beneficial effects as follows: the present invention proposes a kind of hysteresis comparator being applied to RS-485 receiving terminal, solve the sluggish interval problem for positive interval after comparator polarity in nonpolarity RS-485 receiving terminal exchanges, before and after polarity exchange, can ensure that the sluggish interval of comparator is between-200mV～-50mV.

Accompanying drawing explanation

Fig. 1 is the circuit diagram of the hysteresis comparator of the present invention.

Fig. 2 is the pin definitions of RS-485 communication interface chip.

Detailed description of the invention

Describe the present invention below with reference to the accompanying drawings and in conjunction with the embodiments in detail.

Shown in reference accompanying drawing 1, a kind of hysteresis comparator being applied to RS-485 receiving terminal of the present invention, including bleeder circuit, folded cascode Op Amp, polarity switch and hysteresis voltage control circuit:

Described bleeder circuit contains: the first PMOS MP6, second PMOS MP7, 3rd PMOS MP4, 4th PMOS MP5, and four resistance: the first resistance r1, second resistance r2, 3rd resistance r3, 4th resistance r4, wherein, the source electrode of described first PMOS MP6 and the source electrode of the second PMOS MP7 all meet supply voltage VDD, grid meets the first bias voltage VBP1, the drain electrode of this first PMOS MP6 is connected with the source electrode of described 3rd PMOS MP4, the drain electrode of this second PMOS MP7 is connected with the source electrode of described 4th PMOS MP5, the grid of described 3rd PMOS MP4 is connected with drain electrode, again with the first resistance r1, one end of second resistance r2 is connected, the grid of described 4th PMOS MP5 is connected with drain electrode, again with the 3rd resistance r3, one end of 4th resistance r4 is connected, another termination input signal A of described first resistance r1, another termination GND of described second resistance r2, another termination input signal B of described 3rd resistance r3, another termination GND of described 4th resistance r4.

Described folded cascode Op Amp and polarity switch circuit contain: five PMOS: the 5th PMOS MP3, 6th PMOS MP1, 7th PMOS MP2, 8th PMOS MP8, 9th PMOS MP9, possibly together with: eight NMOS tube: the first NMOS tube MN1, second NMOS tube MN2, 3rd NMOS tube MN3, 4th NMOS tube MN4, 5th NMOS tube MN5, 6th NMOS tube MN6, 7th NMOS tube MN8, 8th NMOS tube MN9, wherein: the source electrode of described 5th PMOS MP3, the source electrode of described 8th PMOS MP8 and the source electrode of described 9th PMOS MP9 all meet supply voltage VDD, the grid of the 5th PMOS MP3 connects the first bias voltage, source electrode and the substrate of described 6th PMOS MP1 are connected with each other, it is connected with the drain electrode of the 5th PMOS MP3 again, source electrode and the substrate of described 7th PMOS MP2 are connected with each other, it is connected with the drain electrode of the 5th PMOS MP3 again, the source electrode of the grid of the 6th PMOS MP1 and the drain electrode of the first PMOS MP6 and the 3rd PMOS MP4 is connected, the source electrode of the grid of the 7th PMOS MP2 and the drain electrode of the second PMOS MP7 and the 4th PMOS MP5 is connected, the drain electrode of described first NMOS tube MN1 is connected with the drain electrode of described 3rd NMOS tube MN3, it is connected with the drain electrode of the 6th PMOS MP1 again, the drain electrode of described second NMOS tube MN2 is connected with the drain electrode of described 4th NMOS tube MN4, it is connected with the drain electrode of the 7th PMOS MP2 again, the grid of described first NMOS tube MN1 and the grid of the second NMOS tube MN2 are connected, all it is connected on CLK, the grid of described 3rd NMOS tube MN3 and the grid of the 4th NMOS tube MN4 are connected, all it is connected on CLK ', the source electrode of described first NMOS tube MN1 and the source electrode of the 4th NMOS tube MN4 are connected, it is connected with the drain electrode of the 8th NMOS tube MN9 again, the source electrode of described second NMOS tube MN2 and the source electrode of the 3rd NMOS tube MN3 are connected, it is connected with the drain electrode of the 7th NMOS tube MN8 again, the grid of described 7th NMOS tube MN8 and the grid of the 8th NMOS tube MN9 are connected, all it is connected on the second bias voltage VBN2, the source electrode of the 7th NMOS tube MN8 and the source electrode of the 8th NMOS tube MN9 are all connected with GND, the grid of described 5th NMOS tube MN5 and the grid of the 6th NMOS tube MN6 are connected, all it is connected on the 3rd bias voltage VBN3, the source electrode of described 5th NMOS tube MN5 and the drain electrode of the 7th NMOS tube MN8 are connected, the source electrode of described 6th NMOS tube MN6 and the drain electrode of the 8th NMOS tube MN9 are connected, the grid of described 8th PMOS MP8 and described 9th PMOS MP9 is connected, the grid of described 8th PMOS MP8 is connected with drain electrode, it is connected with the drain electrode of described 5th NMOS tube MN5 again, the drain electrode of described 9th PMOS MP9 is connected with the drain electrode of described 6th NMOS tube MN6.

Described hysteresis voltage control circuit contains: the 5th resistance r5, possibly together with five NMOS tube: the 9th NMOS tube MN7, tenth NMOS tube MN10, 11st NMOS tube MN11, 12nd NMOS tube MN12, 13rd NMOS tube MN13, possibly together with three phase inverters: the first phase inverter inv1, second phase inverter inv2, 3rd phase inverter inv3, wherein: the grid of described 9th NMOS tube MN7 and the 3rd bias voltage VBN3 connect, the drain electrode of the 9th NMOS tube MN7 is connected with one end of the 5th resistance r5, another termination supply voltage VDD of described 5th resistance r5, the drain electrode of the source electrode of described 9th NMOS tube MN7 and the drain electrode of the 9th PMOS MP9 and the 6th NMOS tube MN6 is connected, it is connected with the input of the first phase inverter inv1 again, the output of described first phase inverter inv1 is connected with the input of the second phase inverter inv2, the output of described second phase inverter inv2 is connected with the input of described 3rd phase inverter inv3, described 3rd phase inverter inv3 is output as OUT, the grid of described tenth NMOS tube MN10 and the outfan of the first phase inverter inv1 are connected, the drain electrode of the tenth NMOS tube MN10 is connected with the drain electrode of the 8th NMOS tube MN9, the source electrode of the tenth NMOS tube MN10 is connected with the drain electrode of described 12nd NMOS tube MN12, the grid of described 11st NMOS tube MN11 and the outfan of the second phase inverter inv2 are connected, the drain electrode of the 11st NMOS tube MN11 is connected with the drain electrode of the 7th NMOS tube MN8, the source electrode of the 11st NMOS tube MN11 is connected with the drain electrode of described 13rd NMOS tube MN13, the grid of described 12nd NMOS tube MN12 is connected with the grid of described 13rd NMOS tube MN13, all it is connected on the second bias voltage VBN2, the source electrode of described 12nd NMOS tube MN12 is all connected with GND with the source electrode of described 13rd NMOS tube MN13.

With reference to shown in accompanying drawing 1, in order to seek the positive and negative turn threshold point of comparator, when CLK is that high level makes MN1 and MN2 turn on, when CLK ' makes MN3 and MN4 turn off for low level, A terminal voltage is allowed to be fixed on 0V, B end inputs the voltage being gradually reduced from 12V to-7V, MP1 conducting during beginning, MP2 almost ends, the electric current of MP3 nearly all flows through from MP1, the drain terminal voltage of MN6 is high, the electric current of MP9 and MN7 is all almost 0, the electric current of MN5 all flows to MN8, the electric current of MN11 branch road is only small, along with B terminal voltage continues to reduce, the electric current of MP2 slowly increases, the electric current of MP1 reduces, MN5 drain terminal voltage is reduced, the electric current of MP8 reduces, MP9, the electric current of MN5 all slowly increases, until when the electric current of MP8 and MP9 is equal, phase inverter overturns, after upset, the electric current of MP9 reduces, the electric current of MN7 increases, correspondence can be tried to achieve positive turn threshold point and is:

$V_{TH+}=\frac{\sqrt{I_{MP3}-I_{MN12}-I_{MN9}+I_{MN8}}-\sqrt{I_{MP3}+I_{MN12}+I_{MN9}-I_{MN8}}}{\sqrt{{\mathrm{\&mu;}}_p{C}_{ox}{(W/L)}_{MP1,MP2}}}$

In like manner can try to achieve negative turn threshold point is:

$V_{TH-}=\frac{\sqrt{I_{MP3}+I_{MN13}-I_{MN9}+I_{MN8}}-\sqrt{I_{MP3}-I_{MN13}+I_{MN9}-I_{MN8}}}{\sqrt{{\mathrm{\&mu;}}_p{C}_{ox}{(W/L)}_{MP1,MP2}}}$

When polarity needs to overturn, A/B port exchanges, and simultaneously CLK should be low level MN1 and MN2 is turned off, and CLK ' should be high level and MN3 and MN4 is turned on, and so can make the positive and negative turn threshold voltage after polarity upset is all still negative value.

It is understandable that; the foregoing is only the preferred embodiments of the present invention; it is not limited to the present invention; alteration switch in the present invention is not limited to nmos switch; can also be PMOS switch or transmission gate switch etc.; those skilled in the art can be equal to replacement according to technical scheme and inventive concept thereof or be changed, and all these change or replace the scope of the claims that all should belong to attached by the present invention.

Claims (5)

1. the hysteresis comparator being applied to RS-485 receiving terminal, it is characterised in that including:

Bleeder circuit, for carrying out level linear displacement to two of hysteresis comparator input signals, it is simple to subsequent conditioning circuit processes;

Folded cascode Op Amp, is connected with described bleeder circuit, and two signals after level shift are compared;

Polarity switch, is in described folded cascode Op Amp, the digital output results according to outside polarity detection system, and comparator polarity is exchanged accordingly;

Hysteresis voltage control circuit, is connected with described folded cascode Op Amp, is used for regulating hysteresis voltage interval.

2. hysteresis comparator as claimed in claim 1, it is characterized in that: described bleeder circuit is by the first PMOS (MP6), second PMOS (MP7), 3rd PMOS (MP4), 4th PMOS (MP5), and four resistance: the first resistance (r1), the second resistance (r2), the 3rd resistance (r3), the 4th resistance (r4) composition;

The source electrode of described first PMOS (MP6) and the source electrode of the second PMOS (MP7) all meet supply voltage VDD, grid meets the first bias voltage VBP1, the drain electrode of this first PMOS (MP6) is connected with the source electrode of described 3rd PMOS (MP4), the drain electrode of this second PMOS (MP7) is connected with the source electrode of described 4th PMOS (MP5), the grid of described 3rd PMOS (MP4) is connected with drain electrode, again with the first resistance (r1), one end of second resistance (r2) is connected, the grid of described 4th PMOS (MP5) is connected with drain electrode, again with the 3rd resistance (r3), one end of 4th resistance (r4) is connected, another termination input signal A of described first resistance (r1), another termination GND of described second resistance (r2), another termination input signal B of described 3rd resistance (r3), another termination GND of described 4th resistance (r4).

3. hysteresis comparator as claimed in claim 2, it is characterized in that: described folded cascode Op Amp is by five PMOS: the 5th PMOS (MP3), the 6th PMOS (MP1), the 7th PMOS (MP2), the 8th PMOS (MP8), the 9th PMOS (MP9), four NMOS tube: the 5th NMOS tube (MN5), the 6th NMOS tube (MN6), the 7th NMOS tube (MN8), the 8th NMOS tube (MN9) composition;

The source electrode of described 5th PMOS (MP3), the source electrode of described 8th PMOS (MP8) and the source electrode of described 9th PMOS (MP9) all meet supply voltage VDD, the grid of the 5th PMOS (MP3) meets the first bias voltage VBP1, source electrode and the substrate of described 6th PMOS (MP1) are connected with each other, it is connected with the drain electrode of the 5th PMOS (MP3) again, source electrode and the substrate of described 7th PMOS (MP2) are connected with each other, it is connected with the drain electrode of the 5th PMOS (MP3) again, the source electrode of the described grid of the 6th PMOS (MP1) and the drain electrode of the first PMOS (MP6) and the 3rd PMOS (MP4) is connected, the source electrode of the grid of the 7th PMOS (MP2) and the drain electrode of the second PMOS (MP7) and the 4th PMOS (MP5) is connected, the grid of described 7th NMOS tube (MN8) and the grid of the 8th NMOS tube (MN9) are connected, all it is connected on the second bias voltage VBN2, the source electrode of the 7th NMOS tube (MN8) and the source electrode of the 8th NMOS tube (MN9) are all connected with GND, the grid of described 5th NMOS tube (MN5) and the grid of the 6th NMOS tube (MN6) are connected, all it is connected on the 3rd bias voltage VBN3, the source electrode of described 5th NMOS tube (MN5) and the drain electrode of the 7th NMOS tube (MN8) are connected, the source electrode of described 6th NMOS tube (MN6) and the drain electrode of the 8th NMOS tube (MN9) are connected, described 8th PMOS (MP8) is connected with the grid of described 9th PMOS (MP9), the grid of described 8th PMOS (MP8) is connected with drain electrode, it is connected with the drain electrode of described 5th NMOS tube (MN5) again, the drain electrode of described 9th PMOS (MP9) is connected with the drain electrode of described 6th NMOS tube (MN6).

4. hysteresis comparator as claimed in claim 3, it is characterized in that: described polarity switch is by the first NMOS tube (MN1), second NMOS tube (MN2), the 3rd NMOS tube (MN3), the 4th NMOS tube (MN4) composition; The digital output signal of described outside polarity detection system is CLK and CLK ';

The drain electrode of described first NMOS tube (MN1) is connected with the drain electrode of described 3rd NMOS tube (MN3), it is connected with the drain electrode of the 6th PMOS (MP1) again, the drain electrode of described second NMOS tube (MN2) is connected with the drain electrode of described 4th NMOS tube (MN4), it is connected with the drain electrode of the 7th PMOS (MP2) again, the grid of described first NMOS tube (MN1) and the grid of the second NMOS tube (MN2) are connected, all it is connected on CLK, the grid of described 3rd NMOS tube (MN3) and the grid of the 4th NMOS tube (MN4) are connected, all it is connected on CLK ', the source electrode of described first NMOS tube (MN1) and the source electrode of the 4th NMOS tube (MN4) are connected, it is connected with the drain electrode of the 8th NMOS tube (MN9) again, the source electrode of described second NMOS tube (MN2) and the source electrode of the 3rd NMOS tube (MN3) are connected, it is connected with the drain electrode of the 7th NMOS tube (MN8) again.

5. the hysteresis comparator as described in claim 3 or 4, it is characterized in that: described hysteresis voltage control circuit is by the 5th resistance (r5), five NMOS tube: the 9th NMOS tube (MN7), the tenth NMOS tube (MN10), the 11st NMOS tube (MN11), the 12nd NMOS tube (MN12), the 13rd NMOS tube (MN13), three phase inverters: the first phase inverter (inv1), second phase inverter (inv2), the 3rd phase inverter (inv3) composition;

The grid of described 9th NMOS tube (MN7) and the 3rd bias voltage VBN3 connect, the drain electrode of the 9th NMOS tube (MN7) is connected with one end of the 5th resistance (r5), another termination supply voltage VDD of described 5th resistance (r5), the drain electrode of the described source electrode of the 9th NMOS tube (MN7) and the drain electrode of the 9th PMOS (MP9) and the 6th NMOS tube (MN6) is connected, it is connected with the input of the first phase inverter (inv1) again, the output of described first phase inverter (inv1) is connected with the input of the second phase inverter (inv2), the output of described second phase inverter (inv2) is connected with the input of described 3rd phase inverter (inv3), described 3rd phase inverter (inv3) is output as OUT, the grid of described tenth NMOS tube (MN10) and the outfan of the first phase inverter (inv1) are connected, the drain electrode of the tenth NMOS tube (MN10) is connected with the drain electrode of the 8th NMOS tube (MN9), the source electrode of the tenth NMOS tube (MN10) is connected with the drain electrode of described 12nd NMOS tube (MN12), the grid of described 11st NMOS tube (MN11) and the outfan of the second phase inverter (inv2) are connected, the drain electrode of the 11st NMOS tube (MN11) is connected with the drain electrode of the 7th NMOS tube (MN8), the source electrode of the 11st NMOS tube (MN11) is connected with the drain electrode of described 13rd NMOS tube (MN13), the grid of described 12nd NMOS tube (MN12) is connected with the grid of described 13rd NMOS tube (MN13), all it is connected on the second bias voltage VBN2, the source electrode of described 12nd NMOS tube (MN12) is all connected with GND with the source electrode of described 13rd NMOS tube (MN13).