CN210351094U

CN210351094U - Operational amplifier circuit

Info

Publication number: CN210351094U
Application number: CN201921183173.6U
Authority: CN
Inventors: 唐太平
Original assignee: Individual
Current assignee: Individual
Priority date: 2019-07-25
Filing date: 2019-07-25
Publication date: 2020-04-17
Anticipated expiration: 2029-07-25

Abstract

The utility model discloses an operational amplifier circuit, common mode feedback circuit is put to fortune including interconnect, common mode stability compensating circuit, differential signal amplifier circuit, second level circuit quiescent current control circuit and differential mode stability compensating circuit, differential signal amplifier circuit includes that fortune is put first order circuit and fortune and is put second level circuit, fortune is put common mode feedback circuit and is included operational amplifier, the MOS device of being connected with the operational amplifier output, fifth resistance and the sixth resistance of being connected with operational amplifier in-phase input end respectively, common mode stability compensating circuit includes third electric capacity and third resistance and the fourth resistance of being connected with third electric capacity respectively. The utility model discloses provide the two-stage at signal path and enlarge, guarantee sufficient direct current gain, pass through NMOS pipe output after the two-stage is enlargied, make its area load capacity to back stage circuit strengthen greatly, the input reactance of back stage almost puts direct current gain, bandwidth and stability to this fortune and does not produce the influence, can realize the enlargiing and tracking to differential signal.

Description

Operational amplifier circuit

Technical Field

The utility model belongs to the technical field of the analog circuit, concretely relates to operational amplifier circuit.

Background

The operational amplifier is widely applied to a feedback system as a basic circuit unit, realizes accurate amplification or tracking of an input signal, and becomes an important basis and a component of an information system. In order to meet different application requirements, the industry and the academia have been taking the same as a key research object and have conducted intensive research, and various architectures are infinite, but the dc gain, the bandwidth, the stability and the loading capacity of the architecture are often compromised and cannot be considered at the same time.

SUMMERY OF THE UTILITY MODEL

The utility model aims at solving the technical problem that exists among the prior art, provide an operational amplifier circuit that has enough direct current gain, can strengthen the band-carrying capacity greatly and do not exert an influence to bandwidth and stability.

In order to achieve the above purpose, the utility model adopts the following technical scheme: an operational amplifier circuit comprises an operational amplifier common mode feedback loop, a common mode stability compensation circuit, a differential signal amplification circuit, a second stage circuit quiescent current control circuit and a differential mode stability compensation circuit which are connected with each other, the differential signal amplifying circuit comprises an operational amplifier first-stage circuit and an operational amplifier second-stage circuit, the operational amplifier common-mode feedback loop comprises an operational amplifier, an MOS device connected with the output end of the operational amplifier, a fifth resistor and a sixth resistor which are respectively connected with the non-inverting input end of the operational amplifier, the common mode stability compensation circuit comprises a third capacitor, a third resistor and a fourth resistor which are respectively connected with the third capacitor, the differential mode stability compensation circuit comprises a first resistor, a first capacitor, a second resistor and a second capacitor, wherein the first resistor is connected with the first capacitor in series, and the second resistor is connected with the second capacitor in series.

The operational amplifier circuit further comprises an operational amplifier, an analog circuit power supply, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a first capacitor, a second capacitor and a third capacitor, wherein a source electrode of the first PMOS tube, a source electrode of the second PMOS tube, a source electrode of the third PMOS tube, a source electrode of the fourth PMOS tube, a source electrode of the fifth PMOS tube, a source electrode of the sixth PMOS tube, a drain electrode of the sixth NMOS tube, a drain electrode of the ninth NMOS tube, and a fourteenth NMOS tube, The drain electrode of the fifteenth NMOS tube is respectively connected with an analog circuit power supply, the source electrode of the third NMOS tube, the source electrode of the fourth NMOS tube, the source electrode of the seventh NMOS tube, the source electrode of the eighth NMOS tube, the source electrode of the tenth NMOS tube, the source electrode of the eleventh NMOS tube and the source electrode of the twelfth NMOS tube are respectively connected with an analog ground, the non-inverting input end of the operational amplifier is an output common-mode voltage control end, the output end of the operational amplifier is respectively connected with the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube, the drain electrode of the first PMOS tube is respectively connected with the drain electrode of the third PMOS tube, one end of the third resistor, one end of the first capacitor, the drain electrode of the first NMOS tube and the grid electrode of the sixth NMOS tube, the other end of the first capacitor is connected with one end of the first resistor, the other end of the first resistor is connected with one end of the sixth resistor, and the other end of the sixth resistor is respectively connected with one end of the fifth resistor and the inverting input end, a differential signal output end is arranged between the other end of the fifth resistor and the sixth resistor, the other end of the fifth resistor is connected with one end of the second resistor, the other end of the second resistor is connected with one pole of the second capacitor, the other pole of the second capacitor is respectively connected with one end of the fourth resistor, the drain electrode of the second PMOS tube, the drain electrode of the fifth PMOS tube, the grid electrode of the fourteenth NMOS tube and the drain electrode of the second NMOS tube, the other end of the fourth resistor is respectively connected with the other end of the third resistor and one pole of the third capacitor, the other pole of the third capacitor is respectively connected with the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube, a first bias voltage input end is arranged between the grid electrode of the fifth PMOS tube and the grid electrode of the third PMOS tube, a differential input signal end is arranged between the grid electrode of the second NMOS tube and the grid electrode of the first NMOS tube, and the source electrode of the second NMOS tube is connected with the drain electrode of the third NMOS tube, the grid electrode of the third NMOS tube is a second bias voltage input end, the source electrode of the fourteenth NMOS tube is connected with the drain electrode of the tenth NMOS tube, the grid electrode of the tenth NMOS tube is respectively connected with the grid electrode of the eleventh NMOS tube and the grid electrode of the twelfth NMOS tube, the drain electrode of the eleventh NMOS tube is respectively connected with the drain electrode of the sixth PMOS tube and the grid electrode of the fifteenth NMOS tube, the source electrode of the fifteenth NMOS tube is respectively connected with the drain electrode of the twelfth NMOS tube and the other end of the fifth resistor, the source electrode of the sixth NMOS tube is connected with the drain electrode of the fourth NMOS tube, the grid electrode of the fourth NMOS tube is respectively connected with the grid electrode of the seventh NMOS tube and the grid electrode of the eighth NMOS tube, the drain electrode of the seventh NMOS tube is respectively connected with the drain electrode of the fourth PMOS tube and the grid electrode of the ninth NMOS tube, a third bias voltage input end is arranged between the grid electrode of the fourth PMOS tube and the grid electrode of the sixth PMOS tube, and the source electrode of the ninth NMOS tube is respectively connected with the drain electrode of the eighth NMOS tube and one end of the sixth resistor.

The utility model discloses relative prior art has following beneficial effect: the utility model discloses an operational amplifier circuit includes that the common mode feedback circuit is put to fortune, common mode stability compensating circuit, differential signal amplifier circuit, second level circuit quiescent current control circuit and differential mode stability compensating circuit, and wherein the differential signal amplifier circuit includes that the second level circuit is put to fortune first order circuit and fortune, specifically says: the operational amplifier, a first PMOS tube, a second PMOS tube, MOS devices from the first PMOS tube and the second PMOS tube to the differential signal output end, a fifth resistor and a sixth resistor jointly form an operational amplifier common-mode feedback loop, and the common-mode level of the differential signal output end is determined to be equal to the level of the output common-mode voltage control end; a common mode stability compensation circuit formed by the third resistor, the fourth resistor and the third capacitor provides stability compensation for an operational amplifier common mode feedback loop; the differential mode stability compensation circuit comprises a first NMOS tube, a second NMOS tube and a third NMOS tube, wherein MOS devices from the first NMOS tube and the second NMOS tube to a differential signal output end respectively form a differential signal amplifying circuit together; the first NMOS tube, the second NMOS tube, the third NMOS tube, the first PMOS tube, the second PMOS tube, the third PMOS tube and the fifth PMOS tube form an operational amplifier first-stage circuit, the third NMOS tube provides a first-stage static bias current, and the third PMOS tube and the fifth PMOS tube provide partial pull-up currents; a sixth NMOS tube, a fourth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a fourth PMOS tube, a fourteenth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a fifteenth NMOS tube and a sixth PMOS tube form an operational amplifier second-stage circuit, the pull-up and pull-down functions of an output stage are realized, and static bias currents are provided by the fourth PMOS tube and the sixth PMOS tube respectively; by means of an operational amplifier common mode feedback loop, the width-length ratio of the eighth NMOS transistor, the fourth NMOS transistor and the seventh NMOS transistor and the quiescent current flowing through the fourth PMOS transistor determine the quiescent current flowing through the eighth NMOS transistor and the fourth NMOS transistor; by means of an operational amplifier common mode feedback loop, the width-length ratio of a tenth NMOS transistor, a twelfth NMOS transistor and an eleventh NMOS transistor and the quiescent current flowing through a sixth PMOS transistor determine the quiescent current flowing through the tenth NMOS transistor and the twelfth NMOS transistor; the second bias voltage input end, the third bias voltage input end, the first bias voltage input end are respectively a third NMOS tube, a fourth PMOS tube, a sixth PMOS tube, a third PMOS tube, and a fifth PMOS tube for providing corresponding bias currents. The utility model discloses provide the two-stage at signal path and enlarge, guaranteed sufficient direct current gain, pass through NMOS pipe output after the two-stage is enlargied, make its area load capacity to back stage circuit strengthen greatly, the input reactance of back stage almost puts direct current gain, bandwidth and stability to this fortune and does not exert an influence, cooperation peripheral circuit can realize the enlarging and tracking to differential signal.

Drawings

Fig. 1 is a schematic circuit diagram of the present invention.

The utility model discloses the reference sign is as follows: OP1, operational amplifier; AVCC, analog circuit power supply; AGND, simulated ground; MP1, a first PMOS tube; MP2 and a second PMOS tube; MP3 and a third PMOS tube; MP4 and a fourth PMOS tube; MP5 and a fifth PMOS tube; MP6 and a sixth PMOS tube; MN1 and a first NMOS tube; MN2 and a second NMOS tube; MN3 and a third NMOS tube; MN4 and a fourth NMOS tube; MN5 and a fifth NMOS transistor; MN6 and a sixth NMOS transistor; MN7 and a seventh NMOS transistor; MN8 and an eighth NMOS transistor; MN9 and a ninth NMOS transistor; MN10 and a tenth NMOS transistor; MN11 and an eleventh NMOS tube; MN12 and a twelfth NMOS tube; MN13, a thirteenth NMOS tube; MN14 and a fourteenth NMOS tube; MN15, a fifteenth NMOS transistor; r1, a first resistor; r2, a second resistor; r3, third resistor; r4, fourth resistor; r5, fifth resistor; r6, sixth resistor; c1, a first capacitance; c2, a second capacitor; c3, a third capacitance; vcom, output common mode voltage control terminal; vpb2, a first bias voltage input terminal; vnb1, a second bias voltage input; vpb1, a third bias voltage input terminal.

Detailed Description

The present invention will be further described with reference to the accompanying drawings and the following detailed description.

As shown in fig. 1, an operational amplifier circuit comprises an operational amplifier common-mode feedback loop, a common-mode stability compensation circuit, a differential signal amplification circuit, a second-stage circuit quiescent current control circuit and a differential-mode stability compensation circuit, which are connected with each other, wherein the differential signal amplification circuit comprises an operational amplifier first-stage circuit and an operational amplifier second-stage circuit, the operational amplifier common-mode feedback loop comprises an operational amplifier OP1, the MOS device is connected with the output end of an operational amplifier OP1, and the fifth resistor R5 and the sixth resistor R6 are respectively connected with the non-inverting input end of the operational amplifier OP1, the common mode stability compensation circuit comprises a third capacitor C3, and a third resistor R3 and a fourth resistor R4 are respectively connected with a third capacitor C3, the differential mode stability compensation circuit comprises a first resistor R1, a first capacitor C1, a second resistor R2 and a second capacitor C2, the first resistor R1 is connected with the first capacitor C1 in series, and the second resistor R2 is connected with the second capacitor C2 in series. Specifically, the operational amplifier circuit includes an operational amplifier OP, an analog circuit power supply AVCC, a first PMOS transistor MP, a second PMOS transistor MP, a third PMOS transistor MP, a fourth PMOS transistor MP, a fifth PMOS transistor MP, a sixth PMOS transistor MP, a first NMOS transistor MN, a second NMOS transistor MN, a third NMOS transistor MN, a fourth NMOS transistor MN, a fifth NMOS transistor MN, a sixth NMOS transistor MN, a seventh NMOS transistor MN, an eighth NMOS transistor MN, a ninth NMOS transistor MN, a tenth NMOS transistor MN, an eleventh NMOS transistor MN, a twelfth NMOS transistor MN, a thirteenth NMOS transistor MN, a fourteenth NMOS transistor MN, a fifteenth NMOS transistor MN, a first resistor R, a second resistor R, a third resistor R, a fourth resistor R, a fifth resistor R, a sixth resistor R, a first capacitor C, a second capacitor C, a third capacitor C, a source electrode of the first PMOS transistor MP, a source electrode of the second PMOS transistor MP, a source electrode of the third PMOS transistor MP, a source electrode of the fourth PMOS transistor MP, a source electrode of the fifth NMOS transistor MP, a PMOS transistor MP, a source electrode of the second capacitor C, a third capacitor C, a second capacitor C, a source of a sixth PMOS transistor MP6, a drain of a sixth NMOS transistor MN6, a drain of a ninth NMOS transistor MN9, a drain of a fourteenth NMOS transistor MN14, and a drain of a fifteenth NMOS transistor MN15 are respectively connected to the analog circuit power supply AVCC, a source of a third NMOS transistor MN3, a source of a fourth NMOS transistor MN4, a source of a seventh NMOS transistor MN7, a source of an eighth NMOS transistor MN8, a source of a tenth NMOS transistor MN10, a source of an eleventh NMOS transistor MN11, and a source of a twelfth NMOS transistor MN12 are respectively connected to the analog ground AGND, a non-inverting input terminal of the operational amplifier 1 is the output common mode voltage control terminal Vcom, an output terminal of the operational amplifier OP1 is respectively connected to a gate of the first PMOS transistor MP1 and a gate of the second PMOS transistor MP2, a drain of the first PMOS transistor MP1 is respectively connected to a drain of the third PMOS transistor MP3, an end of the third resistor R3, an output terminal of the first capacitor C1, a drain of the first PMOS transistor MN 6862, a gate of the first NMOS transistor MN 828653, and another drain of the first NMOS transistor MN 828653, the other end of the first resistor R1 is connected to one end of a sixth resistor R6, the other end of the sixth resistor R6 is respectively connected to one end of a fifth resistor R5 and the inverting input terminal of the operational amplifier OP1, a differential signal output terminal vo +/vo is provided between the other end of the fifth resistor R5 and the sixth resistor R6, the other end of the fifth resistor R5 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to one end of a second capacitor C2, the other end of the second capacitor C2 is respectively connected to one end of a fourth resistor R4, the drain of the second PMOS transistor MP2, the drain of the fifth PMOS transistor MP5, the gate of the fourteenth NMOS transistor MN14 and the drain of the second NMOS transistor MN2, the other end of the fourth resistor R4 is respectively connected to the other end of the third resistor R3 and one end of the gate of the third capacitor C3, the other end of the third capacitor C3 is respectively connected to the gates MP1 of the first PMOS transistor MP1 and the second PMOS transistor MP2, a first bias voltage input end Vpb2 is arranged between the grid of the fifth PMOS transistor MP5 and the grid of the third PMOS transistor MP3, a differential input signal end v +/v is arranged between the grid of the second NMOS transistor MN2 and the grid of the first NMOS transistor MN1, the source of the second NMOS transistor MN2 is connected with the source of the first NMOS transistor MN1 and then connected with the drain of the third NMOS transistor MN3, the grid of the third NMOS transistor MN3 is a second bias voltage input end Vnb1, the source of the fourteenth NMOS transistor MN14 is connected with the drain of the tenth NMOS transistor MN10, the grid of the tenth NMOS transistor MN10 is respectively connected with the grid of the eleventh NMOS transistor MN11 and the grid of the twelfth NMOS transistor MN12, the drain of the eleventh NMOS transistor MN11 is respectively connected with the drain of the sixth PMOS transistor MP6 and the grid of the fifteenth NMOS transistor MN15, the source of the fifteenth NMOS transistor MN15 is respectively connected with the drain of the twelfth NMOS transistor MN 6324 and the drain of the sixth NMOS transistor MN 599, the gate of the fourth NMOS transistor MN4 is connected to the gates of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8, the drain of the seventh NMOS transistor MN7 is connected to the drain of the fourth PMOS transistor MP4 and the gate of the ninth NMOS transistor MN9, a third bias voltage input terminal Vpb1 is disposed between the gate of the fourth PMOS transistor MP4 and the gate of the sixth PMOS transistor MP6, and the source of the ninth NMOS transistor MN9 is connected to the drain of the eighth NMOS transistor MN8 and one end of the sixth resistor R6.

When the operational amplifier is used, the operational amplifier OP1, the first PMOS tube MP1 and the second PMOS tube MP2 respectively form MOS devices from the first PMOS tube MP1 and the second PMOS tube MP2 to the differential signal output end vo +/vo-, the fifth resistor R5 and the sixth resistor R6 jointly form an operational amplifier common-mode feedback loop, and the common-mode level of the differential signal output end vo +/vo-is determined to be equal to the level of the output common-mode voltage control end Vcom; a common mode stability compensation circuit formed by the third resistor R3, the fourth resistor R4 and the third capacitor C3 provides stability compensation for an operational amplifier common mode feedback loop; the differential mode stability compensation circuit comprises a first NMOS tube MN1, a second NMOS tube MN2 and a third NMOS tube MN3, wherein MOS devices from the first NMOS tube MN1 and the second NMOS tube MN2 to a differential signal output end vo +/vo-respectively form a differential signal amplification circuit, and the differential mode stability compensation circuit formed by a first resistor R1, a first capacitor C1, a second resistor R2 and a second capacitor C2 provides differential mode stability compensation; the first NMOS tube MN1, the second NMOS tube MN2, the third NMOS tube MN3, the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3 and the fifth PMOS tube MP5 form an operational amplifier first-stage circuit, the third NMOS tube MN3 provides first-stage static bias current, and the third PMOS tube MP3 and the fifth PMOS tube MP5 provide partial pull-up current; an operational amplifier second-stage circuit is formed by a sixth NMOS transistor MN6, a fourth NMOS transistor MN4, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a fourth PMOS transistor MP4, a fourteenth NMOS transistor MN14, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a fifteenth NMOS transistor MN15 and a sixth PMOS transistor MP6, the pull-up and pull-down functions of an output stage are realized, and static bias currents are provided by the fourth PMOS transistor MP4 and the sixth PMOS transistor MP6 respectively; by means of the operational amplifier common mode feedback loop, the width-to-length ratios of the eighth NMOS transistor MN8, the fourth NMOS transistor MN4 and the seventh NMOS transistor MN7 and the quiescent current flowing through the fourth PMOS transistor MP4 determine the quiescent current flowing through the eighth NMOS transistor MN8 and the fourth NMOS transistor MN 4; by means of the operational amplifier common mode feedback loop, the width-to-length ratios of the tenth NMOS transistor MN10, the twelfth NMOS transistor MN12 and the eleventh NMOS transistor MN11 and the quiescent current flowing through the sixth PMOS transistor MP6 determine the quiescent current flowing through the tenth NMOS transistor MN10 and the twelfth NMOS transistor MN 12; the second bias voltage input terminal Vnb1, the third bias voltage input terminal Vpb1, and the first bias voltage input terminal Vpb2 are respectively a third NMOS transistor MN3, a fourth PMOS transistor MP4, a sixth PMOS transistor MP6, a third PMOS transistor MP3, and a fifth PMOS transistor MP5 for providing corresponding bias currents. After the input differential signal is added to the differential input signal end v +/v-, the signal passes through the differential signal amplifying circuit, and the differential signal output end vo +/vo-can generate an output differential signal.

The utility model discloses an one end (the left end in the circuit diagram) of third resistance R3 among the common mode stability compensating circuit can be directly connected to B1 in FIG. 1, B2 position department and the other end (the left end in the circuit diagram) of first resistance R1, and one end (the right-hand member in the circuit diagram) of fourth resistance R4 can be directly connected to A1, A2 position department and the one end (the right-hand member in the circuit diagram) of second resistance R2. The other end (left end in the circuit diagram) of the first resistor R1 in the differential mode stability compensation circuit may be directly connected to positions B1 and B2, and one end (right end in the circuit diagram) of the second resistor R2 may be directly connected to positions a1 and a 2. In addition, in the operational amplifier circuit of the present invention, the first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 can be replaced by corresponding PNP triodes and other corresponding equivalent functional components; the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4, the sixth NMOS transistor MN6, the seventh NMOS transistor MN7, the eighth NMOS transistor MN8, the ninth NMOS transistor MN9, the tenth NMOS transistor MN10, the eleventh NMOS transistor MN11, the twelfth NMOS transistor MN12, the fourteenth NMOS transistor MN14 and the fifteenth NMOS transistor MN15 can be replaced by corresponding NPN triodes and other equivalent components; the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the fifth resistor R5 and the sixth resistor R6 can also be replaced by MOS transistors or corresponding equivalent functional components.

Claims

1. An operational amplifier circuit, characterized by: the operational amplifier comprises an operational amplifier common-mode feedback loop, a common-mode stability compensation circuit, a differential signal amplification circuit, a second-stage circuit quiescent current control circuit and a differential mode stability compensation circuit which are connected with each other, wherein the differential signal amplification circuit comprises an operational amplifier (OP 1), a MOS device connected with the output end of the operational amplifier (OP 1), a fifth resistor (R5) and a sixth resistor (R6) which are respectively connected with the non-inverting input end of the operational amplifier (OP 1), the common-mode stability compensation circuit comprises a third capacitor (C3), a third resistor (R3) and a fourth resistor (R4) which are respectively connected with the third capacitor (C3), and the differential mode stability compensation circuit comprises a first resistor (R1), a first capacitor (C1), a second resistor (R2) and a second capacitor (C2), the first resistor (R1) is connected in series with a first capacitor (C1), and the second resistor (R2) is connected in series with a second capacitor (C2).

2. An operational amplifier circuit as claimed in claim 1, wherein: comprises an operational amplifier (OP 1), an analog circuit power supply (AVCC), a first PMOS tube (MP 1), a second PMOS tube (MP 2), a third PMOS tube (MP 3), a fourth PMOS tube (MP 4), a fifth PMOS tube (MP 5), a sixth PMOS tube (MP 6), a first NMOS tube (MN 6), a second NMOS tube (MN 6), a third NMOS tube (MN 6), a fourth NMOS tube (MN 6), a fifth NMOS tube (MN 6), a sixth NMOS tube (MN 6), a seventh NMOS tube (MN 6), an eighth NMOS tube (MN 6), a ninth NMOS tube (MN 6), a tenth NMOS tube (MN 6), an eleventh NMOS tube (MN 6), a twelfth NMOS tube (MN 6), a thirteenth NMOS tube (MN 6), a fourteenth NMOS tube (MN 6), a fifteenth NMOS tube (MN 6), a first resistor (R6), a second resistor (R6), a sixth resistor (R6), a fifth resistor (R6), a fifth resistor 6) and a fifth resistor 6), a source of the first PMOS transistor (MP 1), a source of the second PMOS transistor (MP 2), a source of the third PMOS transistor (MP 3), a source of the fourth PMOS transistor (MP 4), a source of the fifth PMOS transistor (MP 5), a source of the sixth PMOS transistor (MP 6), a drain of the sixth NMOS transistor (MN 6), a drain of the ninth NMOS transistor (MN 9), a drain of the fourteenth NMOS transistor (MN 14), and a drain of the fifteenth NMOS transistor (MN 15) are respectively connected to an analog circuit power supply (AVCC), a source of the third NMOS transistor (MN 3), a source of the fourth NMOS transistor (MN 4), a source of the seventh NMOS transistor (MN 7), a source of the eighth NMOS transistor (MN 8), a source of the tenth NMOS transistor (MN 10), a source of the eleventh NMOS transistor (MN 11), a source of the twelfth NMOS transistor (MN 12), a gate of the NMOS transistor (AGND 4684), a gate of the analog circuit operational amplifier (MP 4642) and a common mode operational amplifier (MP 4642) are respectively connected to a common mode output terminal of the PMOS 2 and a common mode operational amplifier (MP 4642), the drain of the first PMOS transistor (MP 1) is connected to the drain of a third PMOS transistor (MP 3), one end of a third resistor (R3), one end of a first capacitor (C1), the drain of a first NMOS transistor (MN 1), and the gate of a sixth NMOS transistor (MN 6), the other end of the first capacitor (C1) is connected to one end of a first resistor (R1), the other end of the first resistor (R1) is connected to one end of a sixth resistor (R6), the other end of the sixth resistor (R6) is connected to one end of a fifth resistor (R5) and the inverting input end of an operational amplifier (OP 8), a differential signal output end is provided between the other end of the fifth resistor (R5) and the sixth resistor (R6), the other end of the fifth resistor (R5) is connected to one end of a second resistor (R2), the other end of the second resistor (R84) is connected to one end of a second capacitor (R4642), and the other end of the first capacitor (MN 4) is connected to the other end of the second capacitor (R4642), A drain of a second PMOS transistor (MP 2), a drain of a fifth PMOS transistor (MP 5), a gate of a fourteenth NMOS transistor (MN 14), and a drain of a second NMOS transistor (MN 2), the other end of the fourth resistor (R4) is connected to the other end of a third resistor (R3) and one end of a third capacitor (C3), the other end of the third capacitor (C3) is connected to the gate of a first PMOS transistor (MP 1) and the gate of a second PMOS transistor (MP 2), a first bias voltage input terminal (Vpb 2) is provided between the gate of the fifth PMOS transistor (MP 5) and the gate of a third PMOS transistor (MP 3), a differential input signal terminal is provided between the gate of the second NMOS transistor (MN 2) and the gate of the first NMOS transistor (MN 1), a drain of the second NMOS transistor (MN 2) and a source of the first NMOS transistor (MN 636) are connected to the drain of the third PMOS transistor (MN 3527), and a second bias voltage input terminal (MN 3) is provided between the gate of the third NMOS transistor (MN 3), a source of the fourteenth NMOS transistor (MN 14) is connected to a drain of a tenth NMOS transistor (MN 10), a gate of the tenth NMOS transistor (MN 10) is connected to a gate of an eleventh NMOS transistor (MN 11) and a gate of a twelfth NMOS transistor (MN 12), a drain of the eleventh NMOS transistor (MN 11) is connected to a drain of a sixth PMOS transistor (MP 6) and a gate of a fifteenth NMOS transistor (MN 15), a source of the fifteenth NMOS transistor (MN 15) is connected to a drain of a twelfth NMOS transistor (MN 12) and the other end of a fifth resistor (R5), a source of the sixth NMOS transistor (MN 6) is connected to a drain of a fourth NMOS transistor (MN 638), a gate of the fourth NMOS transistor (MN 4) is connected to a gate of a seventh NMOS transistor (7) and a drain of an eighth NMOS transistor (MN 8), a gate of the seventh NMOS transistor (MN 68629) is connected to a gate of the fourth NMOS transistor (MN 4684), and a gate of the ninth NMOS transistor (MN 4642) is connected to a gate of the ninth NMOS transistor (MP 4684), and a gate of the ninth NMOS transistor (MN 6) And a terminal (Vpb 1), wherein the source of the ninth NMOS transistor (MN 9) is respectively connected with the drain of the eighth NMOS transistor (MN 8) and one terminal of the sixth resistor (R6).