CN111030610B - Full-differential operational amplifier circuit for eliminating DC offset voltage - Google Patents

Full-differential operational amplifier circuit for eliminating DC offset voltage Download PDF

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CN111030610B
CN111030610B CN201911409900.0A CN201911409900A CN111030610B CN 111030610 B CN111030610 B CN 111030610B CN 201911409900 A CN201911409900 A CN 201911409900A CN 111030610 B CN111030610 B CN 111030610B
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operational amplifier
differential
nmos tube
tube
current offset
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CN111030610A (en
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孙伟
黄继成
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Shanghai Panchip Microelectronics Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/303—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters using a switching device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection

Abstract

The invention discloses a full-differential operational amplifier circuit for eliminating direct-current offset voltage, which comprises a first-stage operational amplifier module, a second-stage operational amplifier module, a direct-current offset signal amplifying module and a common mode feedback operational amplifier module, wherein the differential input end of the first-stage operational amplifier module receives differential input signals, the differential output end of the first-stage operational amplifier module is electrically connected to the differential input end of the second-stage operational amplifier module, the differential output end of the second-stage operational amplifier module outputs differential output signals, and the direct-current offset signal amplifying module acquires the differential output signals, filters the differential output signals to obtain direct-current offset signals, amplifies the direct-current offset signals and sends the direct-current offset signals to the differential output end of the first-stage operational amplifier module. The invention not only can realize the suppression of the DC level, but also can adjust the suppression degree of the DC level according to the requirement, thereby greatly simplifying the circuit structure and having simple implementation mode.

Description

Full-differential operational amplifier circuit for eliminating DC offset voltage
Technical Field
The invention relates to the technical field of operational amplifiers, in particular to a full-differential operational amplifier circuit for eliminating DC offset voltage.
Background
Ideally, when the differential input voltage of the operational amplifier is 0, the differential output voltage of the operational amplifier should also be zero. However, since the circuit has mismatch, when the output of the operational amplifier is not 0, the circuit has dc offset, which is defined as the input voltage value when the output voltage is 0.
There are basically three ways to eliminate dc offset: ac coupling, switched capacitor, low pass negative feedback.
Ac coupling is a relatively easy implementation mode, in which a coupling capacitor is added between the front stage and the rear stage, and a dc bias circuit is added at the near input end of the second stage, but when the signal frequency is relatively low, the structure needs a very large on-chip capacitor, which is difficult to realize on-chip. As shown in fig. 1.
The switch capacitor eliminates DC offset by using a clock time-sharing integration method, the switch capacitor is sampled by using clock time-sharing, and the DC offset elimination function is achieved by long-time integration, but a circuit is added in an actual circuit to filter the clock by introducing a clock, and in addition, a clock feed-through and charge injection effect exists in the MOS switch, so that the accuracy of the DC offset elimination is affected. As shown in fig. 2.
The low-pass negative feedback is a direct current offset elimination mode which is widely applied at present, and the basic principle is that a low-pass filter with low cut-off frequency is added in a baseband feedback loop, and the low-pass filter is used for filtering and attenuating low-frequency signals and direct current signals so as to realize direct current offset. This structure needs to be implemented by using an operational amplifier on the feedback loop, and the operational amplifier not only brings extra power consumption, but also has higher requirement on the operational amplifier, and is easy to make the loop oscillate. As shown in fig. 3.
Therefore, those skilled in the art have been working to develop a fully differential operational amplifier circuit for eliminating dc offset voltage, which is convenient to suppress dc level and improves the stability of dc elimination system.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention is to solve the technical problem of how to conveniently implement suppression of dc level and improve stability of dc cancellation system.
The invention provides a full differential operational amplifier circuit for eliminating DC offset voltage, which is characterized by comprising a first-stage operational amplifier module, a second-stage operational amplifier module, a DC offset signal amplifying module and a common mode feedback operational amplifier module, wherein the differential input end of the first-stage operational amplifier module receives differential input signals, the differential output end of the first-stage operational amplifier module is electrically connected to the differential input end of the second-stage operational amplifier module, the differential output end of the second-stage operational amplifier module outputs differential output signals, and the DC offset signal amplifying module acquires the differential output signals, filters the DC offset signals to obtain the DC offset signals, amplifies the DC offset signals and transmits the DC offset signals to the differential output end of the first-stage operational amplifier module.
The circuit further comprises a common mode feedback operational amplifier module, wherein the common mode feedback operational amplifier module acquires the differential output signal to obtain a feedback voltage vfb, and the feedback voltage vfb is compared with a reference voltage VREF and amplified to be used as a common mode voltage VCM to be sent to the first-stage operational amplifier module.
Further, the first-stage operational amplifier module includes a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube and a sixth NMOS tube, gates of the first NMOS tube and the second NMOS tube are used as differential input ends of the first-stage operational amplifier module to receive the differential input signals, sources of the first NMOS tube and the second NMOS tube are connected in parallel with drain electrodes of the sixth NMOS tube electrically, source electrodes of the sixth NMOS tube are grounded, drain electrodes of the first NMOS tube are connected in parallel with drain electrodes of the first PMOS tube as one end of differential output ends of the first-stage operational amplifier module is connected in parallel with one end of differential input ends of the second-stage operational amplifier module electrically, drain electrodes of the second NMOS tube are connected in parallel with drain electrodes of the second PMOS tube as the other end of differential output ends of the first-stage operational amplifier module electrically, source electrodes of the first PMOS tube and the second PMOS tube are connected in parallel with source electrodes of the sixth PMOS tube electrically, and the drain electrodes of the first PMOS tube and the second PMOS tube are connected in parallel with each other to introduce common-mode voltage of the sixth PMOS tube.
Further, the second-stage operational amplifier module includes a third PMOS tube, a fourth PMOS tube, a fifth NMOS tube and an eighth NMOS tube, gates of the third PMOS tube and the fourth PMOS tube are used as differential input ends of the second-stage operational amplifier module and are electrically connected with differential output ends of the first-stage operational amplifier module, a drain electrode of the fifth NMOS tube is connected in parallel with a drain electrode of the third PMOS tube and is used as one end of the differential output ends of the second-stage operational amplifier module, a drain electrode of the eighth NMOS tube is connected in parallel with a drain electrode of the fourth PMOS tube and is used as the other end of the differential output ends of the first-stage operational amplifier module, sources of the third PMOS tube and the fourth PMOS tube are connected to a power supply, sources of the fifth NMOS tube and the eighth NMOS tube are grounded, gates of the fifth NMOS tube and the eighth NMOS tube introduce bias voltage VB, and gates and drains of the third PMOS tube are connected in turn to a miller compensation capacitor C C And zero-setting resistor R Z The grid electrode and the drain electrode of the fourth PMOS tube are sequentially connected with another Miller compensation capacitor C C And another zeroing resistor R Z 。
Further, the direct current offset signal amplifying module comprises a direct current offset signal differential amplifier, a seventh NMOS tube and a direct current offset signal sampling module, the direct current offset signal differential amplifier differential input end receives the direct current offset signal obtained by the direct current offset signal sampling module, the direct current offset signal differential amplifier differential output end is electrically connected to the first-stage operational amplifier differential output end, the common end of the direct current offset signal differential amplifier is electrically connected to the drain electrode of the seventh NMOS tube, the source electrode of the seventh NMOS tube is grounded, and the grid electrode of the seventh NMOS tube introduces bias voltage VB.
Further, the common-mode feedback operational amplifier module includes a fifth PMOS tube, a sixth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, and an output signal sampling module, where the output signal sampling module collects the differential output signal, counteracts the differential signal to obtain the feedback voltage vfb, a gate of the ninth NMOS tube introduces the reference voltage, a gate of the tenth NMOS tube receives the feedback voltage vfb, sources of the ninth NMOS tube and the tenth NMOS tube are connected in parallel with a drain of the eleventh NMOS tube electrically, a drain of the ninth NMOS tube is connected in parallel with a gate and a drain of the fifth PMOS tube, a drain of the tenth NMOS tube is connected in parallel with a gate and a drain of the sixth PMOS tube to output the common-mode voltage VCM, sources of the fifth PMOS tube and the sixth PMOS tube are connected in power, a source of the eleventh NMOS tube is grounded, and a gate of the eleventh NMOS tube introduces the bias voltage VB.
Further, the direct current offset signal differential amplifier comprises a third NMOS tube and a fourth NMOS tube, the gates of the third NMOS tube and the fourth NMOS tube are used as the differential input end of the direct current offset signal differential amplifier to introduce the direct current offset signal, the drains of the third NMOS tube and the fourth NMOS tube are used as the differential output end of the direct current offset signal differential amplifier to be sent to the differential output end of the first-stage operational amplifier, and the sources of the third NMOS tube and the fourth NMOS tube are connected in parallel to be used as the common end of the direct current offset signal differential amplifier.
Further, the direct current offset signal differential amplifier comprises 31 to 3n NMOS tubes and 41 to 4n NMOS tubes, wherein the gates of the 31 to 3n NMOS tubes and the 41 to 4n NMOS tubes are used as differential input ends of the direct current offset signal differential amplifier to introduce the direct current offset signal, the drains of the 31 to 3n NMOS tubes and the 41 to 4n NMOS tubes are connected in parallel with 41 to 4n control switches after passing through 31 to 3n control switches respectively and then are connected in parallel as differential output ends of the direct current offset signal differential amplifier to be sent to differential output ends of the first-stage operational amplifier module, and the 31 to 3n NMOS tubes and the 41 to 4n NMOS tubes are connected in parallel as common ends of the direct current offset signal differential amplifier.
Further, the direct current offset signal sampling module comprises a first resistor R DC1 First capacitor C DC1 A second resistor R DC2 And a second capacitor C DC2 The first resistor R DC1 And a second resistor R DC2 A first end for introducing the differential output signal, a first resistor R DC1 And a second resistor R DC2 The second ends are respectively connected with the first capacitor C DC1 And a second capacitor C DC2 Grounded, the first resistor R DC1 And a second resistor R DC2 The second end outputs the direct current offset signal.
Further, the direct current offset signal sampling module further comprises a third capacitor C DC3 And a fourth capacitor C DC4 The third capacitor C DC3 With the first resistor R DC1 In parallel, the fourth capacitor C DC4 And the second resistor R DC2 And are connected in parallel.
The beneficial technical effects of the invention are as follows:
1. capacitor C DC The stability of the direct current offset elimination system can be improved by introducing a zero stabilization system;
2. the simple RC low-pass filter is utilized to extract the direct current offset signal;
3. the gain of the direct current level can be adjusted according to application requirements, the direct current offset inhibition can be programmable, and compared with the prior art, the circuit structure is simplified, and the implementation mode is simple.
The conception, specific structure, and technical effects of the present invention will be further described with reference to the accompanying drawings to fully understand the objects, features, and effects of the present invention.
Drawings
FIG. 1 is a block diagram of a prior art AC-coupled cancellation DC offset circuit;
FIG. 2 is a block diagram of a prior art switched capacitor DC offset cancellation circuit;
FIG. 3 is a block diagram of a prior art low-pass negative feedback cancellation DC offset circuit;
FIG. 4 is a circuit diagram of a preferred embodiment of the present invention;
fig. 5 is a circuit configuration diagram of a dc offset signal amplifier according to another preferred embodiment of the present invention.
Detailed Description
The following description of the preferred embodiments of the present invention refers to the accompanying drawings, which make the technical contents thereof more clear and easier to understand. The present invention may be embodied in many different forms of embodiments and the scope of the present invention is not limited to only the embodiments described herein.
In view of the drawbacks of the prior art, the present invention provides an operational amplifier circuit for removing dc offset voltage, as shown in fig. 4, which includes a first-stage operational amplifier module 1, a second-stage operational amplifier module 2, a dc offset signal amplifying module 3, and a common-mode feedback operational amplifier module 4.
Embodiment one:
fig. 4 shows a circuit diagram of embodiment 1 of the present invention, namely a full differential operational amplifier circuit for eliminating dc voltage, wherein the full differential operational amplifier circuit has a differential input and differential output structure.
Wherein VIP and VIN are differential input signals, VOP and VON are differential output signals, VDCP and VDCN are direct current offset signals, VDD is a power supply, VB is a bias voltage, vfb is a feedback voltage, VREF is a reference voltage, and VCM is a common mode voltage.
The first-stage operational amplifier module 1 is composed of a P-type MOS tube (MP 1), a P-type MOS tube (MP 2), an N-type MOS tube (MN 1), an N-type MOS tube (MN 2) and an N-type MOS tube (MN 6). The system comprises a load tube, a load tube and a differential input tube, wherein MN1 and MN2 are differential input tubes, and MP1 and MP2 are load tubes; MN6 is the tail current source, providing the operating current for the first stage op-amp.
The second-stage operational amplifier module 2 consists of a P-type MOS tube (MP 3), a P-type MOS tube (MP 4), an N-type MOS tube (MN 5) and an N-type MOS tube (MN 8). Capacitor C C For compensating capacitance, resistance R Z Is zero resistance. VOP and VON are outputs of the op-amp. MP3 and MP4 are input differential pair transistors of the second-stage operational amplifier; MN5 and MN8 are current source loads.
The common mode feedback operational amplifier module 4 is composed of a P-type MOS tube (MP 5), a P-type MOS tube (MP 6), an N-type MOS tube (MN 9), an N-type MOS tube (MN 10), an N-type MOS tube (MN 11) and an output signal sampling module, and provides a stable working point for the two-stage operational amplifier. The output signal sampling module is composed of a resistor R a And capacitor C a The voltage dividing circuit is formed.
The direct-current offset signal amplifying module 3 is composed of a direct-current offset signal differential amplifier 5, an N-type MOS tube (MN 7) and a direct-current offset signal sampling module. The direct current offset signal differential amplifier 5 is composed of an N-type MOS tube (MN 3) and an N-type MOS tube (MN 4). The DC offset signal sampling module consists of a resistor R DC And capacitor C DC The low-pass filter is used for direct current detection, sampling the output signal of the second stage of the operational amplifier, filtering the output signal to obtain a direct current offset signal, amplifying the direct current offset signal through MN3 and MN4, and returning the direct current offset signal to the output point A and the output point B of the operational amplifier of the first stage again, and superposing the direct current offset signal with the original offset signal at the point A and the point B, thereby realizing direct current offset elimination. Capacitor introduction C DC1 And the zero point stabilizing system can improve the stability of the direct current offset eliminating system.
Gain A of Direct Current (DC) level DC The method comprises the following steps:
Figure BDA0002349695030000051
in the formula g MN1 And g MN3 The transconductance of the MOS transistors MN1 and MN3 are respectively; r is R OA Is the equivalent output resistance of point a.
Embodiment two:
as shown in fig. 5, based on the first embodiment, the dc offset signal differential amplifier 5 in the second embodiment is formed by an N-type MOS transistor (MN3 1 -MN3 n ) N type MOS tube (MN 4) 1 -MN4 n ) N-bit control switch S 31 -S 3n And S is 41 -S 4n The composition is formed. The control signal is programmable to realize the adjustment of the direct-current level suppression degree.
The invention not only can realize the suppression of the DC level, but also can adjust the suppression degree of the DC level according to the requirement, thereby greatly simplifying the circuit structure and having simple implementation mode.
The foregoing describes in detail preferred embodiments of the present invention. It should be understood that numerous modifications and variations can be made in accordance with the concepts of the invention without requiring creative effort by one of ordinary skill in the art. Therefore, all technical solutions which can be obtained by logic analysis, reasoning or limited experiments based on the prior art by the person skilled in the art according to the inventive concept shall be within the scope of protection defined by the claims.

Claims (6)

1. The full-differential operational amplifier circuit for eliminating the DC offset voltage is characterized by comprising a first-stage operational amplifier module, a second-stage operational amplifier module, a DC offset signal amplifying module and a common mode feedback operational amplifier module, wherein the differential input end of the first-stage operational amplifier module receives differential input signals, the differential output end of the first-stage operational amplifier module is electrically connected to the differential input end of the second-stage operational amplifier module, the differential output end of the second-stage operational amplifier module outputs differential output signals, and the DC offset signal amplifying module acquires the differential output signals, filters the differential output signals to obtain the DC offset signals, amplifies the DC offset signals and then sends the DC offset signals to the differential output end of the first-stage operational amplifier module;
the first-stage operational amplifier module comprises a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube and a sixth NMOS tube, wherein grid electrodes of the first NMOS tube and the second NMOS tube are used as differential input ends of the first-stage operational amplifier module to receive the differential input signals, source electrodes of the first NMOS tube and the second NMOS tube are connected with drain electrodes of the sixth NMOS tube in parallel, source electrodes of the sixth NMOS tube are grounded, drain electrodes of the first NMOS tube and the drain electrodes of the first PMOS tube are connected with one end of the differential output ends of the first-stage operational amplifier module in parallel and one end of the differential input ends of the second-stage operational amplifier module in parallel, drain electrodes of the second NMOS tube and the drain electrodes of the second PMOS tube are connected with the other end of the differential input ends of the first-stage operational amplifier module in parallel, source electrodes of the first PMOS tube and the second PMOS tube are connected with a power supply, grid electrodes of the first PMOS tube and the second PMOS tube are connected with the common-mode voltage VCM, and bias voltage VB of the sixth grid electrode is introduced into the first-stage operational amplifier module in parallel;
the second-stage operational amplifier module comprises a third PMOS tube, a fourth PMOS tube, a fifth NMOS tube and an eighth NMOS tube, wherein the grid electrodes of the third PMOS tube and the fourth PMOS tube are used as the differential input ends of the second-stage operational amplifier module and are electrically connected with the differential output ends of the first-stage operational amplifier module, the drain electrode of the fifth NMOS tube is connected with the drain electrode of the third PMOS tube in parallel and used as one end of the differential output ends of the second-stage operational amplifier module, the drain electrode of the eighth NMOS tube is connected with the drain electrode of the fourth PMOS tube in parallel and used as the other end of the differential output ends of the first-stage operational amplifier module, the source electrodes of the third PMOS tube and the fourth PMOS tube are connected with a power supply, the source electrodes of the fifth NMOS tube and the eighth NMOS tube are grounded, the grid electrodes of the fifth NMOS tube and the eighth NMOS tube are introduced with a bias voltage VB, and the grid electrodes of the third PMOS tube and the drain electrode of the fifth NMOS tube are sequentially connected with a Miller compensation capacitor C C And zero-setting resistor R Z The grid electrode and the drain electrode of the fourth PMOS tube are sequentially connected with another Miller compensation capacitor C C And another zeroing resistor R Z ；
The direct-current offset signal amplification module comprises a direct-current offset signal differential amplifier, a seventh NMOS tube and a direct-current offset signal sampling module, wherein the direct-current offset signal differential amplifier differential input end receives the direct-current offset signal obtained by the direct-current offset signal sampling module, the direct-current offset signal differential amplifier differential output end is electrically connected to the first-stage operational amplifier differential output end, the common end of the direct-current offset signal differential amplifier is electrically connected to the drain electrode of the seventh NMOS tube, the source electrode of the seventh NMOS tube is grounded, and the grid electrode of the seventh NMOS tube introduces bias voltage VB;
the common mode feedback operational amplifier module comprises a fifth PMOS tube, a sixth PMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube and an output signal sampling module, wherein the output signal sampling module acquires the differential output signal, the feedback voltage vfb is obtained after the differential signal is counteracted, the reference voltage is introduced into the grid electrode of the ninth NMOS tube, the feedback voltage vfb is received by the grid electrode of the tenth NMOS tube, the source electrodes of the ninth NMOS tube and the tenth NMOS tube are connected with the drain electrode of the eleventh NMOS tube in parallel, the drain electrode of the ninth NMOS tube is connected with the grid electrode and the drain electrode of the fifth PMOS tube in parallel, the drain electrode of the tenth NMOS tube is connected with the grid electrode and the drain electrode of the sixth PMOS tube in parallel, the source electrodes of the fifth PMOS tube and the sixth PMOS tube are connected with a power supply, the source electrode of the eleventh NMOS tube is grounded, and the bias voltage VB is introduced into the grid electrode of the eleventh NMOS tube.
2. The full differential operational amplifier circuit for eliminating direct current offset voltage according to claim 1, further comprising a common mode feedback operational amplifier module, wherein the common mode feedback operational amplifier module obtains a feedback voltage vfb by collecting the differential output signal, and the feedback voltage vfb is amplified as a common mode voltage VCM after being compared with a reference voltage VREF, and is sent to the first stage operational amplifier module.
3. The circuit for eliminating the direct-current offset voltage fully differential operational amplifier according to claim 1, wherein the direct-current offset signal differential amplifier comprises a third NMOS tube and a fourth NMOS tube, the gates of the third NMOS tube and the fourth NMOS tube are used as differential input ends of the direct-current offset signal differential amplifier to introduce the direct-current offset signal, the drains of the third NMOS tube and the fourth NMOS tube are used as differential output ends of the direct-current offset signal differential amplifier to the differential output end of the first-stage operational amplifier module, and the sources of the third NMOS tube and the fourth NMOS tube are connected in parallel to be used as a common end of the direct-current offset signal differential amplifier.
4. The circuit of the full differential operational amplifier for eliminating the direct current offset voltage according to claim 1, wherein the direct current offset signal differential amplifier comprises 31 to 3n NMOS tubes and 41 to 4n NMOS tubes, the gates of the 31 to 3n NMOS tubes and the 41 to 4n NMOS tubes are used as differential input ends of the direct current offset signal differential amplifier to introduce the direct current offset signal, the drains of the 31 to 3n NMOS tubes and the 41 to 4n NMOS tubes are respectively connected in parallel with the 41 to 4n control switches after passing through the 31 to 3n control switches, and are connected in parallel with the 41 to 4n control switches as differential output ends of the direct current offset signal differential amplifier to be sent to the differential output ends of the first-stage operational amplifier module, and the 31 to 3n NMOS tubes and the 41 to 4n NMOS tubes are connected in parallel as common ends of the direct current offset signal differential amplifier.
5. The full differential operational amplifier circuit for eliminating DC offset voltage according to claim 1, wherein said DC offset signal sampling module comprises a first resistor R DC1 First capacitor C DC1 A second resistor R DC2 And a second capacitor C DC2 The first resistor R DC1 And a second resistor R DC2 A first end for introducing the differential output signal, a first resistor R DC1 And a second resistor R DC2 The second ends are respectively connected with the first capacitor C DC1 And a second capacitor C DC2 Grounded, the first resistor R DC1 And a second resistor R DC2 The second end outputs the direct current offset signal.
6. The full differential operational amplifier circuit for eliminating DC offset voltage according to claim 5, wherein said DC offset signal sampling module further comprises a third capacitor C DC3 And a fourth capacitor C DC4 The third capacitor C DC3 With the first resistor R DC1 In parallel, the fourth capacitor C DC4 And the second resistor R DC2 And are connected in parallel.
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CN112787609A (en) * 2020-12-25 2021-05-11 武汉邮电科学研究院有限公司 Single slip amplifying circuit for eliminating DC offset
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