CN104601127A - Operational amplifier circuit and reference voltage generating circuit module - Google Patents
Operational amplifier circuit and reference voltage generating circuit module Download PDFInfo
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- CN104601127A CN104601127A CN201310530090.0A CN201310530090A CN104601127A CN 104601127 A CN104601127 A CN 104601127A CN 201310530090 A CN201310530090 A CN 201310530090A CN 104601127 A CN104601127 A CN 104601127A
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Abstract
The invention discloses an operational amplifier circuit. The operational amplifier circuit comprises an operational amplifier and a chopping offset elimination circuit for eliminating an offset signal and flicker noise of the operational amplifier. The invention further discloses a reference voltage generating circuit module. The reference voltage generating circuit module comprises a reference voltage generating circuit, an operational amplifier, a chopping offset elimination circuit and a filtering circuit, wherein the reference voltage generating circuit is used for generating voltage with a zero temperature coefficient and current with a zero temperature coefficient; the operational amplifier is used for providing feedback for the reference voltage generating circuit in order that the output of the reference voltage generating circuit is stabilized at a required working point; the chopping offset elimination circuit is used for modulating the inherent offset voltage and the low-frequency flicker noise of the operational amplifier in order to modulate the influence of the offset of the operational amplifier on a reference voltage generated by the reference voltage generating circuit; and the filtering circuit is used for filtering the offset signal modulated by the offset elimination circuit and keeping a useful reference voltage signal. Through adoption of the operational amplifier circuit and the reference voltage generating circuit module, the offset and the flicker noise of the operational amplifier can be eliminated, and the accuracy is increased.
Description
Technical field
The present invention relates to a kind of analog circuit, especially relate to a kind of operation amplifier circuit.The invention still further relates to a kind of reference voltage generating circuit module adopting described operation amplifier circuit.
Background technology
In most of analog circuit, all operation amplifier circuit will be used.Under high-precision applied environment requires, the precision of operational amplifier becomes more and more important, becomes more and more can not tolerate for the intrinsic imbalance of operational amplifier and the flicker noise of low frequency, so will eliminate the flicker noise of imbalance and low frequency.
For in the application of reference voltage generating circuit, the offset voltage of operational amplifier can be directly reflected into above reference voltage output, increases the dispersion of reference voltage, deviation is increased.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of operation amplifier circuit, can eliminate its imbalance and flicker noise, improve its precision; For this reason, the present invention also will provide a kind of reference voltage generating circuit module adopting described operation amplifier circuit.
For solving the problems of the technologies described above, operation amplifier circuit of the present invention, comprising: an operational amplifier; Wherein, also comprise: a copped wave disappears mistuned circuit, is connected, for eliminating misalignment signal and the flicker noise of described operational amplifier with described operational amplifier.
Described reference voltage generating circuit module, comprising:
One reference voltage generating circuit, for generation of the voltage of zero-temperature coefficient and the electric current of zero-temperature coefficient;
One operational amplifier, provides feedback to described reference voltage generating circuit, makes the stable output of described reference voltage generating circuit in required working point, reduces deviation;
One copped wave disappears mistuned circuit, for modulating the flicker noise of the intrinsic offset voltage of described operational amplifier and low frequency, and then the impact that the imbalance of modulating described operational amplifier brings to the reference voltage that described reference voltage generating circuit produces;
One low-pass filter circuit, the misalignment signal for the mistuned circuit modulation that disappears to described copped wave carries out filtering process, the misalignment signal that namely filtering is modulated, the reference voltage signal only remained with.
Described operational amplifier is dual-stage amplifier, and the first order is the amplifier that differential-input differential exports, and the second level is the amplifier of Differential Input Single-end output, and the input of second level amplifier is connected on the output of first order amplifier.
The described copped wave mistuned circuit that disappears is all the Switch Controller by two groups of non-intersect folded clock controls.
Described filter is made up of passive resistance and passive capacitive circuit.
Operation amplifier circuit of the present invention can not only disappear the offset voltage of operational amplifier Differential Input to pipe, also can eliminate the offset voltage of all the other nmos pass transistors and PMOS transistor in operational amplifier, effectively improve the precision of operational amplifier.
Operation amplifier circuit of the present invention can be applied in this continuous time system of reference voltage generating circuit, and automatic zero adjustment technology (Auto-zeroing) can not be applied in continuous time system; Solve the impact of offset voltage on reference voltage, reduce the discreteness of reference voltage, reduce the deviation of reference voltage, improve the precision of reference voltage.
Operation amplifier circuit of the present invention is applied in reference voltage generating circuit and can realizes lower power consumption and less area overhead, and improves module work reliability.
Accompanying drawing explanation
Below in conjunction with accompanying drawing and embodiment, the present invention is further detailed explanation:
Fig. 1 is described reference voltage generating circuit module one example structure schematic diagram;
Fig. 2 is described operation amplifier circuit one example structure schematic diagram;
Fig. 3 is that described copped wave disappears mistuned circuit one example structure schematic diagram.
Embodiment
See Fig. 1, and shown in composition graphs 2,3, described reference voltage generating circuit module in the following embodiments, comprising: a reference voltage generating circuit, an operation amplifier circuit, a low-pass filter circuit.Described operation amplifier circuit comprises an operational amplifier and a copped wave and to disappear mistuned circuit.
The offset voltage of operational amplifier can be derived by transfer function for the impact of reference voltage V ref.
When not considering offset voltage, then have
When counting offset voltage Vos, the direction supposing Vos here as shown in Figure 1, then has
So the imbalance of operational amplifier is directly reflected in reference voltage V ref, and amplified certain multiple by resistance.
Shown in Figure 2, described operation amplifier circuit comprises an operational amplifier and a copped wave and to disappear mistuned circuit.
Described operational amplifier is by PMOS transistor PM0 ~ PM6, and nmos pass transistor NM1 ~ NM6 forms.Wherein, PMOS transistor PM0 ~ PM3, nmos pass transistor NM1 ~ NM2 form first order differential-input differential output amplifier; PMOS transistor PM3 ~ PM6, nmos pass transistor NM3 ~ NM6 form second level Differential Input Single-end output amplifier.
In described first order differential-input differential output amplifier, the source electrode of PMOS transistor PM0 is connected with supply voltage vdd terminal, and its drain electrode is connected with the source electrode of PM2 with PMOS transistor PM1; The drain electrode of PMOS transistor PM1 is connected with the drain and gate of nmos pass transistor NM1, and its node connected is designated as VN1; The drain electrode of PMOS transistor PM2 is connected with the drain and gate of nmos pass transistor NM2, and its node connected is designated as VN2; The source ground of nmos pass transistor NM1 and NM2.PMOS transistor PM0 is as tail current source, and PMOS transistor PM1, PM2 are as first order differential-input differential output amplifier Differential Input to pipe, and nmos pass transistor NM1, NM2 are as first order differential-input differential output amplifier differential load.
In the Differential Input Single-end output amplifier of the described second level, PMOS transistor PM3 is connected with supply voltage vdd terminal with the source electrode of PM4, and the grid of PMOS transistor PM3 is connected with the grid of PMOS transistor PM4, and its node connected is designated as A.The drain electrode of PMOS transistor PM3 is connected with the source electrode of PMOS transistor PM5, and the drain electrode of PMOS transistor PM4 is connected with the source electrode of PMOS transistor PM6, and the grid of PMOS transistor PM5 is connected with the grid of PMOS transistor PM6; The drain electrode of PMOS transistor PM5 is connected with the drain electrode of nmos pass transistor NM5, and its node connected is designated as B.The drain electrode of PMOS transistor PM6 is connected with the drain electrode of nmos pass transistor NM6, and its node connected is designated as C.The grid of nmos pass transistor NM5 is connected with the grid of nmos pass transistor NM6; The source electrode of nmos pass transistor NM5 is connected with the drain electrode of nmos pass transistor NM3, and the source electrode of nmos pass transistor NM6 is connected with the drain electrode of nmos pass transistor NM4, the grid of nmos pass transistor NM3 with
The node VN2 of first order differential-input differential output amplifier is connected, the source ground of nmos pass transistor NM3.The grid of nmos pass transistor NM4 is connected with the node VN1 of first order differential-input differential output amplifier, the source ground of nmos pass transistor NM4.PMOS transistor PM3, PM4, PM5, PM6 form the cascade load of second level Differential Input Single-end output amplifier, nmos pass transistor NM3, NM4 as the input difference of second level Differential Input Single-end output amplifier to pipe.Nmos pass transistor NM5, NM6 common gate structure strengthens the output impedance of second level Differential Input Single-end output amplifier.
The described copped wave mistuned circuit that disappears comprises modulator H1 and demodulator H2.
Add copped wave at first order differential-input differential output amplifier input to disappear the modulator H1 of mistuned circuit, input INN and INP of described modulator H1 is as the external input terminals of operation amplifier circuit, and output one end of modulator H1 is connected with the grid of first order differential-input differential output amplifier Differential Input to pipe PM1 of operational amplifier, its node connected is designated as P; The output other end of modulator H1 is connected with the grid of first order differential-input differential output amplifier Differential Input to pipe PM2 of operational amplifier, and its node connected is designated as N.
Add copped wave at the output O of second level Differential Input Single-end output amplifier and the node A place of second level Differential Input Single-end output amplifier to disappear the demodulator H2 of mistuned circuit.
On the node A that input A, O of described demodulator H2 are connected to second level Differential Input Single-end output amplifier and output O, output C, B of demodulator H2 are connected to node C and the Node B of second level Differential Input Single-end output amplifier.
Shown in composition graphs 3, described modulator H1 and demodulator H2 is formed by two pairs of switches, and wherein every two switches are first connected, and then by two pairs of switch in parallel after series connection; The two ends VIN1 of two pairs of switches in parallel, VIN2 is respectively as two inputs of two pairs of switches; In two switches be connected in series, the node be connected in series is respectively as two output VO1 of two pairs of switches, VO2.
Described two pairs of switches are controlled by the not overlapping clock signal of two-phase.
When the not overlapping clock of described two-phase is in Φ 1 phase place, the input INP for modulator H1 is linked into the P end of operational amplifier, and another input INN of modulator H1 accesses the N end of operational amplifier; Input A for demodulator H2 accesses the C end of operational amplifier, and another input O of demodulator H2 accesses the B end of operational amplifier.
When the not overlapping clock of described two-phase is in Φ 2 phase place, the input INP for modulator H1 is linked into the N end of operational amplifier, and another input INN of modulator H1 accesses the P end of operational amplifier; Input O for demodulator H2 accesses the C end of operational amplifier, and another input A of demodulator H2 accesses the B end of operational amplifier.
Described copped wave disappear mistuned circuit adopt modulation system modulation DC maladjustment, the offset voltage by operational amplifier is adjusted to high band, and becoming frequency is clock frequency f
chopsquare-wave signal.Apply this operational amplifier circuit structure, not only disappear the first order differential-input differential output amplifier Differential Input of operational amplifier to pipe and PMOS transistor PM1, the offset voltage of PM2, also nmos pass transistor NM1 in operational amplifier can be eliminated, NM2, NM3, NM4, the offset voltage problem of PMOS transistor PM3, PM4.
Again shown in composition graphs 1, described reference voltage generating circuit comprises: PMOS transistor PM8 ~ PM10, PNP transistor Q0, Q1, resistance R1, R2 and R4(R2=R4).
The source electrode of PMOS transistor PM8 ~ PM10 is connected with supply voltage vdd terminal, the grid of PMOS transistor PM8 ~ PM10 and the output of described operation amplifier circuit, and the input O of demodulator H2 that namely described copped wave disappears in mistuned circuit is connected; The input INN of the modulator H1 that the drain electrode of PMOS transistor PM8 disappears in mistuned circuit with one end of resistance R4, the emitter of PNP transistor Q0 and described copped wave is connected.PMOS transistor PM9 another input INP of modulator H1 of disappearing in mistuned circuit with one end and the described copped wave of resistance R1, R2 of drain electrode be connected.The other end of resistance R1 is connected with the emitter of PNP transistor Q1.The base stage of the other end of resistance R2 and R4 and PNP transistor Q0 and Q1 and grounded collector GND.The drain electrode of PMOS transistor PM10 as the output of described reference voltage generating circuit, output reference voltage Vref.
Described low-pass filter circuit is made up of passive resistance R3 and passive capacitive C1 in such as Fig. 1, and resistance R3 is connected with the drain electrode of PMOS transistor PM3 with one end of electric capacity C1, other end ground connection GND.Described low-pass filter circuit-3dB(decibel) bandwidth be:
By the capacitance of control capacittance C1, regulate the cut-off frequency of low pass filter, make cut-off frequency be less than clock frequency f
chop, finally can high-frequency signal outside filter out-band, namely filtering is modulated to the misalignment signal of high frequency, retains reference voltage signal.Disappear in the reference voltage generating circuit module of the operation amplifier circuit adjusted whole employing like this, solve the impact of offset voltage on reference voltage.Reduce discreteness, reduce deviation, improve precision.
Above by embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (14)
1. an operation amplifier circuit, comprising: an operational amplifier; It is characterized in that, also comprise: a copped wave disappears mistuned circuit, is connected, for eliminating misalignment signal and the flicker noise of described operational amplifier with described operational amplifier.
2. operation amplifier circuit as claimed in claim 1, is characterized in that:
Described operational amplifier is dual-stage amplifier, and the first order is the amplifier that differential-input differential exports, and the second level is the amplifier of Differential Input Single-end output, and the input of the second level is connected on the output of the first order.
3. operation amplifier circuit as claimed in claim 1 or 2, is characterized in that:
Described operational amplifier is by the first PMOS transistor ~ the 7th PMOS transistor (PM0 ~ PM6), and the first nmos pass transistor ~ the 6th nmos pass transistor (NM1 ~ NM6) forms; Wherein, the first PMOS transistor ~ the 4th PMOS transistor (PM0 ~ PM3), the first nmos pass transistor (NM1) and the second nmos pass transistor (NM2) form first order differential-input differential output amplifier; 4th PMOS transistor ~ the 7th PMOS transistor (PM3 ~ PM6), the 3rd nmos pass transistor ~ the 6th nmos pass transistor (NM3 ~ NM6) forms second level Differential Input Single-end output amplifier;
In described first order differential-input differential output amplifier, the source electrode of the first PMOS transistor (PM0) is connected with supply voltage vdd terminal, and its drain electrode is connected with the source electrode of the second PMOS transistor (PM1) with the 3rd PMOS transistor (PM2); The drain electrode of the second PMOS transistor (PM1) is connected with the drain and gate of the first nmos pass transistor (NM1), and its node connected is designated as VN1; The drain electrode of the 3rd PMOS transistor (PM2) is connected with the drain and gate of the second nmos pass transistor (NM2), and its node connected is designated as VN2; The source ground of the first nmos pass transistor (NM1) and the second nmos pass transistor (NM2); First PMOS transistor (PM0) is as tail current source, second PMOS transistor (PM1) and the second PMOS transistor (PM2) are as first order differential-input differential output amplifier Differential Input to pipe, and the first nmos pass transistor (NM1) and the second nmos pass transistor (NM2) are as first order differential-input differential output amplifier differential load;
In the Differential Input Single-end output amplifier of the described second level, 4th PMOS transistor (PM3) is connected with supply voltage vdd terminal with the source electrode of the 5th PMOS transistor (PM4), the grid of the 4th PMOS transistor (PM3) is connected with the grid of the 5th PMOS transistor (PM4), and its node connected is designated as A; 4th PMOS transistor (PM3) drain electrode is connected with the source electrode of the 6th PMOS transistor (PM5), the drain electrode of the 5th PMOS transistor (PM4) is connected with the source electrode of the 7th PMOS transistor (PM6), and the grid of the 6th PMOS transistor (PM5) is connected with the grid of the 7th PMOS transistor (PM6); The drain electrode of the 6th PMOS transistor (PM5) is connected with the drain electrode of the 5th nmos pass transistor (NM5), and its node connected is designated as B; The drain electrode of the 7th PMOS transistor (PM6) is connected with the drain electrode of the 6th nmos pass transistor (NM6), and its node connected is designated as C; The grid of the 5th nmos pass transistor (NM5) is connected with the grid of the 6th nmos pass transistor (NM6); The source electrode of the 5th nmos pass transistor (NM5) is connected with the drain electrode of the 3rd nmos pass transistor (NM3), the source electrode of the 6th nmos pass transistor (NM6) is connected with the drain electrode of the 4th nmos pass transistor (NM4), the grid of the 3rd nmos pass transistor (NM3) is connected with the node VN2 of first order differential-input differential output amplifier, the source ground of the 3rd nmos pass transistor (NM3); The grid of the 4th nmos pass transistor (NM4) is connected with the node VN1 of first order differential-input differential output amplifier, the source ground of the 4th nmos pass transistor (NM4); 4th PMOS transistor ~ the 7th PMOS transistor (PM3 ~ PM6) forms the cascade load of second level Differential Input Single-end output amplifier, 3rd nmos pass transistor (NM3), the 4th nmos pass transistor (NM4) as the input difference of second level Differential Input Single-end output amplifier to pipe; 5th nmos pass transistor (NM5), the 6th nmos pass transistor (NM6) common gate structure strengthens the output impedance of second level Differential Input Single-end output amplifier.
4. operation amplifier circuit as claimed in claim 3, is characterized in that:
The described copped wave mistuned circuit that disappears comprises a modulator and a demodulator, and described modulator and demodulator is all the Switch Controller by the non-intersect folded clock control of two-phase.
5. operation amplifier circuit as claimed in claim 4, is characterized in that:
Add copped wave at first order differential-input differential output amplifier input to disappear the modulator (H1) of mistuned circuit, two inputs of described modulator (H1) are designated as INN and INP respectively, and as the external input terminals of operation amplifier circuit; Output one end of modulator (H1) is connected to the grid of managing (PM1) with the first order differential-input differential output amplifier Differential Input of operational amplifier, and its node connected is designated as P; The output other end of modulator (H1) is connected to the grid of managing (PM2) with the first order differential-input differential output amplifier Differential Input of operational amplifier, and its node connected is designated as N;
Add copped wave at the output O of second level Differential Input Single-end output amplifier and the node A place of second level Differential Input Single-end output amplifier to disappear the demodulator (H2) of mistuned circuit; Two inputs of described demodulator (H2) are designated as A, O respectively, and on the node A being connected to second level Differential Input Single-end output amplifier and output O; Two outputs of demodulator (H2) are designated as C and B respectively, and are connected to node C and the Node B of second level Differential Input Single-end output amplifier.
6. operation amplifier circuit as claimed in claim 5, it is characterized in that: described modulator (H1) and demodulator (H2) are formed by two pairs of switches, wherein every two switches are first connected, and then by two pairs of switch in parallel after series connection; The two ends (VIN1, VIN2) of two pairs of in parallel switches are respectively as two inputs of two pairs of switches; In two switching branches be connected in series, two nodes be connected in series are respectively as two outputs (VO1, VO2) of two pairs of switches;
When the not overlapping clock of described two-phase is in Φ 1 phase place, the input INP for modulator (H1) is linked into the P end of operational amplifier, and another input INN accesses the N end of operational amplifier; Input A for demodulator (H2) accesses the node C of operational amplifier, and another input O accesses the Node B of operational amplifier;
When the not overlapping clock of described two-phase is in Φ 2 phase place, the input INP for modulator (H1) is linked into the node N of operational amplifier, and another input INN accesses the node P of operational amplifier; Input O for demodulator (H2) accesses the node C of operational amplifier, and another input A accesses the Node B of operational amplifier.
7. a reference voltage generating circuit module, is characterized in that, comprising:
One reference voltage generating circuit, for generation of the voltage of zero-temperature coefficient and the electric current of zero-temperature coefficient;
One operational amplifier, provides feedback to described reference voltage generating circuit, makes described reference voltage generating circuit stable output in required working point, reduces deviation;
One copped wave disappears mistuned circuit, for modulating the flicker noise of the intrinsic offset voltage of described operational amplifier and low frequency, and then the impact that the imbalance of modulating described operational amplifier brings to the reference voltage that described reference voltage generating circuit produces;
One low-pass filter circuit, the misalignment signal for the mistuned circuit modulation that disappears to described copped wave carries out filtering process, the misalignment signal that namely filtering is modulated, the reference voltage signal only remained with.
8. reference voltage generating circuit module as claimed in claim 7, is characterized in that:
Described operational amplifier is dual-stage amplifier, and the first order is the amplifier that differential-input differential exports, and the second level is the amplifier of Differential Input Single-end output, and the input of the second level is connected on the output of the first order.
9. operation amplifier circuit as claimed in claim 7 or 8, is characterized in that:
Described operational amplifier is by the first PMOS transistor ~ the 7th PMOS transistor (PM0 ~ PM6), and the first nmos pass transistor ~ the 6th nmos pass transistor (NM1 ~ NM6) forms; Wherein, the first PMOS transistor ~ the 4th PMOS transistor (PM0 ~ PM3), the first nmos pass transistor (NM1) and the second nmos pass transistor (NM2) form first order differential-input differential output amplifier; 4th PMOS transistor ~ the 7th PMOS transistor (PM3 ~ PM6), the 3rd nmos pass transistor ~ the 6th nmos pass transistor (NM3 ~ NM6) forms second level Differential Input Single-end output amplifier;
In described first order differential-input differential output amplifier, the source electrode of the first PMOS transistor (PM0) is connected with supply voltage vdd terminal, and its drain electrode is connected with the source electrode of the second PMOS transistor (PM1) with the 3rd PMOS transistor (PM2); The drain electrode of the second PMOS transistor (PM1) is connected with the drain and gate of the first nmos pass transistor (NM1), and its node connected is designated as VN1; The drain electrode of the 3rd PMOS transistor (PM2) is connected with the drain and gate of the second nmos pass transistor (NM2), and its node connected is designated as VN2; The source ground of the first nmos pass transistor (NM1) and the second nmos pass transistor (NM2); First PMOS transistor (PM0) is as tail current source, second PMOS transistor (PM1) and the second PMOS transistor (PM2) are as first order differential-input differential output amplifier Differential Input to pipe, and the first nmos pass transistor (NM1) and the second nmos pass transistor (NM2) are as first order differential-input differential output amplifier differential load;
In the Differential Input Single-end output amplifier of the described second level, 4th PMOS transistor (PM3) is connected with supply voltage vdd terminal with the source electrode of the 5th PMOS transistor (PM4), the grid of the 4th PMOS transistor (PM3) is connected with the grid of the 5th PMOS transistor (PM4), and its node connected is designated as A; 4th PMOS transistor (PM3) drain electrode is connected with the source electrode of the 6th PMOS transistor (PM5), the drain electrode of the 5th PMOS transistor (PM4) is connected with the source electrode of the 7th PMOS transistor (PM6), and the grid of the 6th PMOS transistor (PM5) is connected with the grid of the 7th PMOS transistor (PM6); The drain electrode of the 6th PMOS transistor (PM5) is connected with the drain electrode of the 5th nmos pass transistor (NM5), and its node connected is designated as B; The drain electrode of the 7th PMOS transistor (PM6) is connected with the drain electrode of the 6th nmos pass transistor (NM6), and its node connected is designated as C; The grid of the 5th nmos pass transistor (NM5) is connected with the grid of the 6th nmos pass transistor (NM6); The source electrode of the 5th nmos pass transistor (NM5) is connected with the drain electrode of the 3rd nmos pass transistor (NM3), the source electrode of the 6th nmos pass transistor (NM6) is connected with the drain electrode of the 4th nmos pass transistor (NM4), the grid of the 3rd nmos pass transistor (NM3) is connected with the node VN2 of first order differential-input differential output amplifier, the source ground of the 3rd nmos pass transistor (NM3); The grid of the 4th nmos pass transistor (NM4) is connected with the node VN1 of first order differential-input differential output amplifier, the source ground of the 4th nmos pass transistor (NM4); 4th PMOS transistor ~ the 7th PMOS transistor (PM3 ~ PM6) forms the cascade load of second level Differential Input Single-end output amplifier, 3rd nmos pass transistor (NM3), the 4th nmos pass transistor (NM4) as the input difference of second level Differential Input Single-end output amplifier to pipe; 5th nmos pass transistor (NM5), the 6th nmos pass transistor (NM6) common gate structure strengthens the output impedance of second level Differential Input Single-end output amplifier.
10. reference voltage generating circuit module as claimed in claim 9, is characterized in that: the described copped wave mistuned circuit that disappears comprises a modulator and a demodulator, and described modulator and demodulator is all the Switch Controller by two groups of non-intersect folded clock controls.
11. operation amplifier circuits as claimed in claim 10, is characterized in that:
Add copped wave at first order differential-input differential output amplifier input to disappear the modulator (H1) of mistuned circuit, two inputs of described modulator (H1) are designated as INN and INP respectively, and as the external input terminals of operation amplifier circuit; Output one end of modulator (H1) is connected to the grid of managing (PM1) with the first order differential-input differential output amplifier Differential Input of operational amplifier, and its node connected is designated as P; The output other end of modulator (H1) is connected to the grid of managing (PM2) with the first order differential-input differential output amplifier Differential Input of operational amplifier, and its node connected is designated as N;
Add copped wave at the output O of second level Differential Input Single-end output amplifier and the node A place of second level Differential Input Single-end output amplifier to disappear the demodulator (H2) of mistuned circuit; Two inputs of described demodulator (H2) are designated as A, O respectively, and on the node A being connected to second level Differential Input Single-end output amplifier and output O; Two outputs of demodulator (H2) are designated as C and B respectively, and are connected to node C and the Node B of second level Differential Input Single-end output amplifier.
12. operation amplifier circuits as claimed in claim 11, is characterized in that: described modulator (H1) and demodulator (H2) are formed by two pairs of switches, and wherein every two switches are first connected, and then by two pairs of switch in parallel after series connection; The two ends (VIN1, VIN2) of two pairs of in parallel switches are respectively as two inputs of two pairs of switches; In two switching branches be connected in series, two nodes be connected in series are respectively as two outputs (VO1, VO2) of two pairs of switches;
When the not overlapping clock of described two-phase is in Φ 1 phase place, the input INP for modulator (H1) is linked into the P end of operational amplifier, and another input INN accesses the N end of operational amplifier; Input A for demodulator (H2) accesses the node C of operational amplifier, and another input O accesses the Node B of operational amplifier;
When the not overlapping clock of described two-phase is in Φ 2 phase place, the input INP for modulator (H1) is linked into the node N of operational amplifier, and another input INN accesses the node P of operational amplifier; Input O for demodulator (H2) accesses the node C of operational amplifier, and another input A accesses the Node B of operational amplifier.
13. operation amplifier circuits as claimed in claim 12, is characterized in that:
Described reference voltage generating circuit comprises: the 8th PMOS transistor ~ the tenth PMOS transistor (PM8 ~ PM10), the first PNP transistor (Q0), the second PNP transistor (Q1), the first resistance (R1), the second resistance (R2) and the 4th resistance (R4);
The source electrode of the 8th PMOS transistor ~ the tenth PMOS transistor (PM8 ~ PM10) is connected with supply voltage vdd terminal, 8th PMOS transistor ~ the grid of the tenth PMOS transistor (PM8 ~ PM10) and the output of described operation amplifier circuit, the input O of demodulator (H2) that namely described copped wave disappears in mistuned circuit is connected; The input INN of the modulator (H1) that the drain electrode of the 8th PMOS transistor (PM8) disappears in mistuned circuit with one end of the 4th resistance (R4), the emitter of the first PNP transistor (Q0) and described copped wave is connected; 9th PMOS transistor (PM9) another input INP of modulator (H1) of disappearing in mistuned circuit with one end and the described copped wave of the first resistance (R1), the second resistance (R2) of drain electrode be connected; The other end of the first resistance (R1) is connected with the emitter of the second PNP transistor (Q1); The other end of the second resistance (R2) and the 4th resistance (R4) and the base stage of the first PNP transistor (Q0) and the second PNP transistor (Q1) and grounded collector GND; The drain electrode of the tenth PMOS transistor (PM10) as the output of described reference voltage generating circuit, output reference voltage Vref.
14. reference voltage generating circuit modules as claimed in claim 13, is characterized in that: described low pass filter is made up of passive 3rd resistance (R3) and passive first electric capacity (C1); 3rd resistance (R3) is connected with the drain electrode of the tenth PMOS transistor (PM10) with one end of the first electric capacity (C1), other end ground connection GND.
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| CN106951019A (en) * | 2017-03-29 | 2017-07-14 | 许昌学院 | A kind of difference output formula reference voltage source circuit |
| CN108562373A (en) * | 2018-04-24 | 2018-09-21 | 电子科技大学 | A kind of high-precision temperature sensor circuit |
| CN108572034A (en) * | 2018-04-24 | 2018-09-25 | 电子科技大学 | A kind of temperature sensor circuit of embedded clock |
| CN111030610A (en) * | 2019-12-31 | 2020-04-17 | 上海磐启微电子有限公司 | Fully differential operational amplifier circuit for eliminating DC offset voltage |
| CN114115422A (en) * | 2021-12-10 | 2022-03-01 | 博大融科(北京)信息技术有限公司 | Band gap reference circuit |
| CN115328246A (en) * | 2022-08-12 | 2022-11-11 | 苏州大学 | Low-noise reference voltage source circuit established quickly |
| CN116382402A (en) * | 2023-03-21 | 2023-07-04 | 辰芯半导体（深圳）有限公司 | Band gap reference voltage generating circuit and integrated circuit |
| WO2024031991A1 (en) * | 2022-08-09 | 2024-02-15 | 上海烨映微电子科技股份有限公司 | Reference circuit |
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| CN105824349A (en) * | 2016-05-26 | 2016-08-03 | 上海巨微集成电路有限公司 | Self-calibration band-gap reference circuit and band-gap reference voltage self-calibration system and method |
| CN106951019A (en) * | 2017-03-29 | 2017-07-14 | 许昌学院 | A kind of difference output formula reference voltage source circuit |
| CN106951019B (en) * | 2017-03-29 | 2018-05-15 | 许昌学院 | A kind of difference output formula reference voltage source circuit |
| CN108562373A (en) * | 2018-04-24 | 2018-09-21 | 电子科技大学 | A kind of high-precision temperature sensor circuit |
| CN108572034A (en) * | 2018-04-24 | 2018-09-25 | 电子科技大学 | A kind of temperature sensor circuit of embedded clock |
| CN108572034B (en) * | 2018-04-24 | 2020-11-13 | 电子科技大学 | Temperature sensor circuit with built-in clock |
| CN111030610B (en) * | 2019-12-31 | 2023-05-16 | 上海磐启微电子有限公司 | Full-differential operational amplifier circuit for eliminating DC offset voltage |
| CN111030610A (en) * | 2019-12-31 | 2020-04-17 | 上海磐启微电子有限公司 | Fully differential operational amplifier circuit for eliminating DC offset voltage |
| CN114115422A (en) * | 2021-12-10 | 2022-03-01 | 博大融科(北京)信息技术有限公司 | Band gap reference circuit |
| CN114115422B (en) * | 2021-12-10 | 2023-10-20 | 河南省科学院集成电路研究所 | Band gap reference circuit |
| WO2024031991A1 (en) * | 2022-08-09 | 2024-02-15 | 上海烨映微电子科技股份有限公司 | Reference circuit |
| CN115328246A (en) * | 2022-08-12 | 2022-11-11 | 苏州大学 | Low-noise reference voltage source circuit established quickly |
| CN115328246B (en) * | 2022-08-12 | 2023-09-29 | 苏州大学 | Low-noise reference voltage source circuit capable of being quickly established |
| CN116382402A (en) * | 2023-03-21 | 2023-07-04 | 辰芯半导体（深圳）有限公司 | Band gap reference voltage generating circuit and integrated circuit |
| CN116382402B (en) * | 2023-03-21 | 2024-01-12 | 辰芯半导体（深圳）有限公司 | Band gap reference voltage generating circuit and integrated circuit |
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