CN115328246A - A Fast Settling Low Noise Voltage Reference Circuit - Google Patents

Abstract

The invention discloses a quickly-established low-noise reference voltage source circuit which comprises a unipolar transistor and a bipolar transistor, wherein the unipolar transistor comprises a P-type MOS (metal oxide semiconductor) transistor and an N-type MOS transistor, and a reference voltage V is generated by a reference voltage generating circuit _ref The reference voltage is input into a low-pass filter circuit, and the output end of the low-pass filter circuit outputs a low-noise reference voltage V _out By utilizing the cut-off characteristic of the diode, high resistance can be realized, the area of a chip is saved, and meanwhile, the cut-off frequency of the filter can be very low without needing a large capacitor.

Description

A Quickly Established Low Noise Reference Voltage Source Circuit

technical field

The invention relates to the field of reference voltage circuits, in particular to a rapidly established low-noise reference voltage source circuit.

Background technique

The reference circuit uses the low dependence of the bandgap voltage of the semiconductor on the process, temperature, and power supply voltage (PVT) to generate a relatively constant reference voltage. However, the noise generation mechanism accompanying the reference voltage is relatively complicated. The output noise of the reference circuit includes internal noise (mainly thermal noise and flicker noise) and external noise (mainly from power supply ripple). Among them, thermal noise is a kind of white noise, and its power spectral density is almost independent of frequency; power supply ripple The influence of the wave feedthrough mainly occurs at higher frequencies; the flicker noise of the MOS tube has the characteristic that the power spectral density increases as the frequency decreases. Therefore, we can also understand the aging failure of MOS circuits from the perspective of flicker noise: that is, the energy of a flicker noise with a sufficiently low frequency (the reciprocal of the aging cycle) is enough to break down the MOS tube to make it fail.

In short, the reference voltage is a DC value, however, semiconductor circuits also contribute significant low-frequency noise due to device characteristics (the lower the frequency, the higher the power spectral density). For broadband thermal noise and high-frequency power supply ripple feedthrough noise, we can easily suppress it to a lower level through low-pass filtering; for low-frequency flicker noise, we can suppress the noise level by further reducing the cut-off frequency. However, the establishment time of the reference voltage will become very long. If the noise requirement is high, the establishment time may reach the order of several seconds or tens of seconds.

Contents of the invention

In order to solve at least one of the technical problems above, the present invention proposes a fast-established low-noise reference voltage source circuit.

The first aspect of the present invention provides a rapidly established low-noise reference voltage source circuit, including: a reference voltage generation circuit and a low-pass filter circuit;

The reference voltage generating circuit includes a unipolar transistor and a bipolar transistor, the unipolar transistor includes a P-type MOS transistor and an N-type MOS transistor, and the P-type MOS transistor includes a PMOS transistor P ₁₄ , a PMOS transistor P ₁₅ , a PMOS transistor Tube P ₁₆ , N-type MOS tubes include NMOS tube N ₁₂ , NMOS tube N ₁₃ ,

The bipolar transistor includes a bipolar transistor Q ₁ and a bipolar transistor Q ₂ , and the reference voltage generating circuit further includes a resistor R ₁ , a resistor R ₂ , a resistor R ₃ , and a resistor R ₄ ;

The sources of the PMOS transistors P ₁₄ , PMOS transistors P ₁₅ , and PMOS transistors P ₁₆ are connected together and connected to the power supply voltage VDD;

_The gate of PMOS transistor _P14 is connected to the gates of PMOS transistor _P15 and PMOS transistor P16, and connected to the drains of PMOS transistor _P15 and NMOS transistor _N13 , and the gate of NMOS transistor _N13 is connected to the gate of NMOS transistor _N12 . The pole and the drain are connected to the drain of the PMOS transistor _P14 , the source _of the NMOS transistor N12 is connected to the emitter of the bipolar transistor Q1 and _one end _of the resistor R1, and the other end _of the resistor R1 is grounded;

The bases and collectors of bipolar transistor Q1 and bipolar transistor Q2 are connected together and grounded; the source of NMOS transistor N13 is connected to one end of resistor R2 and one end of resistor R3, and the other end of R2 is connected to bipolar The emitter of the transistor Q2, the other end of the resistor R3 are grounded, the drains of the PMOS transistors _P16 and P16 are connected to one end of the resistor R4, and the other end of the resistor R4 is grounded;

The reference voltage generation circuit generates a reference voltage V _ref , the reference voltage is input to a low-pass filter circuit, and the output terminal of the low-pass filter circuit outputs a low-noise reference voltage V _out .

In a preferred embodiment of the present invention, the bipolar transistor Q ₁ and the bipolar transistor Q ₂ are both PNP bipolar transistors.

In a preferred embodiment of the present invention, the low-pass filter circuit includes a Schmitt trigger, a plurality of inverters, and a plurality of P-type MOS transistors and N-type MOS transistors, and the plurality of inverters are inverters Phase device INV1, inverter INV2, inverter INV3, inverter INV4, and multiple P-type MOS tubes are respectively recorded as PMOS tube P1, PMOS tube P2, PMOS tube P3, PMOS tube P4, PMOS tube P5, and PMOS tube P6, PMOS transistor P7, PMOS transistor P8, and multiple N-type MOS transistors are recorded as NMOS transistor N1, NMOS transistor N2, NMOS transistor N3, NMOS transistor N4, NMOS transistor N5, NMOS transistor N6, and NMOS transistor N7.

In a preferred embodiment of the present invention, the sources of PMOS transistor P2, PMOS transistor P3, PMOS transistor P4, PMOS transistor P5, and PMOS transistor P6 are connected together and connected to a voltage, and the gate of PMOS transistor P2 is connected to the gate of PMOS transistor P3 The gates of the NMOS transistors are connected together and connected to the drain of the PMOS transistor P2, the drain of the PMOS transistor P2 is connected to the drain of the NMOS transistor N3, the gate of the NMOS transistor N3 is connected to the drain of the NMOS transistor N3, and the NMOS transistor N3 The source of NMOS transistor N4 is connected to the drain of NMOS transistor N4, the gate of NMOS transistor N4 is connected to the source of NMOS transistor N3, and the source of NMOS transistor N4 is grounded.

In a preferred embodiment of the present invention, the drain of the PMOS transistor P3 is connected to the drain of the NMOS transistor N5, the gate of the NMOS transistor N5 is connected to the gate of the NMOS transistor N6, and is connected to the drain of the PMOS transistor P3, The source of the NMOS transistor N5 is grounded together with the source of the NMOS transistor N6, the drain of the NMOS transistor N6 is connected to the drain of the PMOS transistor P4, the gate of the PMOS transistor P4 is connected to the gate of the PMOS transistor P5, and is connected to the The drain of the NMOS transistor N6 and the drain of the PMOS transistor P5 are grounded through the capacitor C1.

In a preferred embodiment of the present invention, the drain of the PMOS transistor P5 is connected to the input terminal of the Schmitt trigger, and the gates of the PMOS transistor P6, PMOS transistor P7, and PMOS transistor P8 are connected to the NMOS transistor N7, and are connected to The output terminal of the Schmitt trigger, the drain of the PMOS transistor P6 is connected to the source of the PMOS transistor P7, the drain of the PMOS transistor P7 is connected to the source of the PMOS transistor P8, and the drain of the PMOS transistor P8 is connected to the drain of the NMOS transistor N7 , the source of the NMOS transistor N7 is grounded.

In a preferred embodiment of the present invention, the drain of the PMOS transistor P8 and the drain of the NMOS transistor N7 are connected to the input terminal of the inverter INV1, the inverter INV1, the inverter INV2, the inverter INV3, the inverter The phase inverter INV4 is connected in series, the output terminal of the inverter INV4 is connected to the gate of the PMOS transistor P9, the source of the PMOS transistor P9 is connected to the reference voltage V _ref , and the drain of the PMOS transistor P9 is connected to the output terminal of the low-pass filter circuit Output low noise reference voltage V _out .

In a preferred embodiment of the present invention, the source of the PMOS transistor P9 is connected to the drain of the NMOS transistor N2, the drain of the PMOS transistor P9 is connected to the drain of the PMOS transistor P1, and the source of the PMOS transistor P1 is connected to the drain of the NMOS transistor N2. The source of N2 is connected, the gate of PMOS transistor P1 is connected with the gate of NMOS transistor N2, and is connected to the source of PMOS transistor P1.

In a preferred embodiment of the present invention, the drain of the PMOS transistor P1 is connected to the gate of the NMOS transistor N1, and the source and drain of the NMOS transistor N1 are connected to the ground together.

The above technical solution of the present invention has the following advantages compared with the prior art:

1. By using the cut-off characteristics of N2 and P1 in the diode connection mode, N2 and P1 are used as the resistors of the low-pass filter, which can not only achieve high resistance, but also save chip area. At the same time, it can be used without a large capacitor. The cutoff frequency of the filter is very low.

2. After power-on, before the reset signal is generated, the Schmitt trigger inputs a low level and outputs a high level, and passes through the inverter composed of P6, P7, P8 and N7 and the inverters INV1, INV2, INV3, After the shaping delay of INV4, the gate of P9 is at low level, and P9 is turned on. The fast establishment module short-circuits the input and output of the filter, thereby rapidly charging the filter capacitor, which greatly reduces the establishment time.

Description of drawings

In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the accompanying drawings that need to be used in the description of the specific embodiments or prior art. Obviously, some of the following descriptions The accompanying drawings are some embodiments of the present invention, and those skilled in the art can obtain other accompanying drawings based on these drawings without any creative effort.

Fig. 1 is the circuit diagram of the low-noise voltage reference voltage source set up quickly in the embodiment of the present invention;

Fig. 2 is a circuit diagram of a low-pass filter according to an embodiment of the present invention;

Fig. 3 is a schematic diagram of a flip-flop and an inverter according to an embodiment of the present invention;

Fig. 4 is a comparison chart of the establishment time of using the rapid establishment module and not using the rapid establishment module according to the embodiment of the present invention.

Detailed ways

In order to understand the above-mentioned purpose, features and advantages of the present invention more clearly, the present invention will be further described in detail below in conjunction with specific embodiments. It should be noted that, in the case of no conflict, the embodiments of the present application and the features in the embodiments can be combined with each other.

In the following description, numerous specific details are set forth in order to provide a full understanding of the invention,

However, the present invention can also be implemented in other ways than those described here,

Therefore, the protection scope of the present invention is not limited by the specific embodiments disclosed below.

Embodiment one

Referring to FIGS. 1-4 , the present invention proposes a fast-established low-noise voltage reference circuit, as shown in FIG. 3 , which is used to provide a very low-noise level reference voltage that can be quickly established. P ₁₄ , P ₁₅ , P ₁₆ , N ₁₂ , N ₁₃ , R ₁ , R ₂ , R ₃ , R ₄ , Q ₁ , Q ₂ are used to generate a temperature-independent reference voltage V _ref via a fast-settling low-pass filter circuit filter processing, output low-noise reference voltage V _out ,

The reference voltage generating circuit includes a unipolar transistor and a bipolar transistor, the unipolar transistor includes a P-type MOS transistor and an N-type MOS transistor, and the P-type MOS transistor includes a PMOS transistor P ₁₄ , a PMOS transistor P ₁₅ , a PMOS transistor Tube P ₁₆ , N-type MOS tubes include NMOS tube N ₁₂ , NMOS tube N ₁₃ ,

The bipolar transistor includes a bipolar transistor Q ₁ and a bipolar transistor Q ₂ , and the reference voltage generating circuit further includes a resistor R ₁ , a resistor R ₂ , a resistor R ₃ , and a resistor R ₄ ;

The sources of the PMOS transistors P ₁₄ , PMOS transistors P ₁₅ , and PMOS transistors P ₁₆ are connected together and connected to the power supply voltage VDD;

_The gate of PMOS transistor _P14 is connected to the gates of PMOS transistor _P15 and PMOS transistor P16, and connected to the drains of PMOS transistor _P15 and NMOS transistor _N13 , and the gate of NMOS transistor _N13 is connected to the gate of NMOS transistor _N12 . The pole and the drain are connected to the drain of the PMOS transistor _P14 , the source _of the NMOS transistor N12 is connected to the emitter of the bipolar transistor Q1 and _one end _of the resistor R1, and the other end _of the resistor R1 is grounded;

The bases and collectors of bipolar transistor Q1 and bipolar transistor Q2 are connected together and grounded; the source of NMOS transistor N13 is connected to one end of resistor R2 and one end of resistor R3, and the other end of R2 is connected to bipolar The emitter of the transistor Q2, the other end of the resistor R3 is grounded, the drain of the PMOS transistor _P16 P16 is connected to one end of the resistor R4, and the other end of the resistor R4 is grounded;

The reference voltage generation circuit generates a reference voltage V _ref , the reference voltage is input to a low-pass filter circuit, and the output terminal of the low-pass filter circuit outputs a low-noise reference voltage V _out .

Further, both the bipolar transistor Q ₁ and the bipolar transistor Q ₂ are PNP bipolar transistors.

Further, the low-pass filter circuit includes a Schmitt trigger, a plurality of inverters, and a plurality of P-type MOS transistors and N-type MOS transistors, and the plurality of inverters are respectively inverters INV1 and inverted Inverter INV2, inverter INV3, inverter INV4, a plurality of P-type MOS tubes are respectively recorded as PMOS tube P1, PMOS tube P2, PMOS tube P3, PMOS tube P4, PMOS tube P5, PMOS tube P6, PMOS tube P7, PMOS tube P8, multiple N-type MOS tubes are recorded as NMOS tube N1, NMOS tube N2, NMOS tube N3, NMOS tube N4, NMOS tube N5, NMOS tube N6, NMOS tube N7, PMOS tube P2, PMOS tube P3, PMOS tube The sources of the transistor P4, the PMOS transistor P5, and the PMOS transistor P6 are connected together and connected to a voltage, the gate of the PMOS transistor P2 is connected together with the gate of the PMOS transistor P3, and connected to the drain of the PMOS transistor P2, and the PMOS transistor P2 The drain of the transistor P2 is connected to the drain of the NMOS transistor N3, the gate of the NMOS transistor N3 is connected to the drain of the NMOS transistor N3, the source of the NMOS transistor N3 is connected to the drain of the NMOS transistor N4, and the gate of the NMOS transistor N4 connected to the source of the NMOS transistor N3, and the source of the NMOS transistor N4 is grounded.

Further, the drain of the PMOS transistor P3 is connected to the drain of the NMOS transistor N5, the gate of the NMOS transistor N5 is connected to the gate of the NMOS transistor N6, and is connected to the drain of the PMOS transistor P3, and the source of the NMOS transistor N5 The source of the NMOS transistor N6 is connected to the ground, the drain of the NMOS transistor N6 is connected to the drain of the PMOS transistor P4, the gate of the PMOS transistor P4 is connected to the gate of the PMOS transistor P5, and is connected to the drain of the NMOS transistor N6 , the drain of the PMOS transistor P5 is grounded through the capacitor C1.

The diode-connected transistor is cut off as a low-pass filter resistor, which can not only achieve high resistance, but also save chip area, and at the same time can make the cut-off frequency of the filter very low without requiring a large capacitor.

Figure 2 shows the main circuit of the low-pass filter circuit of the present invention. The source base and drain of N1 are grounded, and the gate is connected to the output as a filter capacitor. The drain of N2 is connected to the input, the drain of N2 is connected to the gate of N2, the drain of N2 is connected to the source of P1, the source of P1 is connected to the gate of P1, and the diode connection mode of N2 and P1 constitutes a filter resistor.

A power-on reset (POR) module and a switch tube P10 form a quick setup module. N3 and N4 are inverting tubes, and N3 and N4 form a nanoampere current source. P2, P3, P4, P5 and N5, N6 constitute a three-stage current mirror.

When power on, before the reset signal is generated, INV4 outputs a low level, and the switch tube P9 is turned on, which is equivalent to short-circuiting the input Vin and output Vout, quickly charging the capacitor N1, the current source charges the fF-level on-chip capacitor C1, and the drain of P6 The voltage rises. SMIT1, P6, P7, P8, N7, INV1, INV2, INV3, and INV4 form a delay shaping circuit. When the power is turned on, as the drain voltage of P5 rises, the Schmitt trigger SMIT1 and inverter INV1, INV2, INV3, and INV4 are shaped, INV4 outputs high level, P9 is turned off, the fast building module is no longer connected in parallel with the filter resistor of the low-pass filter circuit, and the low-pass filter circuit starts to work.

Furthermore, during power-on, the capacitor C1 is charged. When the input voltage of the Schmitt trigger reaches the threshold value, the output voltage of the Schmitt trigger is reversed, the input is high, and the output is low. After P6, P7, P8 and The inverter composed of N7 and the inverters INV1, INV2, INV3, and INV4 generate a high-level reset signal after shaping and delaying, the gate of P9 is high, and P9 is turned off. P9 is no longer connected in parallel with the filter resistor, and the low-pass The filter circuit starts to work.

Figure 3 shows the flip-flop and inverter schematic.

Schmitt trigger SMIT1 includes PMOS transistor P10, PMOS transistor P11 and PMOS transistor P12, NMOS transistor N8, NMOS transistor N9, NMOS transistor N10, NMOS transistor N11 and NMOS transistor N12, the gate of PMOS transistor P10 and the gate of NMOS transistor N10 Gate connection, the drain of the PMOS transistor P10 is connected to the source of the PMOS transistor P11, the gate of the PMOS transistor P11 is connected to the gate of the NMOS transistor N8, and is connected to the voltage input terminal V _in together, the drain of the PMOS transistor P11 is connected to the NMOS transistor P11 The drain of N8 is connected to the voltage output terminal V _out together, the source of NMOS transistor N8 is connected to the drain of NMOS transistor N10 and the source of NMOS transistor N9, the source of NMOS transistor N10 is grounded, and the gate of NMOS transistor N9 The pole is connected to the gate of the PMOS transistor P12, and connected to the output terminal V _out of the voltage together, the drain of the NMOS transistor N9 is connected to the drain of the PMOS transistor P12, and the source of the PMOS transistor P12 is connected to the drain of the PMOS transistor P10 , the gates of the NMOS transistor N9 and the PMOS transistor P12 are connected together to the gate of the PMOS transistor P10 and the gate of the NMOS transistor N10.

The inverter includes an NMOS transistor N11 and a PMOS transistor P13, the gate of the NMOS transistor N11 is connected to the gate of the NMOS transistor P12 and connected to the input terminal V _in , the drain of the PMOS transistor P13 is connected to the drain of the NMOS transistor N11 and connected to the output terminal V _out together, and the source of the NMOS transistor N11 is grounded.

The embodiment of the present invention is realized under the 40nm CMOS technology, the power supply voltage is 3.3V, the cut-off frequency is less than 0.01Hz, the establishment time of the present invention is 18ms, and the goal of rapid establishment of the output voltage is realized.

In order to extend the service time of battery-powered systems, SOC systems generally require low power consumption. The quiescent current of the low-pass filter circuit that can be quickly established in the present invention is only 160nA, which is negligible compared to the overall power consumption of the SOC system.

As shown in Figure 4, in the present invention, when the cut-off frequency is very low, the time delay of the RC filter without the fast establishment module is as long as 23s, and the present invention has adopted the fast establishment module, and the establishment time is shortened to 18ms, the present invention It solves the contradiction between RC delay and cut-off frequency, and has obvious advantages in settling time. After the output is connected to a low-pass filter circuit, the noise generated by the reference source is greatly reduced.

The technical features of the above embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, they should be It is considered to be within the range described in this specification.

The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to the above-described embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the above-described embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (9)

1. A fast settling low noise reference voltage source circuit comprising: a reference voltage generating circuit and a low-pass filter circuit; it is characterized in that the preparation method is characterized in that,

the reference voltage generating circuit comprises a unipolar transistor and a bipolar transistor, the unipolar transistor comprises a P-type MOS (metal oxide semiconductor) transistor and an N-type MOS transistor, and the P-type MOS transistor comprises a PMOS (P-channel metal oxide semiconductor) transistor ₁₄ PMOS tube P ₁₅ PMOS tube P ₁₆ The N-type MOS transistor comprises an NMOS transistor N ₁₂ NMOS transistor N ₁₃ ，

The bipolar transistor comprises a bipolar transistor Q ₁ Bipolar transistor Q ₂ The reference voltage generating circuit further includes a resistor R ₁ Resistance R ₂ Resistance R ₃ Resistance R ₄ ；

PMOS tube P ₁₄ PMOS tube P ₁₅ PMOS tube P ₁₆ Are connected together and are connected to a supply voltage VDD;

PMOS tube P ₁₄ Grid electrode of the PMOS tube P ₁₅ PMOS tube P ₁₆ Is connected with the PMOS tube P ₁₅ NMOS tube N ₁₃ Drain electrode of (2), NMOS tube N ₁₃ Grid of the NMOS transistor N ₁₂ And the grid electrode and the drain electrode of the PMOS transistor are connected with the PMOS tube P ₁₄ Drain electrode of (1), NMOS tube N ₁₂ Is connected to the bipolar transistor Q ₁ Emitter and resistor R of ₁ One terminal of (1), resistance R ₁ The other end of the first and second electrodes is grounded;

the bases and the collectors of the bipolar transistors Q1 and Q2 are connected together and grounded; the source electrode of the NMOS transistor N13 is connected with one end of a resistor R2 and one end of a resistor R3, the other end of the R2 is connected with the emitting electrode of the bipolar transistor Q2, the other end of the resistor R3 is grounded, and the PMOS transistor P is connected with the source electrode of the NMOS transistor N13 ₁₆ The drain electrode of the P16 is connected with one end of the resistor R4, and the other end of the resistor R4 is grounded;

the reference voltage generating circuit generates a reference voltage V _ref The reference voltage is input into a low-pass filter circuit, and the output end of the low-pass filter circuit outputs a low-noise reference voltage V _out 。

2. A fast settling low noise reference voltage source circuit according to claim 1 wherein said bipolar transistor Q ₁ Bipolar transistor Q ₂ Are all PNP type bipolar transistors.

3. The fast-acting low-noise reference voltage source circuit according to claim 2, wherein the low-pass filter circuit comprises a schmitt trigger, a plurality of inverters and a plurality of P-type MOS transistors and N-type MOS transistors, the plurality of inverters are respectively inverter INV1, inverter INV2, inverter INV3, and inverter INV4, the plurality of P-type MOS transistors are respectively denoted as PMOS transistor P1, PMOS transistor P2, PMOS transistor P3, PMOS transistor P4, PMOS transistor P5, PMOS transistor P6, PMOS transistor P7, and PMOS transistor P8, and the plurality of N-type MOS transistors are respectively denoted as NMOS transistor N1, NMOS transistor N2, NMOS transistor N3, NMOS transistor N4, NMOS transistor N5, NMOS transistor N6, and NMOS transistor N7.

4. The fast settling low noise reference voltage source circuit of claim 3, wherein the sources of PMOS transistor P2, PMOS transistor P3, PMOS transistor P4, PMOS transistor P5, and PMOS transistor P6 are connected together and to a voltage, the gate of PMOS transistor P2 is connected to the gate of PMOS transistor P3 and to the drain of PMOS transistor P2, the drain of PMOS transistor P2 is connected to the drain of NMOS transistor N3, the gate of NMOS transistor N3 is connected to the drain of NMOS transistor N3, the source of NMOS transistor N3 is connected to the drain of NMOS transistor N4, the gate of NMOS transistor N4 is connected to the source of NMOS transistor N3, and the source of NMOS transistor N4 is grounded.

5. The fast-set-up low-noise reference voltage source circuit according to claim 1, wherein the drain of the PMOS transistor P3 is connected to the drain of the NMOS transistor N5, the gate of the NMOS transistor N5 is connected to the gate of the NMOS transistor N6 and is also connected to the drain of the PMOS transistor P3, the source of the NMOS transistor N5 is grounded together with the source of the NMOS transistor N6, the drain of the NMOS transistor N6 is connected to the drain of the PMOS transistor P4, the gate of the PMOS transistor P4 is connected to the gate of the PMOS transistor P5 and is also connected to the drain of the NMOS transistor N6, and the drain of the PMOS transistor P5 is grounded through a capacitor C1.

6. The fast-set low-noise reference voltage source circuit according to claim 5, wherein a drain of the PMOS transistor P5 is connected to an input terminal of the Schmitt trigger, a gate of the PMOS transistor P6, a gate of the PMOS transistor P7, a gate of the PMOS transistor P8 and a gate of the NMOS transistor N7 are connected together and connected to an output terminal of the Schmitt trigger, a drain of the PMOS transistor P6 is connected to a source of the PMOS transistor P7, a drain of the PMOS transistor P7 is connected to a source of the PMOS transistor P8, a drain of the PMOS transistor P8 is connected to a drain of the NMOS transistor N7, and a source of the NMOS transistor N7 is grounded.

7. The fast-acting low-noise reference voltage source circuit as claimed in claim 6, wherein the drain of the PMOS transistor P8 and the drain of the NMOS transistor N7 are connected to the input terminal of the inverter INV1, the inverters INV1, INV2, INV3 and INV4 are connected in series, the output terminal of INV4 is connected to the gate of the PMOS transistor P9, and the source of the PMOS transistor P9 is connected to the reference voltage V _ref， The drain electrode of the PMOS tube P9 is connected to the output end of the low-pass filter circuit to output a low-noise reference voltage V _out。

8. The fast-set-up low-noise reference voltage source circuit according to claim 7, wherein the source of the PMOS transistor P9 is connected to the drain of the NMOS transistor N2, the drain of the PMOS transistor P9 is connected to the drain of the PMOS transistor P1, the source of the PMOS transistor P1 is connected to the source of the NMOS transistor N2, and the gate of the PMOS transistor P1 is connected to the gate of the NMOS transistor N2 and to the source of the PMOS transistor P1.

9. The fast settling low noise reference voltage source circuit of claim 8 wherein the drain of the PMOS transistor P1 is connected to the gate of the NMOS transistor N1, and the source and drain of the NMOS transistor N1 are connected together to ground.

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