CN115328246A - Low-noise reference voltage source circuit established quickly - Google Patents

Low-noise reference voltage source circuit established quickly Download PDF

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Publication number
CN115328246A
CN115328246A CN202210965054.6A CN202210965054A CN115328246A CN 115328246 A CN115328246 A CN 115328246A CN 202210965054 A CN202210965054 A CN 202210965054A CN 115328246 A CN115328246 A CN 115328246A
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transistor
pmos
drain
pmos transistor
nmos transistor
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CN115328246B (en
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白春风
张开
王耀攀
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Suzhou University
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Suzhou University
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters

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Abstract

The invention discloses a quickly-established low-noise reference voltage source circuit which comprises a unipolar transistor and a bipolar transistor, wherein the unipolar transistor comprises a P-type MOS (metal oxide semiconductor) transistor and an N-type MOS transistor, and a reference voltage V is generated by a reference voltage generating circuit ref The reference voltage is input into a low-pass filter circuit, and the output end of the low-pass filter circuit outputs a low-noise reference voltage V out By utilizing the cut-off characteristic of the diode, high resistance can be realized, the area of a chip is saved, and meanwhile, the cut-off frequency of the filter can be very low without needing a large capacitor.

Description

Low-noise reference voltage source circuit established quickly
Technical Field
The invention relates to the field of reference voltage circuits, in particular to a low-noise reference voltage source circuit which is established quickly.
Background
The reference circuit generates a relatively constant reference voltage using low dependence of a bandgap voltage of a semiconductor on a process, temperature, and power supply voltage (PVT), but a noise generation mechanism accompanying the reference voltage is relatively complicated. The output noise of the reference circuit includes internal noise (mainly thermal noise and flicker noise) and external noise (mainly from power supply ripple), wherein the thermal noise is white noise, and the power spectral density of the thermal noise is almost independent of frequency; the effect of power supply ripple feed-through occurs mainly at higher frequencies; the flicker noise of the MOS tube has the characteristic that the power spectral density increases along with the reduction of the frequency. Therefore, we can also understand the aging failure of MOS circuits from the perspective of flicker noise: i.e., a flicker noise with a frequency low enough (inverse of the aging period) has enough energy to break down the MOS transistor to fail.
In summary, the reference voltage is a dc value, however, the semiconductor circuit contributes significant low frequency noise (the lower the frequency the higher the spectral density) due to device characteristics. For broadband thermal noise and high-frequency power supply ripple feed-through noise, the noise can be easily suppressed to a lower level through low-pass filtering; for low frequency flicker noise, we can suppress the noise level by further depressing the cut-off frequency. However, the settling time of the reference voltage becomes very long, and if the noise requirements are high, the settling time may be on the order of seconds, tens of seconds.
Disclosure of Invention
In order to solve at least one technical problem, the invention provides a low-noise reference voltage source circuit which is established quickly.
A first aspect of the present invention provides a fast-settling low-noise reference voltage source circuit, comprising: a reference voltage generating circuit and a low-pass filter circuit;
the reference voltage generating circuit comprises a unipolar transistor and a bipolar transistor, the unipolar transistor comprises a P-type MOS (metal oxide semiconductor) transistor and an N-type MOS transistor, and the P-type MOS transistor comprises a PMOS (P-channel metal oxide semiconductor) transistor 14 PMOS tube P 15 PMOS tube P 16 The N-type MOS transistor comprises an NMOS transistor N 12 NMOS tube N 13 ，
The bipolar transistor comprises a bipolar transistor Q 1 Bipolar transistor Q 2 The reference voltage generating circuit further includes a resistor R 1 Resistance R 2 Resistance R 3 Resistance R 4 ；
PMOS tube P 14 PMOS tube P 15 PMOS tube P 16 Are connected together and are connected to a supply voltage VDD;
PMOS tube P 14 Grid electrode of the PMOS tube P 15 PMOS tube P 16 Is connected with the PMOS tube P 15 NMOS transistor N 13 Drain electrode of (1), NMOS tube N 13 Grid of the NMOS transistor N 12 And is connected to the drainPMOS tube P 14 Drain electrode of (1), NMOS tube N 12 Is connected to the bipolar transistor Q 1 Emitter and resistor R of 1 One terminal of (1), resistance R 1 The other end of the first and second electrodes is grounded;
the bases and the collectors of the bipolar transistors Q1 and Q2 are connected together and grounded; the source electrode of the NMOS transistor N13 is connected with one end of a resistor R2 and one end of a resistor R3, the other end of the R2 is connected with the emitting electrode of the bipolar transistor Q2, the other end of the resistor R3 is grounded, and the PMOS transistor P is connected with the source electrode of the NMOS transistor N13 16 The drain electrode of the P16 is connected with one end of the resistor R4, and the other end of the resistor R4 is grounded; .
The reference voltage generating circuit generates a reference voltage V ref The reference voltage is input into a low-pass filter circuit, and the output end of the low-pass filter circuit outputs a low-noise reference voltage V out 。
In a preferred embodiment of the present invention, the bipolar transistor Q 1 Bipolar transistor Q 2 Are all PNP type bipolar transistors.
In a preferred embodiment of the present invention, the low pass filter circuit includes a schmitt trigger, a plurality of inverters, a plurality of P-type MOS transistors and N-type MOS transistors, the plurality of inverters are respectively inverter INV1, inverter INV2, inverter INV3, and inverter INV4, the plurality of P-type MOS transistors are respectively denoted as PMOS transistor P1, PMOS transistor P2, PMOS transistor P3, PMOS transistor P4, PMOS transistor P5, PMOS transistor P6, PMOS transistor P7, and PMOS transistor P8, and the plurality of N-type MOS transistors are respectively denoted as NMOS transistor N1, NMOS transistor N2, NMOS transistor N3, NMOS transistor N4, NMOS transistor N5, NMOS transistor N6, and NMOS transistor N7.
In a preferred embodiment of the present invention, the sources of the PMOS transistors P2, P3, P4, P5, and P6 are connected together and connected to a voltage, the gate of the PMOS transistor P2 is connected to the gate of the PMOS transistor P3 and to the drain of the PMOS transistor P2, the drain of the PMOS transistor P2 is connected to the drain of the NMOS transistor N3, the gate of the NMOS transistor N3 is connected to the drain of the NMOS transistor N3, the source of the NMOS transistor N3 is connected to the drain of the NMOS transistor N4, the gate of the NMOS transistor N4 is connected to the source of the NMOS transistor N3, and the source of the NMOS transistor N4 is grounded.
In a preferred embodiment of the present invention, the drain of the PMOS transistor P3 is connected to the drain of the NMOS transistor N5, the gate of the NMOS transistor N5 is connected to the gate of the NMOS transistor N6 and is also connected to the drain of the PMOS transistor P3, the source of the NMOS transistor N5 and the source of the NMOS transistor N6 are grounded, the drain of the NMOS transistor N6 is connected to the drain of the PMOS transistor P4, the gate of the PMOS transistor P4 is connected to the gate of the PMOS transistor P5 and is also connected to the drain of the NMOS transistor N6, and the drain of the PMOS transistor P5 is grounded through the capacitor C1.
In a preferred embodiment of the present invention, the drain of the PMOS transistor P5 is connected to the input terminal of the schmitt trigger, the gates of the PMOS transistors P6, P7, and P8 are connected to the gate of the NMOS transistor N7, and are connected to the output terminal of the schmitt trigger, the drain of the PMOS transistor P6 is connected to the source of the PMOS transistor P7, the drain of the PMOS transistor P7 is connected to the source of the PMOS transistor P8, the drain of the PMOS transistor P8 is connected to the drain of the NMOS transistor N7, and the source of the NMOS transistor N7 is grounded.
In a preferred embodiment of the present invention, the drain of the PMOS transistor P8 and the drain of the NMOS transistor N7 are connected to the input terminal of the inverter INV1, the inverters INV1, INV2, INV3 and INV4 are connected in series, the output terminal of INV4 is connected to the gate of the PMOS transistor P9, and the source of the PMOS transistor P9 is connected to the reference voltage V ref The drain electrode of the PMOS tube P9 is connected to the output end of the low-pass filter circuit to output a low-noise reference voltage V out 。
In a preferred embodiment of the present invention, the source of the PMOS transistor P9 is connected to the drain of the NMOS transistor N2, the drain of the PMOS transistor P9 is connected to the drain of the PMOS transistor P1, the source of the PMOS transistor P1 is connected to the source of the NMOS transistor N2, and the gate of the PMOS transistor P1 is connected to the gate of the NMOS transistor N2 and to the source of the PMOS transistor P1.
In a preferred embodiment of the present invention, the drain of the PMOS transistor P1 is connected to the gate of the NMOS transistor N1, and the source and the drain of the NMOS transistor N1 are connected together and grounded.
Compared with the prior art, the technical scheme of the invention has the following advantages:
1. by utilizing the cut-off characteristics of N2 and P1 in a diode connection mode, the N2 and the P1 are used as the resistors of the low-pass filter, so that high resistance can be realized, the area of a chip is saved, and the cut-off frequency of the filter can be very low without needing a large capacitor.
2. After power-on and before a reset signal is generated, a Schmitt trigger inputs a low level and outputs a high level, after shaping and delaying by a phase inverter consisting of P6, P7, P8 and N7 and phase inverters INV1, INV2, INV3 and INV4, a P9 grid is the low level, P9 is conducted, and a quick establishing module is used for short-circuiting the input and the output of a filter, so that the filter capacitor is quickly charged, and the establishing time is greatly reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that some of the drawings in the following description are embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a circuit diagram of a fast-settling low noise voltage reference source in an embodiment of the present invention;
FIG. 2 is a circuit diagram of a low pass filter according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a flip-flop and inverter of an embodiment of the present invention;
FIG. 4 is a graph comparing setup times with and without the fast setup module according to an embodiment of the present invention.
Detailed Description
In order that the above objects, features and advantages of the present invention can be more clearly understood, the present invention will be described in further detail with reference to specific embodiments. It should be noted that the embodiments and features of the embodiments of the present application may be combined with each other without conflict.
In the following description numerous specific details are set forth in order to provide a thorough understanding of the present invention,
the invention may, however, be practiced otherwise than as specifically described herein,
therefore, the scope of the invention is not limited by the specific embodiments disclosed below.
Example one
Referring to fig. 1-4, the present invention provides a fast-settling, low-noise voltage reference circuit, as shown in fig. three, for providing a reference voltage with a very low noise level and capable of being settled fast. P 14 、P 15 、P 16 、N 12 、N 13 、R 1 、R 2 、R 3 、R 4 、Q 1 、Q 2 For generating a temperature-independent reference voltage V ref Outputting a low-noise reference voltage V through a filtering process of a rapidly established low-pass filter circuit out ，
The reference voltage generating circuit comprises a unipolar transistor and a bipolar transistor, the unipolar transistor comprises a P-type MOS (metal oxide semiconductor) transistor and an N-type MOS transistor, and the P-type MOS transistor comprises a PMOS (P-channel metal oxide semiconductor) transistor 14 PMOS tube P 15 PMOS tube P 16 The N-type MOS transistor comprises an NMOS transistor N 12 NMOS transistor N 13 ，
The bipolar transistor comprises a bipolar transistor Q 1 Bipolar transistor Q 2 The reference voltage generating circuit further includes a resistor R 1 Resistance R 2 And a resistor R 3 Resistance R 4 ；
PMOS pipe P 14 PMOS tube P 15 PMOS tube P 16 Are connected together and are connected to a supply voltage VDD;
PMOS pipe P 14 Grid electrode of the PMOS tube P 15 PMOS tube P 16 Is connected with the PMOS tube P 15 NMOS transistor N 13 Drain electrode of (1), NMOS tube N 13 Grid of the NMOS transistor N 12 And the grid electrode and the drain electrode of the PMOS transistor are connected with the PMOS tube P 14 Drain electrode of (2), NMOS tube N 12 Is connected to the bipolar transistor Q 1 Emitter and resistor R of 1 One terminal of (1), resistance R 1 The other end of the first and second electrodes is grounded;
the bases and the collectors of the bipolar transistors Q1 and Q2 are connected together and grounded; the source electrode of the NMOS transistor N13 is connected with one end of a resistor R2 and one end of a resistor R3, the other end of the R2 is connected with the emitting electrode of the bipolar transistor Q2, the other end of the resistor R3 is grounded, and the PMOS transistor P is connected with the source electrode of the NMOS transistor N13 16 Drain electrode of P16One end of the resistor R4 is connected, and the other end of the resistor R4 is grounded; .
The reference voltage generating circuit generates a reference voltage V ref The reference voltage is input into a low-pass filter circuit, and the output end of the low-pass filter circuit outputs a low-noise reference voltage V out 。
Further, a bipolar transistor Q 1 Bipolar transistor Q 2 Are all PNP type bipolar transistors.
Further, the low pass filter circuit includes a schmitt trigger, a plurality of inverters and a plurality of P-type MOS transistors and N-type MOS transistors, the plurality of inverters are respectively inverter INV1, inverter INV2, inverter INV3, inverter INV4, the plurality of P-type MOS transistors are respectively designated as PMOS transistor P1, PMOS transistor P2, PMOS transistor P3, PMOS transistor P4, PMOS transistor P5, PMOS transistor P6, PMOS transistor P7, PMOS transistor P8, the plurality of N-type MOS transistors are respectively designated as NMOS transistor N1, NMOS transistor N2, NMOS transistor N3, NMOS transistor N4, NMOS transistor N5, NMOS transistor N6, NMOS transistor N7, the sources of PMOS transistor P2, PMOS transistor P3, PMOS transistor P4, PMOS transistor P5, PMOS transistor P6 are connected together and connected to a voltage, the gate of PMOS transistor P2 is connected to the gate of PMOS transistor P3 and to the drain of PMOS transistor P2, the drain of PMOS transistor P2 is connected to the drain of NMOS transistor N3, the source of PMOS transistor N3 is connected to the drain of NMOS transistor N3, the source of NMOS transistor N3 is connected to the drain of NMOS transistor N4, the drain of NMOS transistor N4 is connected to the drain of NMOS transistor N3 is connected to the drain of NMOS transistor N4, and the drain of NMOS transistor N4 is connected to the drain of NMOS transistor N4.
Further, the drain of the PMOS transistor P3 is connected to the drain of the NMOS transistor N5, the gate of the NMOS transistor N5 is connected to the gate of the NMOS transistor N6 and is also connected to the drain of the PMOS transistor P3, the source of the NMOS transistor N5 is grounded together with the source of the NMOS transistor N6, the drain of the NMOS transistor N6 is connected to the drain of the PMOS transistor P4, the gate of the PMOS transistor P4 is connected to the gate of the PMOS transistor P5 and is also connected to the drain of the NMOS transistor N6, and the drain of the PMOS transistor P5 is grounded through the capacitor C1.
The transistor in a diode connection mode is cut off to be used as a resistor of the low-pass filter, so that high resistance value can be realized, the area of a chip is saved, and meanwhile, the cut-off frequency of the filter can be very low without needing a large capacitor.
FIG. 2 shows the main circuit of the low-pass filter circuit of the present invention, in which the N1 source and drain are grounded, and the gate is connected to the output as the filter capacitor. The N2 drain electrode is connected with the input, the N2 drain electrode is connected with the N2 grid electrode, the N2 drain electrode is connected with the P1 source electrode, the P1 source electrode is connected with the P1 grid electrode, and the filtering resistor is formed by the diode connection mode of the N2 and the P1.
The Power-on reset (POR) module and the switching tube P10 constitute a fast setup module. N3 and N4 are inverse ratio tubes, and the N3 and N4 form a nano-ampere current source. P2, P3, P4, P5 and N5, N6 constitute a three-stage current mirror.
When the power is on, before a reset signal is generated, the INV4 outputs a low level, the switch tube P9 is conducted, namely, the input Vin and the output Vout are in short circuit, the capacitor N1 is rapidly charged, the current source charges the capacitor C1 on the fF stage, and the voltage of a P6 drain electrode is increased. When power is started, along with the increase of the voltage of a drain electrode of P5, the SMIT1, the inverters INV1, INV2, INV3 and INV4 shape the power, the INV4 outputs a high level, P9 is turned off, the quick establishing module is not connected with a filter resistor of the low-pass filter circuit in parallel, and the low-pass filter circuit starts to work.
Further, during power-on, the capacitor C1 is charged, when the input voltage of the Schmitt trigger reaches a threshold value, the output voltage of the Schmitt trigger is inverted, a high level is input, a low level is output, after shaping and delaying of the inverter formed by P6, P7, P8 and N7 and the inverters INV1, INV2, INV3 and INV4, a high level reset signal is generated, the grid of the P9 is at the high level, the P9 is turned off, the P9 is not connected with the filter resistor in parallel, and the low-pass filter circuit starts to work.
Fig. 3 shows a schematic diagram of a flip-flop and an inverter.
The Schmitt trigger SMIT1 comprises a PMOS tube P10, a PMOS tube P11 and a PMOS tube P12, an NMOS tube N8, an NMOS tube N9, an NMOS tube N10, an NMOS tube N11 and an NMOS tube N12, wherein the grid electrode of the PMOS tube P10 is connected with the grid electrode of the NMOS tube N10, the drain electrode of the PMOS tube P10 is connected with the source electrode of the PMOS tube P11, the grid electrode of the PMOS tube P11 is connected with the grid electrode of the NMOS tube N8 and is connected with a voltage input end V together in The drain electrode of the PMOS tube P11 is connected with the drain electrode of the NMOS tube N8 and is connected to the voltage output end V together out Source of NMOS transistor N8The drain electrode of the NMOS tube N10 is connected with the source electrode of the NMOS tube N9, the source electrode of the NMOS tube N10 is grounded, the grid electrode of the NMOS tube N9 is connected with the grid electrode of the PMOS tube P12, and the grid electrodes are connected with the output end V of the voltage out The drain electrode of the NMOS tube N9 is connected with the drain electrode of the PMOS tube P12, the source electrode of the PMOS tube P12 is connected with the drain electrode of the PMOS tube P10, and the grid electrodes of the NMOS tube N9 and the PMOS tube P12 are connected with the grid electrode of the PMOS tube P10 and the grid electrode of the NMOS tube N10.
The phase inverter comprises an NMOS transistor N11 and a PMOS transistor P13, wherein the grid electrode of the NMOS transistor N11 is connected with the grid electrode of the NMOS transistor P12 and connected to the input end V in The drain electrode of the PMOS pipe P13 is connected with the drain electrode of the NMOS pipe N11 and is connected to the output end V together out And the source electrode of the NMOS tube N11 is grounded.
The implementation scheme of the invention is realized under a 40nm CMOS process, the power supply voltage is 3.3V, the cut-off frequency is less than 0.01Hz, the establishment time of the invention is 18ms, and the aim of quickly establishing the output voltage is realized.
In order to prolong the service time of a battery power supply system, the SOC system generally requires low power consumption, and the quiescent current of the low-pass filter circuit which can be quickly established is only 160nA, and is negligible relative to the overall power consumption of the SOC system.
As shown in fig. 4, in the present invention, when the cut-off frequency is very low, the delay of the RC filter without the fast establishment module is as long as 23s, while the establishment time is shortened to 18ms by using the fast establishment module in the present invention, the present invention solves the contradiction between the RC delay and the cut-off frequency, has an obvious advantage of establishment time, and greatly reduces the noise generated by the reference source after the output is connected to the low-pass filter circuit.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to the above-described embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (9)

1. A fast settling low noise reference voltage source circuit comprising: a reference voltage generating circuit and a low-pass filter circuit; it is characterized in that the preparation method is characterized in that,
the reference voltage generating circuit comprises a unipolar transistor and a bipolar transistor, the unipolar transistor comprises a P-type MOS (metal oxide semiconductor) transistor and an N-type MOS transistor, and the P-type MOS transistor comprises a PMOS (P-channel metal oxide semiconductor) transistor 14 PMOS tube P 15 PMOS tube P 16 The N-type MOS transistor comprises an NMOS transistor N 12 NMOS transistor N 13 ，
The bipolar transistor comprises a bipolar transistor Q 1 Bipolar transistor Q 2 The reference voltage generating circuit further includes a resistor R 1 Resistance R 2 Resistance R 3 Resistance R 4 ；
PMOS tube P 14 PMOS tube P 15 PMOS tube P 16 Are connected together and are connected to a supply voltage VDD;
PMOS tube P 14 Grid electrode of the PMOS tube P 15 PMOS tube P 16 Is connected with the PMOS tube P 15 NMOS tube N 13 Drain electrode of (2), NMOS tube N 13 Grid of the NMOS transistor N 12 And the grid electrode and the drain electrode of the PMOS transistor are connected with the PMOS tube P 14 Drain electrode of (1), NMOS tube N 12 Is connected to the bipolar transistor Q 1 Emitter and resistor R of 1 One terminal of (1), resistance R 1 The other end of the first and second electrodes is grounded;
the bases and the collectors of the bipolar transistors Q1 and Q2 are connected together and grounded; the source electrode of the NMOS transistor N13 is connected with one end of a resistor R2 and one end of a resistor R3, the other end of the R2 is connected with the emitting electrode of the bipolar transistor Q2, the other end of the resistor R3 is grounded, and the PMOS transistor P is connected with the source electrode of the NMOS transistor N13 16 The drain electrode of the P16 is connected with one end of the resistor R4, and the other end of the resistor R4 is grounded;
the reference voltage generating circuit generates a reference voltage V ref The reference voltage is input into a low-pass filter circuit, and the output end of the low-pass filter circuit outputs a low-noise reference voltage V out 。
2. A fast settling low noise reference voltage source circuit according to claim 1 wherein said bipolar transistor Q 1 Bipolar transistor Q 2 Are all PNP type bipolar transistors.
3. The fast-acting low-noise reference voltage source circuit according to claim 2, wherein the low-pass filter circuit comprises a schmitt trigger, a plurality of inverters and a plurality of P-type MOS transistors and N-type MOS transistors, the plurality of inverters are respectively inverter INV1, inverter INV2, inverter INV3, and inverter INV4, the plurality of P-type MOS transistors are respectively denoted as PMOS transistor P1, PMOS transistor P2, PMOS transistor P3, PMOS transistor P4, PMOS transistor P5, PMOS transistor P6, PMOS transistor P7, and PMOS transistor P8, and the plurality of N-type MOS transistors are respectively denoted as NMOS transistor N1, NMOS transistor N2, NMOS transistor N3, NMOS transistor N4, NMOS transistor N5, NMOS transistor N6, and NMOS transistor N7.
4. The fast settling low noise reference voltage source circuit of claim 3, wherein the sources of PMOS transistor P2, PMOS transistor P3, PMOS transistor P4, PMOS transistor P5, and PMOS transistor P6 are connected together and to a voltage, the gate of PMOS transistor P2 is connected to the gate of PMOS transistor P3 and to the drain of PMOS transistor P2, the drain of PMOS transistor P2 is connected to the drain of NMOS transistor N3, the gate of NMOS transistor N3 is connected to the drain of NMOS transistor N3, the source of NMOS transistor N3 is connected to the drain of NMOS transistor N4, the gate of NMOS transistor N4 is connected to the source of NMOS transistor N3, and the source of NMOS transistor N4 is grounded.
5. The fast-set-up low-noise reference voltage source circuit according to claim 1, wherein the drain of the PMOS transistor P3 is connected to the drain of the NMOS transistor N5, the gate of the NMOS transistor N5 is connected to the gate of the NMOS transistor N6 and is also connected to the drain of the PMOS transistor P3, the source of the NMOS transistor N5 is grounded together with the source of the NMOS transistor N6, the drain of the NMOS transistor N6 is connected to the drain of the PMOS transistor P4, the gate of the PMOS transistor P4 is connected to the gate of the PMOS transistor P5 and is also connected to the drain of the NMOS transistor N6, and the drain of the PMOS transistor P5 is grounded through a capacitor C1.
6. The fast-set low-noise reference voltage source circuit according to claim 5, wherein a drain of the PMOS transistor P5 is connected to an input terminal of the Schmitt trigger, a gate of the PMOS transistor P6, a gate of the PMOS transistor P7, a gate of the PMOS transistor P8 and a gate of the NMOS transistor N7 are connected together and connected to an output terminal of the Schmitt trigger, a drain of the PMOS transistor P6 is connected to a source of the PMOS transistor P7, a drain of the PMOS transistor P7 is connected to a source of the PMOS transistor P8, a drain of the PMOS transistor P8 is connected to a drain of the NMOS transistor N7, and a source of the NMOS transistor N7 is grounded.
7. The fast-acting low-noise reference voltage source circuit as claimed in claim 6, wherein the drain of the PMOS transistor P8 and the drain of the NMOS transistor N7 are connected to the input terminal of the inverter INV1, the inverters INV1, INV2, INV3 and INV4 are connected in series, the output terminal of INV4 is connected to the gate of the PMOS transistor P9, and the source of the PMOS transistor P9 is connected to the reference voltage V ref， The drain electrode of the PMOS tube P9 is connected to the output end of the low-pass filter circuit to output a low-noise reference voltage V out。
8. The fast-set-up low-noise reference voltage source circuit according to claim 7, wherein the source of the PMOS transistor P9 is connected to the drain of the NMOS transistor N2, the drain of the PMOS transistor P9 is connected to the drain of the PMOS transistor P1, the source of the PMOS transistor P1 is connected to the source of the NMOS transistor N2, and the gate of the PMOS transistor P1 is connected to the gate of the NMOS transistor N2 and to the source of the PMOS transistor P1.
9. The fast settling low noise reference voltage source circuit of claim 8 wherein the drain of the PMOS transistor P1 is connected to the gate of the NMOS transistor N1, and the source and drain of the NMOS transistor N1 are connected together to ground.
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