CN100468934C - Voltage converter and its method - Google Patents

Voltage converter and its method Download PDF

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CN100468934C
CN100468934C CNB2006101640509A CN200610164050A CN100468934C CN 100468934 C CN100468934 C CN 100468934C CN B2006101640509 A CNB2006101640509 A CN B2006101640509A CN 200610164050 A CN200610164050 A CN 200610164050A CN 100468934 C CN100468934 C CN 100468934C
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output signal
transistor
power supply
input signal
phase
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CN1988344A (en
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沈洪浩
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Via Technologies Inc
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Via Technologies Inc
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Abstract

This invention relates to a voltage converter used in converting an input signal to an output signal, in which, when an input signal is at the high potential or an external supply is at low potential, a first inverting module inverts the input signal to output a first output signal, when the input signal is at low potential and the supply is at high potential, a second inverting module turns the first output signal to the high potential, when said first output signal is at high potential, a first inverting protection circuit outputs a low potential second output signal, when the input signal is at high potential, the second inverting protection circuit inputs signals inversely to output a third output signal, when the input signal is at the high potential, the second inverting protection circuit inputs signals inversely to output a third output signal, and the potential of the second and the third output signals is opposite, the lock circuit receives the second and third output signals and a voltage source, and the output circuit outputs an output signal according to the level of the second output signal.

Description

Electric pressure converter and method thereof
Technical field
The present invention is relevant for a kind of electric pressure converter, particularly relevant for a kind of electric pressure converter of leakage current.
Background technology
Fig. 1 is for showing the schematic diagram of conventional voltage transducer 100.Conventional voltage transducer 100 comprises anti-phase module 110, latch circuit 140, negative circuit 160 and 180 and output circuit 195.Anti-phase module 110 has N channel mos (Negative-Channel Metal OxideSemiconductor, NMOS) transistor 111 and 112 and P channel mos (Positive-Channel Metal Oxide Semiconductor, PMOS) transistor 113, nmos pass transistor 111 has a drain electrode with receiving inputted signal input, one grid is to receive voltage source V DD and one source pole ground connection, nmos pass transistor 112 has a drain electrode to couple node 121, one grid receiving inputted signal Vin and one source pole ground connection, PMOS transistor 113 have a drain electrode and couple node 121, one grid receiving inputted signal Vin and one source pole receive voltage source V DD.
Negative circuit 160 has nmos pass transistor 161,163,164 and 165 and PMOS transistor 162, nmos pass transistor 161 has the grid that a drain electrode couples nmos pass transistor 163, one grid receiving inputted signal Vin and one source pole ground connection, nmos pass transistor 163 has a drain electrode and couples nmos pass transistor 164, one grid couples nmos pass transistor 161 and one source pole ground connection, nmos pass transistor 164 has a drain electrode and couples nmos pass transistor 165, one grid receives voltage source V DD and one source pole couples nmos pass transistor 163, nmos pass transistor 165 has a drain electrode and couples node N1, one grid receives voltage source V BAT and one source pole couples nmos pass transistor 164, and PMOS transistor 162 has a drain electrode and couples nmos pass transistor 161, one grid receiving inputted signal Vin and one source pole receive voltage source V DD.Wherein voltage source V DD can be produced by voltage source V BAT dividing potential drop.
Negative circuit 180 has nmos pass transistor 181,183,184 and 185 and PMOS transistor 182, nmos pass transistor 181 has the grid that a drain electrode couples nmos pass transistor 183, one grid couples node 121 and one source pole ground connection, nmos pass transistor 183 has a drain electrode and couples nmos pass transistor 184, one grid couples nmos pass transistor 181 and one source pole ground connection, nmos pass transistor 184 has a drain electrode and couples nmos pass transistor 185, one grid receives voltage source V DD and one source pole couples nmos pass transistor 183, nmos pass transistor 185 has a drain electrode and couples node N2, one grid receives voltage source V BAT and one source pole couples nmos pass transistor 184, and PMOS transistor 182 has a drain electrode and couples nmos pass transistor 181, one grid couples node 121 and one source pole receives voltage source V DD.
Latch circuit 140 comprises PMOS transistor 141 and 142, PMOS transistor 141 have one the drain electrode couple node N1, a grid couples node N2 and one source pole couples voltage source V BAT, PMOS transistor 142 have one the drain electrode couple node N2, a grid couples node N1 and one source pole couples voltage source V BAT.Output circuit 195 comprises inverter 196 and 197, inverter 196 is coupled between voltage source V BAT and the power supply VSS and has that an input couples node N1 and an output couples inverter 197, and inverter 197 is coupled between voltage source V BAT and the power supply VSS and has an input and couples inverter 196 and an output with output signal output Vout.
Because conventional voltage transducer 100 can be applied in the logical block of computer system, when computer system does not provide voltage source V DD or voltage source V DD to be electronegative potential, because the node N1 of electric pressure converter 100 is a suspension joint, so the inverter 196 of output circuit 195 and 197 can produce leakage current.
Summary of the invention
The invention provides a kind of electric pressure converter, be biased between a voltage source and an earthing power supply, in order to convert an input signal to an output signal, include: one first anti-phase module and one second anti-phase module, all receive an external power supply and input signal, in order to export one first output signal, wherein when input signal be high potential or when external power supply is electronegative potential, the first anti-phase module rp input signal is to export first output signal, when input signal is an electronegative potential and when external power supply was high potential, it was high potential that the second anti-phase module makes the output signal of winning; One first reverse-phase protection circuit is connected to the first anti-phase module and the second anti-phase module, receives first output signal to export one second output signal, and when first output signal was high potential, the first reverse-phase protection circuit made that second output signal is an electronegative potential; One second reverse-phase protection circuit, be connected to the second anti-phase module, receiving inputted signal is to export one the 3rd output signal, when input signal is high potential, the second reverse-phase protection circuit makes that the 3rd output signal is an electronegative potential, and wherein the 3rd output signal is opposite with the second output signal current potential; One latch circuit receives second output signal, the 3rd output signal and voltage source; And an output circuit, according to the second output signal level output signal output.
The present invention more provides a kind of voltage conversion method, in order to convert input signal to output signal, comprising: export one first output signal according to input signal and external power supply signal, produce one the 3rd output signal according to input signal; Produce one second output signal according to first output signal and the 3rd output signal; Produce output signal according to second output signal.
Description of drawings
For described and other purposes of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and conjunction with figs., be described in detail as follows:
Fig. 1 is for showing the schematic diagram of conventional voltage transducer; And
Fig. 2 is for showing the schematic diagram according to electric pressure converter of the present invention.
Fig. 3 shows input signal of the present invention, external power supply, the graph of a relation of each node voltage and output signal.
The main element symbol description
100～conventional voltage transducer
110～anti-phase module
111,112,161,163,164,165,181,183,184,185～nmos pass transistor
113,141,142,162,182～PMOS transistor
121, N1, N2, X1, X2, X3, X4～node
140,240～latch circuit
160,180～negative circuit
195,295～output circuit
196,197,235,296,297～inverter
200～electric pressure converter
210,230～anti-phase module
260,280～reverse-phase protection circuit
R1, R2, R3, R4～resistance
C1, C2～electric capacity
T1, T4, T5, T6, T7, T8, T9, T10～nmos pass transistor
T2, T3, T11, T12～PMOS transistor
VDD～voltage source
VSS～power supply
Vout～output signal
Vin～input signal
Vex～external power supply
VBAT～voltage source
Embodiment
Fig. 2 shows the schematic diagram of electric pressure converter 200 according to an embodiment of the invention.Electric pressure converter 200 comprises anti-phase module 210 and 230, reverse- phase protection circuit 260 and 280, latch circuit 240 and output circuit 295.
Anti-phase module 210 has resistance R 2, nmos pass transistor T1 and PMOS transistor T 2 and T3, resistance R 2 is coupled between PMOS transistor T 3 and the voltage source V BAT, nmos pass transistor T1 has a drain electrode and couples nodes X 1, one grid receiving inputted signal Vin and one source pole couple power supply VSS, PMOS transistor T 2 has a drain electrode and couples nodes X 1, one grid couples the drain electrode that external power supply Vex and one source pole couple PMOS transistor T 3, and PMOS transistor T 3 has the source electrode that a drain electrode couples PMOS transistor T 2, one grid couples the end that input signal Vin and one source pole couple resistance R 2.
Anti-phase module 230 has inverter 235 and nmos pass transistor T4.Inverter 235 has an input and couples nodes X 2 and couple nmos pass transistor T4 with a receiving inputted signal Vin and an output, nmos pass transistor T4 has a drain electrode and couples nodes X 1, a grid and couple the output that external power supply Vex and one source pole couple inverter 235, and resistance R 1 couples nodes X 2 and power supply VSS in addition.
Reverse-phase protection circuit 260 comprises nmos pass transistor T5; T6 and T7; resistance R 3 and capacitor C 1; nmos pass transistor T5 has a drain electrode and couples nmos pass transistor T6; one grid couples nodes X 1 and one source pole couples power supply VSS; nmos pass transistor T6 has a drain electrode and couples nmos pass transistor T7; one grid couples resistance R 3 and capacitor C 1 and one source pole and couples nmos pass transistor T5; nmos pass transistor T7 has a drain electrode and couples nodes X 3; one grid couples voltage source V BAT and one source pole couples nmos pass transistor T6; resistance R 3 is coupled between the grid and voltage source V BAT of nmos pass transistor T6, and capacitor C 1 is coupled between resistance R 3 and the power supply Vss.
Reverse-phase protection circuit 280 comprises nmos pass transistor T8; T9 and T10 resistance R 4 and capacitor C 2; nmos pass transistor T8 has a drain electrode and couples nmos pass transistor T9; one grid couples nodes X 2 and one source pole couples power supply VSS; nmos pass transistor T9 has a drain electrode and couples nmos pass transistor T10; one grid couples resistance R 4 and capacitor C 2 and one source pole and couples nmos pass transistor T8; nmos pass transistor T10 has a drain electrode and couples nodes X 4; one grid couples voltage source V BAT and one source pole couples nmos pass transistor T9; resistance R 4 is coupled between the grid and voltage source V BAT of nmos pass transistor T9, and capacitor C 2 is coupled between resistance R 4 and the power supply VSS.
Latch circuit 240 comprises PMOS transistor T 11 and T12, PMOS transistor T 11 have one the drain electrode couple nodes X 3, a grid couples nodes X 4 and one source pole couples voltage source V BAT, PMOS transistor T 12 have one the drain electrode couple nodes X 4, a grid couples nodes X 3 and one source pole couples voltage source V BAT.Output circuit 295 comprises inverter 296 and 297, inverter 296 is coupled between voltage source V BAT and the power supply Vss and has that an input couples nodes X 3 and an output couples inverter 297, and inverter 297 is coupled between voltage source V BAT and the power supply VSS and has an input and couples inverter 296 and an output with output signal output Vout.
In the present invention, the voltage range of supposing input signal Vin and external power supply Vex is 0～0.9 volt (also can be 0～1.2 volt), voltage source V BAT is 3.3 volts, power supply VSS is an earthing power supply, therefore the voltage range of output signal Vout is 0～3.3 volt, in theory, when input signal Vin is low voltage level (for example: 0 volt), output signal Vout is low voltage level (for example: 0 volt), when input signal Vin was high-voltage level (for example: 0.9 volt), output signal Vout also was high-voltage level (for example: 3.3 volts).Below out of the ordinary four kinds of different situations are discussed.
Please refer to Fig. 2, first embodiment of the invention, when supposing that external power supply Vex and input signal Vin are high-voltage level (for example: 0.9 volt), then nodes X 2 is a high-voltage level, nmos pass transistor T8 conducting, nmos pass transistor T4 conducting, nmos pass transistor T1 conducting, nodes X 1 is a low voltage level, so not conducting of nmos pass transistor T5.In addition because the current potential of the grid of nmos pass transistor T6, T7, T9 and T10 is all voltage source V BAT, therefore nmos pass transistor T6, T7, T9 and T10 conducting, so nodes X 4 is a low voltage level, 11 conductings of PMOS transistor T, therefore nodes X 3 is high-voltage level (VBAT), the output signal (Vout=VBAT) that output circuit 295 receives from the signal and the output HIGH voltage level (for example: 3.3 volts) of nodes X 3.
Please refer to Fig. 2, second embodiment of the invention, suppose that external power supply Vex is that high-voltage level (for example: 0.9 volt) and input signal Vin are when being low voltage level (for example: 0 volt), then nodes X 2 is a low voltage level, not conducting of nmos pass transistor T8, nmos pass transistor T4 conducting, nodes X 1 is a high-voltage level, makes nmos pass transistor T5 conducting.Because the current potential of the grid of nmos pass transistor T6, T7, T9 and T10 is voltage source V BAT, therefore nmos pass transistor transistor T 6, T7, T9 and T10 conducting, nodes X 3 is a low voltage level, 12 conductings of PMOS transistor T, X4 is a high-voltage level, and output circuit 295 receives from the signal of the low voltage level of nodes X 3 with output LOW voltage level () output signal Vout for example: 0 volt.
Please refer to Fig. 2, third embodiment of the invention, suppose that external power supply Vex is that low voltage level (for example: 0 volt) and input signal Vin are when being high-voltage level (for example: 0.9 volt), then nodes X 2 is a high-voltage level, nmos pass transistor T8 conducting, not conducting of nmos pass transistor T4, nmos pass transistor T1 conducting, nodes X 1 is a low voltage level, not conducting of nmos pass transistor T5.Because the current potential of the grid of nmos pass transistor T6, T7, T9 and T10 is voltage source V BAT, therefore nmos pass transistor transistor T 6, T7, T9 and T10 conducting, nodes X 4 is a low voltage level, 11 conductings of PMOS transistor T, nodes X 3 is a high-voltage level, and output circuit 295 receives from the signal of the high-voltage level of nodes X 3 and the output signal (Vout=VBAT) of output HIGH voltage level (for example: 3.3 volts).
Please refer to Fig. 2, fourth embodiment of the invention, when supposing that external power supply Vex and input signal Vin are all low voltage level (for example: 0 volt), then nodes X 2 is a low voltage level, not conducting of nmos pass transistor T8, not conducting of nmos pass transistor T4, nmos pass transistor T2 and T3 conducting, therefore nodes X 1 is a high-voltage level, nmos pass transistor T5 conducting.The current potential of the grid of nmos pass transistor T6, T7, T9 and T10 is voltage source V BAT, therefore nmos pass transistor transistor T 6, T7, T9 and T10 conducting, nodes X 3 is a low voltage level, 12 conductings of PMOS transistor T, nodes X 4 is a high-voltage level, and output circuit 295 receives from the signal of the low voltage level of nodes X 3 to export a low voltage level () output signal Vout for example: 0 volt.
Figure 3 shows that the graph of a relation of input signal VIN among described four embodiment and external power supply Vex resulting each node voltage and output signal Vout under different situations.Can find that by the 3rd figure electric pressure converter 200 can be not low voltage potential or high voltage potential because of external power supply Vex, and influence the running of electric pressure converter 200.Therefore when electric pressure converter 200 receiving inputted signal Vin are low voltage potential (for example: 0 volt), electric pressure converter 200 output LOW voltage current potentials (for example: 0 volt), when electric pressure converter 200 receiving inputted signal Vin are high voltage potential (for example: 0.9 volt), 200 output HIGH voltage current potentials of electric pressure converter (for example: 3.3 volts), in case when being electronegative potential unlike conventional voltage transducer 100 voltage source V DD, the node N1 of electric pressure converter 100 is a suspension joint, so the inverter 196 of the output circuit 195 of electric pressure converter 100 and 197 can produce leakage current.
In sum, though the present invention with preferred embodiment openly as above, so it is not in order to limit the present invention.Those of ordinary skill under any in the technical field under the situation that does not break away from the spirit and scope of the present invention, can carry out various changes and modification.Therefore, protection scope of the present invention is as the criterion with the scope of the claim that proposed.

Claims (17)

1. an electric pressure converter is biased between a voltage source and an earthing power supply, in order to convert an input signal to an output signal, comprising:
One first anti-phase module and one second anti-phase module, all receive an external power supply and described input signal, in order to export one first output signal, wherein when described input signal be high potential or when described external power supply is electronegative potential, the anti-phase described input signal of the described first anti-phase module is to export described first output signal, when described input signal is an electronegative potential and when described external power supply was high potential, the described second anti-phase module made that described first output signal is a high potential;
One first reverse-phase protection circuit, be connected to the described first anti-phase module and the described second anti-phase module, receive described first output signal to export one second output signal, when described first output signal was high potential, the described first reverse-phase protection circuit made that described second output signal is an electronegative potential;
One second reverse-phase protection circuit, be connected to the described second anti-phase module, receive described input signal to export one the 3rd output signal, when described input signal is high potential, the described second reverse-phase protection circuit makes that described the 3rd output signal is an electronegative potential, and wherein said the 3rd output signal is opposite with the described second output signal current potential;
One latch circuit receives described second output signal, described the 3rd output signal and described voltage source; And
One output circuit receives described second output signal, in order to export described output signal according to described second output signal level.
2. electric pressure converter as claimed in claim 1 also comprises one first resistance, is coupled between the input and described earthing power supply of the described second anti-phase module.
3. electric pressure converter as claimed in claim 1, wherein said output circuit comprises:
One first inverter receives described voltage source and described earthing power supply, and described second output signal is anti-phase to export one the 4th output signal; And
One second inverter receives described voltage source and described earthing power supply, and described the 4th output signal is anti-phase to export described output signal.
4. electric pressure converter as claimed in claim 1, the wherein said first anti-phase module comprises:
One the first transistor, drain electrode is connected to the described first reverse-phase protection circuit, and source electrode couples described earthing power supply, and grid receives described input signal;
One transistor seconds, drain electrode is connected to the drain electrode of described the first transistor, and grid receives described external power supply;
One the 3rd transistor, drain electrode is connected to the source electrode of described transistor seconds, and grid receives described input signal, and source electrode receives described voltage source.
5. electric pressure converter as claimed in claim 4, the wherein said first anti-phase module also comprises: the two ends of one second resistance are connected to described voltage source and the described the 3rd transistorized source electrode.
6. electric pressure converter as claimed in claim 1, the wherein said second anti-phase module comprises:
One the 3rd inverter receives described input signal, in order to described input signal is anti-phase; And
One the 4th transistor, grid receives described external power supply, and wherein when described external power supply was high potential, exporting the anti-phase of described input signal was described first output signal.
7. electric pressure converter as claimed in claim 1, the wherein said first reverse-phase protection circuit comprises:
One the 5th transistor, grid receive described first output signal, and source electrode receives described earthing power supply;
One the 6th transistor, grid receives described voltage source, and source electrode is connected with described the 5th transistor drain; And
One the 7th transistor, grid receives described voltage source, and drain electrode is connected to described latch circuit, and exports described second output signal, and source electrode is connected to the 6th transistor drain.
8. electric pressure converter as claimed in claim 7, wherein said latch circuit include 1 the tenth two-transistor, and grid receives described second output signal, and source electrode receives described voltage source, and drain electrode connects the described second reverse-phase protection circuit.
9. electric pressure converter as claimed in claim 7, the wherein said first reverse-phase protection circuit also comprises: one the 3rd resistance, an end connects described voltage source, and an end is connected to the described the 6th transistorized grid; And one first electric capacity, an end connects described earthing power supply, and an end is connected to the described the 6th transistorized grid.
10. electric pressure converter as claimed in claim 1, the wherein said second reverse-phase protection circuit comprises:
One the 8th transistor, grid receives described input signal, and source electrode connects described earthing power supply;
One the 9th transistor, grid receives described voltage source, and source electrode is connected to described the 8th transistor drain; And
The tenth transistor, grid receives described voltage source, and drain electrode is connected to described latch circuit, and exports described the 3rd output signal, and source electrode is connected to described the 9th transistor drain.
11. electric pressure converter as claimed in claim 10; wherein said latch circuit includes 1 the 11 transistor; grid receives described the 3rd output signal; source electrode receives described voltage source; drain electrode connects the described first reverse-phase protection circuit; wherein when described first output signal was electronegative potential, described the 11 transistor made that described second output signal is a high potential.
12. electric pressure converter as claimed in claim 10, the wherein said second reverse-phase protection circuit also comprises: one the 4th resistance, and an end connects described voltage source, and an end is connected to the described the 9th transistorized grid; And one second electric capacity, an end connects described earthing power supply, and an end is connected to the described the 9th transistorized grid.
13. a voltage conversion method, in order to convert an input signal to an output signal, described method comprises:
Export one first output signal according to the current potential of described input signal and the current potential of an external power supply signal;
Current potential according to described input signal produces one the 3rd output signal;
Produce one second output signal according to the current potential of described first output signal and the current potential of described the 3rd output signal; And
Current potential according to described second output signal produces described output signal.
14. as the voltage conversion method of claim 13, wherein when described input signal be high potential or when described external power supply signal is electronegative potential, make that described first output signal is the anti-phase of described input signal; Wherein when described input signal be electronegative potential and described external power supply signal when being high potential, make that described first output signal is a high potential.
15., wherein when described first output signal is high potential, make that described second output signal is an electronegative potential, and described output signal also is an electronegative potential as the voltage conversion method of claim 13.
16. as the voltage conversion method of claim 13, wherein when described input signal is high potential, make that described the 3rd output signal is an electronegative potential, and make that described second output signal is that high potential and described output signal also are high potential.
17. as the voltage conversion method of claim 13, wherein said second output signal and described the 3rd output signal current potential are opposite.
CNB2006101640509A 2006-12-06 2006-12-06 Voltage converter and its method Active CN100468934C (en)

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Application Number Priority Date Filing Date Title
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CN100468934C true CN100468934C (en) 2009-03-11

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