CN219577036U - Level conversion circuit from low voltage to positive and negative voltage - Google Patents
Level conversion circuit from low voltage to positive and negative voltage Download PDFInfo
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- CN219577036U CN219577036U CN202223328116.7U CN202223328116U CN219577036U CN 219577036 U CN219577036 U CN 219577036U CN 202223328116 U CN202223328116 U CN 202223328116U CN 219577036 U CN219577036 U CN 219577036U
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Abstract
The embodiment of the utility model provides a low-voltage to positive and negative voltage level conversion circuit, which belongs to the technical field of level conversion circuits, and comprises first to eighth PMOS transistors and first to fourth NMOS transistors, wherein: the grid electrode of the first PMOS transistor is used for being connected with a first input signal, the source electrode of the first PMOS transistor is used for being connected with a positive voltage, the drain electrode of the first PMOS transistor is connected with the source electrode of the third PMOS transistor, the grid electrode of the third PMOS transistor is grounded, and the drain electrode of the third PMOS transistor is used for being connected with a first output signal; the grid electrode of the sixth PMOS transistor is used for being connected with a second input signal, the source electrode of the sixth PMOS transistor is used for being connected with a positive voltage, the drain electrode of the sixth PMOS transistor is connected with the source electrode of the eighth PMOS transistor, the grid electrode of the eighth PMOS transistor is grounded, and the drain electrode of the eighth PMOS transistor is used for being connected with a second output signal. The low-voltage to positive and negative voltage level conversion circuit provided by the embodiment of the utility model has the advantages of simple structure, convenience in construction, low power consumption and cost and high reliability.
Description
Technical Field
The utility model relates to the technical field of level conversion circuits, in particular to a level conversion circuit from low voltage to positive and negative voltage.
Background
The radio frequency switch is the most commonly used radio frequency component, is used for channel switching and receiving and transmitting state switching in a radio frequency link, and is widely applied to a plurality of fields such as the Internet of things, a communication base station, a small base station, a repeater, a testing instrument, a radar, wiFi (wireless fidelity), RFID (Radio Frequency Identification ) and the like. The radio frequency antenna switch is connected between the antenna and the radio frequency processing circuit and used for switching the working state of the antenna, switching the frequency band and receiving and transmitting signals. Through the switch, signals with different frequency bands and different systems can be separated and then output to different systems of the mobile phone for processing, so that mutual interference among different signals is reduced, and signal receiving sensitivity is improved. The radio frequency switch is an essential key device of the radio frequency front end of the mobile phone, and the quality of the performance directly determines the signal quality of the mobile phone terminal. Since SOI (Silicon-On-Insulator) has high speed, high isolation and excellent radiation resistance, and has advantages that GaAs (gallium arsenide) technology cannot be compared with, SOI technology has become a preferred technology for radio frequency switches in the field of wireless communication in recent years.
The radio frequency switch mainly comprises a local oscillator, a negative pressure generating circuit, a low-voltage to positive-negative voltage converting circuit and a switch core transistor. The low-to-positive voltage conversion circuit needs to convert the normal control signal into a control signal in the positive and negative voltage domain, which is typically 1 time greater than the voltage of the normal control signal; meanwhile, the current driving capability of the on-chip negative voltage generating circuit is generally low, so that the low-voltage to positive-negative voltage conversion circuit is required to have the characteristics of high reliability, low power consumption and the like.
Fig. 1 shows a prior art low-to-positive voltage conversion circuit. The circuit proposes to use two different partial negative voltages (Vss 1 and Vss 2) to convert the standard control signal into control signals of positive and negative voltage domains (VDD, on and Vss 1) by means of two-stage conversion. The circuit can effectively convert standard control signals into positive and negative voltage domains, and the reliability of transistors in the circuit can be ensured through different voltage domains. But it requires two negative voltage generating circuits, two local oscillators and two negative voltage charge pump circuits, which may result in an increase in power consumption and cost of the entire system.
Fig. 2 shows another prior art low-to-positive voltage conversion circuit. The first stage circuit in the circuit is connected with the capacitor C through the boosting capacitor boost The control signal amplitude of the standard voltage domain is increased to control the second stage circuit. The output signal swing of the second stage circuit is from negative supply voltage to positive supply voltage. In this circuit, an input signal whose signal swing is negative to positive power supply voltage is changed to an output signal of negative to 0 voltage by a pull-down driver circuit of a third pole. The pull-down driver circuit of the third stage is eliminated, the circuit adopts a two-stage circuit, simultaneously adopts a plurality of directors and capacitors, and also adopts standard transistors and thick gate transistors, thereby not only increasing the power consumption of the circuit, but also greatly increasing the cost of the circuit.
Disclosure of Invention
In order to solve the technical defects, the embodiment of the utility model provides a low-voltage-to-positive-voltage level conversion circuit with low power consumption, low cost and high reliability.
According to an embodiment of the present utility model, there is provided a level conversion circuit from low voltage to positive and negative voltage, including first to eighth PMOS transistors, first to fourth NMOS transistors, wherein:
the grid electrode of the first PMOS transistor is used for being connected with a first input signal, the source electrode of the first PMOS transistor is used for being connected with a positive voltage, the drain electrode of the first PMOS transistor is connected with the source electrode of the third PMOS transistor, the grid electrode of the third PMOS transistor is grounded, and the drain electrode of the third PMOS transistor is used for being connected with a first output signal;
the grid electrode of the sixth PMOS transistor is used for being connected with a second input signal, the source electrode of the sixth PMOS transistor is used for being connected with a positive voltage, the drain electrode of the sixth PMOS transistor is connected with the source electrode of the eighth PMOS transistor, the grid electrode of the eighth PMOS transistor is grounded, and the drain electrode of the eighth PMOS transistor is used for being connected with a second output signal;
the source electrode of the second PMOS transistor is used for being connected with a positive voltage, the drain electrode of the second PMOS transistor is connected with the source electrode of the fourth PMOS transistor, the drain electrode of the fourth PMOS transistor is connected with the drain electrode of the first NMOS transistor, the source electrode of the first NMOS transistor is connected with the drain electrode of the second NMOS transistor, and the source electrode of the second NMOS transistor is used for being connected with a negative voltage;
the source electrode of the fifth PMOS transistor is used for being connected with a positive voltage, the drain electrode of the fifth PMOS transistor is connected with the source electrode of the seventh PMOS transistor, the drain electrode of the seventh PMOS transistor is connected with the drain electrode of the third NMOS transistor, the source electrode of the third NMOS transistor is connected with the drain electrode of the fourth NMOS transistor, and the source electrode of the fourth NMOS transistor is used for being connected with a negative voltage;
the grid electrode of the second PMOS transistor is connected with the drain electrode of the fifth PMOS transistor, the grid electrode of the fifth PMOS transistor is connected with the drain electrode of the second PMOS transistor, the grid electrode of the fourth PMOS transistor, the grid electrode of the seventh PMOS transistor, the grid electrode of the first NMOS transistor and the grid electrode of the third NMOS transistor are all grounded, the grid electrode of the second NMOS transistor is connected with the drain electrode of the fourth NMOS transistor, and the grid electrode of the fourth NMOS transistor is connected with the drain electrode of the second NMOS transistor.
The low-voltage to positive-negative-voltage level conversion circuit provided by the embodiment of the utility model has the advantages that the second PMOS transistor, the fifth PMOS transistor, the second NMOS transistor and the fourth NMOS transistor are all of negative resistance structures, so that the conversion gain of the level conversion circuit can be improved; and the first NMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the seventh PMOS transistor and the eighth PMOS transistor are adopted to carry out overvoltage protection on the circuit, so that the voltage difference of any two ports in three ports of each transistor of the circuit is not more than one power supply voltage, and the reliability of the circuit is well protected. Therefore, the low-voltage to positive and negative voltage level conversion circuit provided by the embodiment of the utility model has the advantages of simple structure, convenience in construction, low power consumption and cost and high reliability.
Drawings
The accompanying drawings, which are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate embodiments of the utility model and together with the description serve to explain the utility model and do not constitute a limitation on the utility model. In the drawings:
FIG. 1 is a circuit diagram of a prior art low-to-positive voltage conversion circuit;
FIG. 2 is a circuit diagram of another prior art low-to-positive voltage conversion circuit;
FIG. 3 is a circuit diagram of a low-to-positive voltage level shifter circuit according to an embodiment of the present utility model;
fig. 4 is a schematic diagram of input and output waveforms of a low-to-positive voltage level shifter circuit according to an embodiment of the present utility model.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present utility model more apparent, the following detailed description of exemplary embodiments of the present utility model is provided in conjunction with the accompanying drawings, and it is apparent that the described embodiments are only some embodiments of the present utility model and not exhaustive of all embodiments. It should be noted that, without conflict, the embodiments of the present utility model and features of the embodiments may be combined with each other.
In one aspect, an embodiment of the present utility model provides a level shifter circuit for converting a low voltage to a positive voltage and a negative voltage, as shown in fig. 3, including first to eighth PMOS transistors (P-channel metal oxide semiconductor field effect transistors), and first to fourth NMOS transistors (N-channel metal oxide semiconductor field effect transistors), wherein:
the grid electrode of the first PMOS transistor MP1 is used for being connected with a first input signal VIP, the source electrode is used for being connected with a positive voltage VDD, the drain electrode is connected with the source electrode of the third PMOS transistor MP3, the grid electrode of the third PMOS transistor MP3 is grounded, and the drain electrode is used for being connected with a first output signal VON;
the gate of the sixth PMOS transistor MP6 is connected to the second input signal VIN, the source is connected to the positive voltage VDD, the drain is connected to the source of the eighth PMOS transistor MP8, the gate of the eighth PMOS transistor MP8 is grounded, and the drain is connected to the second output signal VOP;
the source electrode of the second PMOS transistor MP2 is used for being connected with a positive voltage VDD, the drain electrode of the second PMOS transistor MP4 is connected with the source electrode of the fourth PMOS transistor MP4, the drain electrode of the fourth PMOS transistor MP4 is connected with the drain electrode of the first NMOS transistor MN1, the source electrode of the first NMOS transistor MN1 is connected with the drain electrode of the second NMOS transistor MN2, and the source electrode of the second NMOS transistor MN2 is used for being connected with a Negative voltage Negative VDD;
the source electrode of the fifth PMOS transistor MP5 is used for being connected with a positive voltage VDD, the drain electrode of the fifth PMOS transistor MP7 is connected with the source electrode of the seventh PMOS transistor MP7, the drain electrode of the seventh PMOS transistor MP7 is connected with the drain electrode of the third NMOS transistor MN3, the source electrode of the third NMOS transistor MN3 is connected with the drain electrode of the fourth NMOS transistor MN4, and the source electrode of the fourth NMOS transistor MN4 is used for being connected with a Negative voltage Negative VDD;
the grid electrode of the second PMOS transistor MP2 is connected with the drain electrode of the fifth PMOS transistor MP5, the grid electrode of the fifth PMOS transistor MP5 is connected with the drain electrode of the second PMOS transistor MP2, the grid electrode of the fourth PMOS transistor MP4, the grid electrode of the seventh PMOS transistor MP7, the grid electrode of the first NMOS transistor MN1 and the grid electrode of the third NMOS transistor MN3 are grounded, the grid electrode of the second NMOS transistor MN2 is connected with the drain electrode of the fourth NMOS transistor MN4, and the grid electrode of the fourth NMOS transistor MN4 is connected with the drain electrode of the second NMOS transistor MN 2.
The low-voltage to positive-negative-voltage level conversion circuit of the embodiment of the utility model is at least composed of 8 PMOS transistors and 4 NMOS transistors. There are two voltage sources in the circuit, namely positive voltage VDD and Negative voltage Negative VDD. The level conversion achieved by the present utility model may be, for example, from 0-1.8V to ±1.8V, or from 0-2.5V to ±2.5V, etc.
The first input signal VIP and the second input signal VIN are preferably a pair of differential signals having voltages of 0 to VDD, and the input signals VIP and VIN are input to the circuit and output as a pair of differential signals VON and VOP from Negative VDD to VDD. MP1, MP3, MP6, and MP8 transistors are used to convert an input signal into a current signal for injection into an intermediate main circuit to control the output signal of the main circuit. Specifically, when the first input signal VIP is at a high level and the second input signal VIN is at a low level, both MP1 and MP3 are not turned on, and both MP6 and MP8 are turned on, so that the first output signal VON is at a low level and the second output signal VOP is at a high level; the upper half part (used as a pull-up circuit) MP2 and MP4 in the main circuit are not conducted, and MP5 and MP7 are conducted, so that the pull-up circuit does not pull up the low-level signal VON and only pulls up the high-level signal VOP (pulls up to VDD); the lower half of the main circuit (used as a pull-down circuit) MN1, MN2 is on, and MN3, MN4 is off, so that the pull-down circuit does not pull down the high level signal VOP, but only pulls down the low level signal VON (to Negative VDD). When VIP is low and VIN is high, the operation states of the transistors are opposite, and the operation principle is similar to that described above, and the description is omitted here.
Fig. 4 is a schematic diagram of input and output waveforms of the level conversion circuit from low voltage to positive and negative voltage in the embodiment of the present utility model when the input signal frequency is 25KHz, wherein the dotted waveform is the input waveform and the solid waveform is the output waveform. As can be seen from fig. 4, the circuit can well convert a normal signal into a signal in a voltage domain of + -2.5V under an input waveform of 25 KHz. Since all transistors operate in the digital circuit state with a large conversion gain, the circuit consumes less than 1uA at 25KHz signal frequency.
The level conversion circuit from low voltage to positive and negative voltage in the embodiment of the utility model, wherein the second PMOS transistor MP2, the fifth PMOS transistor MP5, the second NMOS transistor MN2 and the fourth NMOS transistor MN4 are all of negative resistance structures, so that the conversion gain of the level conversion circuit can be improved; and the first NMOS transistor MN1, the third NMOS transistor MN3, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 are adopted to carry out overvoltage protection on the circuit, so that the voltage difference of any two ports in three ports of each transistor of the circuit is not more than one power supply voltage, and the reliability of the circuit is well protected. Therefore, the low-voltage to positive and negative voltage level conversion circuit provided by the embodiment of the utility model has the advantages of simple structure, convenience in construction, low power consumption and cost and high reliability.
In a preferred embodiment, the low-to-positive voltage level shifter circuit of the present utility model may further include a fifth NMOS transistor MN5, wherein:
the gate of the fifth NMOS transistor MN5 is connected to the first input signal VIP, the drain is connected to the drain of the first PMOS transistor MP1, and the source is grounded.
Therefore, when the input signal of the branch circuit connected with the MN5 is in a high level, the MN5 transistor is conducted to perform pressure relief, so that the potential of the point connected with the MN5 is directly pulled down to a low level, and the conversion gain of the level conversion circuit from the low level to the positive and negative voltage is further improved.
In a preferred embodiment, the low-to-positive voltage level shifter circuit of the present utility model may further include a sixth NMOS transistor MN6, wherein:
the gate of the sixth NMOS transistor MN6 is connected to the second input signal VIN, the drain is connected to the drain of the sixth PMOS transistor MP6, and the source is grounded.
Thus, when the input signal of the branch circuit connected with the MN6 is high level, the MN6 transistor is conducted to perform pressure relief, so that the potential of the point connected with the MN6 is directly pulled down to low level rapidly, and the conversion gain of the level conversion circuit from low voltage to positive and negative voltage is further improved.
In a preferred embodiment, all transistors may be thin gate transistors to further reduce cost.
On the other hand, the embodiment of the utility model provides electronic equipment, which comprises the level conversion circuit from low voltage to positive and negative voltage. Since the structure of the level shifter is the same as above, the description thereof will not be repeated here. Here, the electronic device may be a radio frequency switch, or various devices such as a mobile terminal including the radio frequency switch.
In the electronic device of the embodiment of the utility model, the second PMOS transistor MP2, the fifth PMOS transistor MP5, the second NMOS transistor MN2 and the fourth NMOS transistor MN4 in the level conversion circuit from low voltage to positive and negative voltage are all of negative resistance structures, so that the conversion gain of the level conversion circuit can be improved; and the first NMOS transistor MN1, the third NMOS transistor MN3, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 are adopted to carry out overvoltage protection on the circuit, so that the voltage difference of any two ports in three ports of each transistor of the circuit is not more than one power supply voltage, and the reliability of the circuit is well protected. Therefore, the electronic equipment provided by the embodiment of the utility model has the advantages of simple structure, convenience in construction, low power consumption and cost and high reliability.
The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present utility model, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
While preferred embodiments of the present utility model have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the utility model.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present utility model without departing from the spirit or scope of the utility model. Thus, it is intended that the present utility model also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (8)
1. A low-to-positive voltage level shifter circuit comprising first to eighth PMOS transistors, first to fourth NMOS transistors, wherein:
the grid electrode of the first PMOS transistor is used for being connected with a first input signal, the source electrode of the first PMOS transistor is used for being connected with a positive voltage, the drain electrode of the first PMOS transistor is connected with the source electrode of the third PMOS transistor, the grid electrode of the third PMOS transistor is grounded, and the drain electrode of the third PMOS transistor is used for being connected with a first output signal;
the grid electrode of the sixth PMOS transistor is used for being connected with a second input signal, the source electrode of the sixth PMOS transistor is used for being connected with a positive voltage, the drain electrode of the sixth PMOS transistor is connected with the source electrode of the eighth PMOS transistor, the grid electrode of the eighth PMOS transistor is grounded, and the drain electrode of the eighth PMOS transistor is used for being connected with a second output signal;
the source electrode of the second PMOS transistor is used for being connected with a positive voltage, the drain electrode of the second PMOS transistor is connected with the source electrode of the fourth PMOS transistor, the drain electrode of the fourth PMOS transistor is connected with the drain electrode of the first NMOS transistor, the source electrode of the first NMOS transistor is connected with the drain electrode of the second NMOS transistor, and the source electrode of the second NMOS transistor is used for being connected with a negative voltage;
the source electrode of the fifth PMOS transistor is used for being connected with a positive voltage, the drain electrode of the fifth PMOS transistor is connected with the source electrode of the seventh PMOS transistor, the drain electrode of the seventh PMOS transistor is connected with the drain electrode of the third NMOS transistor, the source electrode of the third NMOS transistor is connected with the drain electrode of the fourth NMOS transistor, and the source electrode of the fourth NMOS transistor is used for being connected with a negative voltage;
the grid electrode of the second PMOS transistor is connected with the drain electrode of the fifth PMOS transistor, the grid electrode of the fifth PMOS transistor is connected with the drain electrode of the second PMOS transistor, the grid electrode of the fourth PMOS transistor, the grid electrode of the seventh PMOS transistor, the grid electrode of the first NMOS transistor and the grid electrode of the third NMOS transistor are all grounded, the grid electrode of the second NMOS transistor is connected with the drain electrode of the fourth NMOS transistor, and the grid electrode of the fourth NMOS transistor is connected with the drain electrode of the second NMOS transistor.
2. The low-to-positive voltage level shifter circuit of claim 1, further comprising a fifth NMOS transistor, wherein:
the grid electrode of the fifth NMOS transistor is used for being connected with the first input signal, the drain electrode of the fifth NMOS transistor is connected with the drain electrode of the first PMOS transistor, and the source electrode of the fifth NMOS transistor is grounded.
3. The low-to-positive voltage level shifter circuit of claim 2, further comprising a sixth NMOS transistor, wherein:
the grid electrode of the sixth NMOS transistor is used for being connected with a second input signal, the drain electrode of the sixth NMOS transistor is connected with the drain electrode of the sixth PMOS transistor, and the source electrode of the sixth NMOS transistor is grounded.
4. The low-to-positive voltage level shifter circuit of claim 1, wherein the first input signal and the second input signal are a pair of differential signals having voltages of 0 to positive voltage.
5. The low-to-positive voltage level shifter circuit of claim 4, wherein the first and second input signals are 0-1.8V.
6. The low-to-positive voltage level shifter circuit of claim 4, wherein the first and second input signals are 0-2.5V.
7. The low-to-positive voltage level shifter circuit of claim 4, wherein the first and second output signals are a pair of differential signals from negative voltage to positive voltage.
8. The low-to-positive voltage level shifter of claim 1, wherein all of the transistors are thin gate transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223328116.7U CN219577036U (en) | 2022-12-13 | 2022-12-13 | Level conversion circuit from low voltage to positive and negative voltage |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223328116.7U CN219577036U (en) | 2022-12-13 | 2022-12-13 | Level conversion circuit from low voltage to positive and negative voltage |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219577036U true CN219577036U (en) | 2023-08-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202223328116.7U Active CN219577036U (en) | 2022-12-13 | 2022-12-13 | Level conversion circuit from low voltage to positive and negative voltage |
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| Country | Link |
|---|---|
| CN (1) | CN219577036U (en) |
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- 2022-12-13 CN CN202223328116.7U patent/CN219577036U/en active Active
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