CN210693865U - Low-noise fully-differential high-voltage operational amplifier - Google Patents

Abstract

The utility model relates to a low-noise fully-differential high-voltage operational amplifier, which comprises an input stage circuit, an output stage circuit, an upper cascode circuit which is in adaptive connection with the output stage circuit, and a lower cascode circuit which is in adaptive connection with the output stage circuit; the voltage slew rate maintaining circuit is adaptively connected with the differential output end OUTN and the differential output end OUTP of the output stage circuit, and the bias power supply circuit can provide power supplies required by the input stage circuit, the output stage circuit, the upper cascode circuit and the lower cascode circuit; when the current flowing through the upper cascode circuit is reduced through the bias power supply circuit, the slew rate of the voltage output by the differential output terminal OUTN and the differential output terminal OUTP of the output stage circuit can be improved by using the slew rate retaining circuit, so that the slew rate of the high-voltage operational amplifier is kept stable. The utility model discloses under the condition of effective noise reduction, keep operational amplifier's slew rate index, safe and reliable.

Description

Low-noise fully-differential high-voltage operational amplifier

Technical Field

The utility model relates to a high accuracy total difference high voltage differential operational amplifier, especially a low noise total difference high voltage operational amplifier belong to high voltage operational amplifier's technical field.

Background

The high-voltage operational amplifier has the common characteristic functions of signal acquisition, comparison, amplification, operation and the like, is very suitable for occasions requiring small volume and large output power due to the characteristic of high voltage and large current, is widely applied to all electronic devices requiring high-power output at the final stage, and has wide application in various fields of industrial control systems, communication, automotive electronics, rail transit, new energy conservation, military/civil aerospace, weaponry and the like.

The high-voltage operational amplifier generally includes an input stage circuit, an upper cascode circuit, a lower cascode circuit, an output stage circuit, and the like, where the input stage circuit determines many important parameters of the operational amplifier, such as an input voltage range, a wide band, and the like. The noise of the high-voltage operational amplifier is related to the input stage circuit, the upper cascode circuit and the lower cascode circuit, and the noise of the input stage circuit is N₁Noise of the upper cascode circuit is N₂Noise of the lower cascode circuit is N₃The total noise N of the operational amplifier, which is the total noise reduced from all internal noises to the input end, is:

wherein, gm₁Is transconductance of an input stage circuit，gm₂Transconductance, gm, of the upper cascode circuit₃Is the transconductance of the lower cascode circuit; as will be appreciated by those skilled in the art, the transconductance is proportional to the current flowing, and thus, as can be seen from the above expression of the total noise, reducing the current flowing can reduce the corresponding noise.

Typically, the input stage circuit has a current of I₁The current of the upper cascode circuit is I₂The current of the lower cascode circuit is I₃，I₃＝0.5I₁+I₂. As can be seen from the above description, for a particular high voltage operational amplifier, the current I of the input stage circuit₁Cannot be adjusted generally, otherwise, it will cause the parameters of the high-voltage operational amplifier to change, so that when the noise of the operational amplifier is to be reduced, the current I of the upper cascode circuit can only be reduced₂. When the current I of the upper cascode circuit is reduced₂When the total noise of the operational amplifier is reduced, the Slew Rate (SR) of the operational amplifier is reduced, so that the technical indexes of the high-voltage operational amplifier in use are influenced, and even more matching problems in use are caused; therefore, the conventional high-voltage operational amplifiers cannot effectively reduce noise.

Disclosure of Invention

The utility model aims at overcoming the not enough of existence among the prior art, provide a low noise fully differential high pressure operational amplifier, its under the condition of effective noise reduction, keep operational amplifier's slew rate index, safe and reliable.

According to the technical scheme provided by the utility model, the low-noise fully-differential high-voltage operational amplifier comprises an input stage circuit, an output stage circuit, an upper cascode circuit in adaptive connection with the output stage circuit and a lower cascode circuit in adaptive connection with the output stage circuit; the voltage slew rate maintaining circuit is adaptively connected with the differential output end OUTN and the differential output end OUTP of the output stage circuit, and the bias power supply circuit can provide power supplies required by the input stage circuit, the output stage circuit, the upper cascode circuit and the lower cascode circuit; when the current flowing through the upper cascode circuit is reduced through the bias power supply circuit, the slew rate of the voltage output by the differential output terminal OUTN and the differential output terminal OUTP of the output stage circuit can be improved by using the slew rate retaining circuit, so that the slew rate of the high-voltage operational amplifier is kept stable.

The input stage circuit comprises a PMOS tube PM20 and a PMOS tube PM21, the gate end of the PMOS tube PM20 is connected with the differential input signal INP, and the gate end of the PMOS tube PM21 is connected with the differential input signal INN; the source end of the PMOS pipe PM20 and the source end of the PMOS pipe PM21 are connected with the drain end of a PMOS pipe PM5 in the bias power supply circuit;

the gate terminal of the PMOS tube PM5 is connected with the gate terminal of a PMOS tube PM4, the gate terminal of a PMOS tube PM1, the drain terminal of a PMOS tube PM1, the drain terminal of an NMOS tube NM19 and the gate terminal of a PMOS tube PM17 in the bias power supply circuit;

the source terminal of a PMOS pipe PM1, the source terminal of a PMOS pipe PM2, the source terminal of a PMOS pipe PM3, the source terminal of a PMOS pipe PM16 in the upper cascode circuit, the source terminal of a PMOS pipe PM18 and the source terminal of a PMOS pipe PM19 are all connected with voltage VDD, and the gate terminal of a PMOS pipe PM2 is connected with the gate terminal of a PMOS pipe PM3, the drain terminal of a PMOS pipe PM4 and the drain terminal of an NMOS pipe NM 20; the drain end of the PMOS pipe PM3 is connected with the source end of the PMOS pipe PM5, the drain end of the PMOS pipe PM2 is connected with the source end of the PMOS pipe PM4, the gate end of the PMOS pipe PM19 is connected with the gate end of the PMOS pipe PM18 and the gate end of the PMOS pipe PM16, and the drain end of the PMOS pipe PM17 and the drain end of the NMOS pipe NM10 are connected;

the gate terminal of the NMOS tube NM19, the gate terminal of the NMOS tube NM20, the gate terminal of the NMOS tube NM18, the gate terminal of the NMOS tube NM17 and the drain terminal of the NMOS tube NM17 are all connected with one output terminal of a bias current source, and the gate terminal of the NMOS tube NM10, the gate terminal of the NMOS tube NM14, the gate terminal of the NMOS tube NM15, the gate terminal of the NMOS tube NM16 and the drain terminal of the NMOS tube NM18 are all connected with the other output terminal of the bias current source; the source terminal of the NMOS tube NM18 is connected with the drain terminal of the NMOS tube NM16, the source terminal of the NMOS tube NM19 is connected with the drain terminal of the NMOS tube NM15, the source terminal of the NMOS tube NM20 is connected with the drain terminal of the NMOS tube NM14, the drain terminal of the PMOS tube PM20 is connected with the drain terminal of the NMOS tube NM13 and the drain terminal of the NMOS tube NM13, the drain terminal of the PMOS tube PM21 is connected with the drain terminal of the NMOS tube NM12 and the gate terminal of the NMOS tube NM12, the source terminals of the NMOS tube NM10, NM12, NMOS tube NM13, NM14, NM15, NM16 and NM17 are all grounded, the drain terminals of the PMOS tube PM20, PMOS tube PM21 are also connected with the output stage circuit, and the drain terminals of the PMOS tube PM18 and PM19 are adapted to the output stage circuit.

The offset voltage storage circuit is used for storing offset voltage of the input stage circuit and comprises a PMOS tube PM22 and a PMOS tube PM23, the grid end of the PMOS tube PM22 is connected with one end of a capacitor C2, the grid end of the PMOS tube PM23 is connected with one end of a capacitor C1, the drain end of the PMOS tube PM22 is connected with the drain end of the PMOS tube PM20, and the drain end of the PMOS tube PM23 is connected with the drain end of a PMOS tube PM 21; the other end of the capacitor C1 and the other end of the capacitor C2 are both grounded;

the source terminal of the PMOS tube PM22 and the source terminal of the PMOS tube PM23 are connected with the drain terminal of the PMOS tube PM7, the gate terminal of the PMOS tube PM7 is connected with the gate terminal of the PMOS tube PM5, the source terminal of the PMOS tube PM7 is connected with the drain terminal of the PMOS tube PM6, the gate terminal of the PMOS tube PM6 is connected with the gate terminal of the PMOS tube PM3, and the source terminal of the PMOS tube PM6 is connected with the voltage VDD.

The common-mode voltage generating circuit can provide common-mode voltage required by the output-stage circuit, and comprises a PMOS tube PM24, a PMOS tube PM25, an NMOS tube NM8 and an NMOS tube NM 9;

the gate terminal of the NMOS tube NM9 and the gate terminal of the NMOS tube NM8 are connected with the gate terminal of the NMOS tube NM18, the source terminal of the NMOS tube NM9 is connected with the drain terminal of the NMOS tube NM10, the drain terminal of the PMOS tube PM24 and the drain terminal of the PMOS tube PM25, and the drain terminal of the NMOS tube NM9 is connected with the drain terminal of the PMOS tube PM17, the gate terminal of the PMOS tube PM16, the gate terminal of the PMOS tube PM18 and the gate terminal of the PMOS tube PM 19; the grid end of the PMOS pipe PM24 and the grid end of the PMOS pipe PM25 are connected with the drain end of the PMOS pipe PM9, the drain end of the NMOS pipe NM11 and the grid end of the NMOS pipe NM11, and the source end of the NMOS pipe NM11 is grounded;

the source end of the PMOS pipe PM24 is connected with the drain end of the PMOS pipe PM11 and an output stage circuit, the source end of the PMOS pipe PM25 is connected with the drain end of the PMOS pipe PM13 and an output stage circuit, the drain end of the NMOS pipe NM8 is connected with the drain end of the PMOS pipe PM15, the gate end of an NMOS pipe NM7 and the gate end of an NMOS pipe NM6 in the lower cascode circuit, and the gate end of the NMOS pipe NM5 is connected; the source terminal of the NMOS tube NM5, the source terminal of the NMOS tube NM6 and the source terminal of the NMOS tube NM7 are all grounded, the drain terminal of the NMOS tube NM7 is connected with the source terminal of the NMOS tube NM8 and the output stage circuit, and the drain terminal of the NMOS tube NM5 and the drain terminal of the NMOS tube NM6 are connected with the output stage circuit;

the gate terminal of the PMOS transistor PM9 is connected with the gate terminal of the PMOS transistor PM5, the gate terminal of the PMOS transistor PM11, the gate terminal of the PMOS transistor PM13 and the gate terminal of the PMOS transistor PM15, the source terminal of the PMOS transistor PM9 is connected with the drain terminal of the PMOS transistor PM8, the source terminal of the PMOS transistor PM11 is connected with the drain terminal of the PMOS transistor PM10, the source terminal of the PMOS transistor PM13 is connected with the drain terminal of the PMOS transistor PM12, the source terminal of the PMOS transistor PM15 is connected with the drain terminal of the PMOS transistor PM14, the source terminal of the PMOS transistor PM8, the source terminal of the PMOS transistor PM10, the source terminal of the PMOS transistor PM12 and the source terminal of the PMOS transistor PM14 are all connected with the voltage VDD, and the gate terminal of the PMOS transistor PM8 is connected with the gate terminal of the PMOS transistor PM3, the gate terminal of the PMOS transistor PM 573.

The output stage circuit comprises a first gain amplifier and a second gain amplifier, wherein the input end of the first gain amplifier is respectively connected with the drain end of a PMOS pipe PM19, the drain end of a PMOS pipe PM18, the drain end of a PMOS pipe PM16 and the source end of a PMOS pipe PM17, one output end of the first gain amplifier is connected with the gate end of a PMOS pipe PM28, the other output end of the first gain amplifier is connected with the gate end of a PMOS pipe PM29, the drain end of the PMOS pipe PM28 is connected with the gate end of a PMOS pipe PM26 and the drain end of an NMOS pipe NM3, the drain end of a PMOS pipe PM29 is connected with the gate end of a PMOS pipe PM27 and the drain end of an NMOS pipe NM4, the source end of a PMOS pipe PM26 is connected with the source end of a PMOS pipe PM25, the source end of a PMOS pipe PM 48 is connected with the source end of a PMOS pipe PM24, and the drain ends of a PMOS pipe PM;

the grid end of the NMOS tube NM3 is connected with one output end of the second gain amplifier, the grid end of the NMOS tube NM4 is connected with the other output end of the second gain amplifier, the source end of the NMOS tube NM3 is connected with the drain end of the NMOS tube NM6, one input end of the second gain amplifier and the drain end of the PMOS tube PM20, the source end of the NMOS tube NM4 is connected with the drain end of the NMOS tube NM5, the other input end of the second gain amplifier and the drain end of the PMOS tube PM21, and the third input end of the second gain amplifier is connected with the source end of the NMOS tube NM8 and the drain end of the NMOS tube NM 7;

the drain end of the PMOS pipe PM28, the gate end of the PMOS pipe PM26 and the drain end of the NMOS pipe NM3 are mutually connected to form a differential output end OUTN, and the drain end of the PMOS pipe PM29, the gate end of the PMOS pipe PM27 and the drain end of the NMOS pipe NM4 are mutually connected to form a differential output end OUTP; the slew rate maintaining circuit comprises a bootstrap switch circuit, and the bootstrap switch circuit is in adaptive connection with the differential output end OUTN and the differential output end OUTP.

The bootstrap switch circuit comprises an NMOS tube NM1 and an NMOS tube NM2, the grid end of the NMOS tube NM1, the drain end of the NMOS tube NM1 and the source end of the NMOS tube NM2 are connected with a differential output end OUTN, and the source end of the NMOS tube NM1, the drain end of the NMOS tube NM2 and the grid end of the NMOS tube NM2 are connected with a differential output end OUTP.

The utility model has the advantages that: a slew rate improving circuit is added between a differential output end OUTN and a differential output end OUTP of an output stage circuit, and when the current flowing through an upper cascode circuit is reduced through a bias power supply circuit, the slew rate of the voltage output by the differential output end OUTN and the differential output end OUTP of the output stage circuit can be improved by using a slew rate maintaining circuit, so that the slew rate of the high-voltage operational amplifier is kept stable, and the slew rate index of the operational amplifier is maintained under the condition of effectively reducing noise, and the high-voltage operational amplifier is safe and reliable.

Drawings

Fig. 1 is a schematic circuit diagram of the present invention.

Description of reference numerals: 1-a bias current source, 2-a first gain amplification circuit, and 3-a second gain amplification circuit.

Detailed Description

The invention is further described with reference to the following specific drawings and examples.

As shown in fig. 1: for example, under the condition of effectively reducing noise, the slew rate index of the operational amplifier is kept, the utility model discloses an input stage circuit, an output stage circuit, an upper cascode circuit in adaptive connection with the output stage circuit and a lower cascode circuit in adaptive connection with the output stage circuit; the voltage slew rate maintaining circuit is adaptively connected with the differential output end OUTN and the differential output end OUTP of the output stage circuit, and the bias power supply circuit can provide power supplies required by the input stage circuit, the output stage circuit, the upper cascode circuit and the lower cascode circuit; when the current flowing through the upper cascode circuit is reduced through the bias power supply circuit, the slew rate of the voltage output by the differential output terminal OUTN and the differential output terminal OUTP of the output stage circuit can be improved by using the slew rate retaining circuit, so that the slew rate of the high-voltage operational amplifier is kept stable.

Specifically, the input stage circuit, the output stage circuit, the upper cascode circuit, and the lower cascode circuit may all adopt the existing commonly used circuit form, and the specific coordination among the input stage circuit, the output stage circuit, the upper cascode circuit, and the lower cascode circuit realizes that the process and the principle of amplifying the differential signal are consistent with the existing one, and are specifically known to those skilled in the art, and are not described herein again.

The embodiment of the utility model provides an in, at output stage circuit's differential output OUTN, increase slew rate holding circuit between differential output OUTP, can provide input stage circuit through biasing power supply circuit, output stage circuit, go up the cascode circuit, down cascode circuit and slew rate holding circuit work required power, go up the cascode circuit, the current state relation between lower cascode circuit and the input stage circuit is unanimous with the current relation among this technical technology, the electric current of input stage circuit is I promptly₁The current of the upper cascode circuit is I₂The current of the lower cascode circuit is I₃，I₃＝0.5I₁+I₂. The current flowing through the upper cascode circuit can be reduced by adjusting the parameters of the bias power supply circuit according to the transfer relationship of the current, and the current can be reduced according to the above descriptionWhen the current flowing through the upper cascode circuit is reduced, the current flowing through the lower cascode circuit is also reduced, and the noise of the fully differential high-voltage operational amplifier can be reduced according to the corresponding relation between the current and the transconductance and the corresponding relation between the transconductance and the noise.

As can be seen from the above description, when the current flowing through the upper cascode circuit and the lower cascode circuit is reduced, the slew rate of the fully differential high-voltage operational amplifier is reduced. The embodiment of the utility model provides an in, increase slew rate holding circuit between difference output OUTN, difference output OUTP, can promote through difference output OUTN, difference output OUTP output voltage's slew rate through slew rate holding circuit to make high-pressure operational amplifier's slew rate remain stable. Specifically, the slew rate of the high-voltage operational amplifier is kept stable, that is, the slew rate of the high-voltage operational amplifier is consistent with the slew rate under the condition that the current flowing through the upper cascode circuit and the current flowing through the lower cascode circuit are reduced without reducing the corresponding current flowing through the upper cascode circuit and the corresponding current flowing through the lower cascode circuit, the slew rate can fluctuate within an allowable range in accordance with the consistent slew rate, the specific allowable range can be set according to the requirements of practical applications, and the specific setting process is well known by those skilled in the art and is not described herein again.

Further, the input stage circuit comprises a PMOS transistor PM20 and a PMOS transistor PM21, the gate terminal of the PMOS transistor PM20 is connected with the differential input signal INP, and the gate terminal of the PMOS transistor PM21 is connected with the differential input signal INN; the source end of the PMOS pipe PM20 and the source end of the PMOS pipe PM21 are connected with the drain end of a PMOS pipe PM5 in the bias power supply circuit;

the gate terminal of the PMOS tube PM5 is connected with the gate terminal of a PMOS tube PM4, the gate terminal of a PMOS tube PM1, the drain terminal of a PMOS tube PM1, the drain terminal of an NMOS tube NM19 and the gate terminal of a PMOS tube PM17 in the bias power supply circuit;

the source terminal of a PMOS pipe PM1, the source terminal of a PMOS pipe PM2, the source terminal of a PMOS pipe PM3, the source terminal of a PMOS pipe PM16 in the upper cascode circuit, the source terminal of a PMOS pipe PM18 and the source terminal of a PMOS pipe PM19 are all connected with voltage VDD, and the gate terminal of a PMOS pipe PM2 is connected with the gate terminal of a PMOS pipe PM3, the drain terminal of a PMOS pipe PM4 and the drain terminal of an NMOS pipe NM 20; the drain end of the PMOS pipe PM3 is connected with the source end of the PMOS pipe PM5, the drain end of the PMOS pipe PM2 is connected with the source end of the PMOS pipe PM4, the gate end of the PMOS pipe PM19 is connected with the gate end of the PMOS pipe PM18 and the gate end of the PMOS pipe PM16, and the drain end of the PMOS pipe PM17 and the drain end of the NMOS pipe NM10 are connected;

the gate terminal of the NMOS tube NM19, the gate terminal of the NMOS tube NM20, the gate terminal of the NMOS tube NM18, the gate terminal of the NMOS tube NM17 and the drain terminal of the NMOS tube NM17 are all connected with one output terminal of the bias current source 1, and the gate terminal of the NMOS tube NM10, the gate terminal of the NMOS tube NM14, the gate terminal of the NMOS tube NM15, the gate terminal of the NMOS tube NM16 and the drain terminal of the NMOS tube NM18 are all connected with the other output terminal of the bias current source 1; the source terminal of the NMOS tube NM18 is connected with the drain terminal of the NMOS tube NM16, the source terminal of the NMOS tube NM19 is connected with the drain terminal of the NMOS tube NM15, the source terminal of the NMOS tube NM20 is connected with the drain terminal of the NMOS tube NM14, the drain terminal of the PMOS tube PM20 is connected with the drain terminal of the NMOS tube NM13 and the drain terminal of the NMOS tube NM13, the drain terminal of the PMOS tube PM21 is connected with the drain terminal of the NMOS tube NM12 and the gate terminal of the NMOS tube NM12, the source terminals of the NMOS tube NM10, NM12, NMOS tube NM13, NM14, NM15, NM16 and NM17 are all grounded, the drain terminals of the PMOS tube PM20, PMOS tube PM21 are also connected with the output stage circuit, and the drain terminals of the PMOS tube PM18 and PM19 are adapted to the output stage circuit.

The embodiment of the utility model provides an in, PMOS pipe PM20 and PMOS pipe PM21 constitute the input stage circuit, PMOS pipe PM16, PMOS pipe PM18, PMOS pipe PM19 constitutes the cascode circuit, PMOS pipe PM1, PMOS pipe PM2, PMOS pipe PM3, PMOS pipe PM4, PMOS pipe PM5, PMOS pipe PM17, NMOS pipe NM17, NMOS pipe NM18, NMOS pipe NM19, NMOS pipe NM20, NMOS pipe NM16, NMOS pipe NM15, NMOS pipe NM14, NMOS pipe NM13, NMOS pipe NM12 and NMOS pipe NM10 constitute a part of biasing power supply circuit.

The magnitude of the voltage VDD is selected according to actual needs, and is well known to those skilled in the art. The bias current source 1 can adopt an existing common form, two output ends of the bias current source 1 output currents with the same magnitude, the NMOS tube NM17 can provide bias voltages required by the NMOS tube NM18, the NMOS tube NM19, the NMOS tube NM20, the NMOS tube NM16, the NMOS tube NM15, the NMOS tube NM14, the NMOS tube NM13, the NMOS tube NM12, the NMOS tube NM10 and the like through matching of the NMOS tube NM 3678 and the bias voltage VDD can provide bias voltages required by the PMOS tube PM2, the PMOS tube PM3, the PMOS tube PM4, the PMOS tube PM5 and the PMOS tube PM17 through matching of the PMOS tube PM1 and the voltage VDD.

According to the circuit, the NMOS tube NM18, the NMOS tube NM19, the NMOS tube NM20, the NMOS tube NM16, the NMOS tube NM15, the NMOS tube NM14 and the NMOS tube NM10 form a current mirror, and the current of the upper cascode circuit can form a channel through the PMOS tube PM17 and the NMOS tube NM10, so that the current flowing through the upper cascode circuit can be adjusted when the current flowing through the NMOS tube NM10 is controlled or adjusted. The embodiment of the utility model provides an in, through reducing the electric current that flows through NMOS pipe NM10, can reduce the electric current of the cascode circuit of flowing through, simultaneously, can reduce the electric current of the cascode circuit under flowing through, reach the purpose that reduces high-pressure operational amplifier noise, the mode and the process that the NMOS pipe NM10 electric current was flowed through in the concrete reduction are known for this technical field personnel, and it is no longer repeated here.

The offset voltage storage circuit comprises a PMOS pipe PM22 and a PMOS pipe PM23, the gate end of the PMOS pipe PM22 is connected with one end of a capacitor C2, the gate end of the PMOS pipe PM23 is connected with one end of a capacitor C1, the drain end of the PMOS pipe PM22 is connected with the drain end of the PMOS pipe PM20, and the drain end of the PMOS pipe PM23 is connected with the drain end of a PMOS pipe PM 21; the other end of the capacitor C1 and the other end of the capacitor C2 are both grounded;

the source terminal of the PMOS tube PM22 and the source terminal of the PMOS tube PM23 are connected with the drain terminal of the PMOS tube PM7, the gate terminal of the PMOS tube PM7 is connected with the gate terminal of the PMOS tube PM5, the source terminal of the PMOS tube PM7 is connected with the drain terminal of the PMOS tube PM6, the gate terminal of the PMOS tube PM6 is connected with the gate terminal of the PMOS tube PM3, and the source terminal of the PMOS tube PM6 is connected with the voltage VDD.

The embodiment of the utility model provides an in, the drain terminal of PMOS pipe PM22, the drain terminal of PMOS pipe PM23 still with output stage circuit connection, through PMOS pipe PM22 and electric capacity C2 cooperation and PMOS pipe PM23 and electric capacity C1 cooperation, offset voltage storage circuit can detect and store input stage circuit's offset voltage, and output stage circuit can offset the offset voltage that offset voltage storage circuit obtained to can realize the low detuning and the purpose that the low temperature floats.

The common-mode voltage generating circuit can provide common-mode voltage required by the output-stage circuit, and comprises a PMOS tube PM24, a PMOS tube PM25, an NMOS tube NM8 and an NMOS tube NM 9;

the gate terminal of the NMOS tube NM9 and the gate terminal of the NMOS tube NM8 are connected with the gate terminal of the NMOS tube NM18, the source terminal of the NMOS tube NM9 is connected with the drain terminal of the NMOS tube NM10, the drain terminal of the PMOS tube PM24 and the drain terminal of the PMOS tube PM25, and the drain terminal of the NMOS tube NM9 is connected with the drain terminal of the PMOS tube PM17, the gate terminal of the PMOS tube PM16, the gate terminal of the PMOS tube PM18 and the gate terminal of the PMOS tube PM 19; the grid end of the PMOS pipe PM24 and the grid end of the PMOS pipe PM25 are connected with the drain end of the PMOS pipe PM9, the drain end of the NMOS pipe NM11 and the grid end of the NMOS pipe NM11, and the source end of the NMOS pipe NM11 is grounded;

the source end of the PMOS pipe PM24 is connected with the drain end of the PMOS pipe PM11 and an output stage circuit, the source end of the PMOS pipe PM25 is connected with the drain end of the PMOS pipe PM13 and an output stage circuit, the drain end of the NMOS pipe NM8 is connected with the drain end of the PMOS pipe PM15, the gate end of an NMOS pipe NM7 and the gate end of an NMOS pipe NM6 in the lower cascode circuit, and the gate end of the NMOS pipe NM5 is connected; the source terminal of the NMOS tube NM5, the source terminal of the NMOS tube NM6 and the source terminal of the NMOS tube NM7 are all grounded, the drain terminal of the NMOS tube NM7 is connected with the source terminal of the NMOS tube NM8 and the output stage circuit, and the drain terminal of the NMOS tube NM5 and the drain terminal of the NMOS tube NM6 are connected with the output stage circuit;

the gate terminal of the PMOS transistor PM9 is connected with the gate terminal of the PMOS transistor PM5, the gate terminal of the PMOS transistor PM11, the gate terminal of the PMOS transistor PM13 and the gate terminal of the PMOS transistor PM15, the source terminal of the PMOS transistor PM9 is connected with the drain terminal of the PMOS transistor PM8, the source terminal of the PMOS transistor PM11 is connected with the drain terminal of the PMOS transistor PM10, the source terminal of the PMOS transistor PM13 is connected with the drain terminal of the PMOS transistor PM12, the source terminal of the PMOS transistor PM15 is connected with the drain terminal of the PMOS transistor PM14, the source terminal of the PMOS transistor PM8, the source terminal of the PMOS transistor PM10, the source terminal of the PMOS transistor PM12 and the source terminal of the PMOS transistor PM14 are all connected with the voltage VDD, and the gate terminal of the PMOS transistor PM8 is connected with the gate terminal of the PMOS transistor PM3, the gate terminal of the PMOS transistor PM 573.

The embodiment of the utility model provides an in, cascode circuit under NMOS pipe NM5, NMOS pipe NM6 and NMOS pipe NM7 constitute, NMOS pipe NM8, NMOS pipe NM9, PMOS pipe PM24, PMOS pipe PM25, PMOS pipe PM10, PMOS pipe PM11, PMOS pipe PM12, PMOS pipe PM13, PMOS pipe PM14 and PMOS pipe PM15 constitute common mode voltage and produce the circuit.

Further, the output stage circuit comprises a first gain amplifier 2 and a second gain amplifier 3, an input end of the first gain amplifier 2 is connected with a drain end of a PMOS transistor PM19, a drain end of a PMOS transistor PM18, a drain end of a PMOS transistor PM16 and a source end of the PMOS transistor PM17 respectively, an output end of the first gain amplifier 2 is connected with a gate end of the PMOS transistor PM28, another output end of the first gain amplifier 2 is connected with a gate end of the PMOS transistor PM29, a drain end of the PMOS transistor PM28 is connected with a gate end of the PMOS transistor PM26 and a drain end of the NMOS transistor 3, an NM end of the PMOS transistor PM29 is connected with a gate end of the PMOS transistor PM27 and a drain end of the NMOS transistor NM4, a source end of the PMOS transistor PM26 is connected with a source end of the PMOS transistor PM25, a source end of the PMOS transistor PM27 is connected with a source end of the PMOS transistor PM24, and drain ends of the PMOS transistor PM26 and the PM 27;

the gate terminal of the NMOS transistor NM3 is connected to an output terminal of the second gain amplifier 3, the gate terminal of the NMOS transistor NM4 is connected to another output terminal of the second gain amplifier 3, the source terminal of the NMOS transistor NM3 is connected to the drain terminal of the NMOS transistor NM6, an input terminal of the second gain amplifier 3 and the drain terminal of the PMOS transistor PM20, the source terminal of the NMOS transistor NM4 is connected to the drain terminal of the NMOS transistor NM5, another input terminal of the second gain amplifier 3 and the drain terminal of the PMOS transistor PM21, and the third input terminal of the second gain amplifier 3 is connected to the source terminal of the NMOS transistor NM8 and the drain terminal of the NMOS transistor NM 7;

the drain end of the PMOS pipe PM28, the gate end of the PMOS pipe PM26 and the drain end of the NMOS pipe NM3 are mutually connected to form a differential output end OUTN, and the drain end of the PMOS pipe PM29, the gate end of the PMOS pipe PM27 and the drain end of the NMOS pipe NM4 are mutually connected to form a differential output end OUTP; the slew rate maintaining circuit comprises a bootstrap switch circuit, and the bootstrap switch circuit is in adaptive connection with the differential output end OUTN and the differential output end OUTP.

The embodiment of the utility model provides an in, can carry out required gain through first gain amplifier 2, second gain amplifier 3 and amplify, generally, first gain amplifier 2 adopts identical circuit structure with second gain amplifier 3, and first gain amplifier 2, second gain amplifier 3 can adopt current commonly used circuit form, specifically can select as required, and here is no longer repeated. When the offset voltage storage circuit exists, the drain end of the PMOS transistor PM22 and the drain end of the PMOS transistor PM23 of the offset voltage storage circuit are connected to the corresponding input ends of the second gain amplifier 3, that is, the drain end of the PMOS transistor PM22 is connected to the drain end of the PMOS transistor PM20, and the drain end of the PMOS transistor PM23 is connected to the drain end of the PMOS transistor PM 21.

During specific implementation, the slew rate holding circuit adopts a bootstrap switch circuit, and the characteristics of the bootstrap switch circuit can be utilized to realize the improvement of the slew rates of the output voltages of the differential output terminal OUTN and the differential output terminal OUTP. Of course, in specific implementation, the slew rate holding circuit may also adopt other circuit forms, which may be specifically selected according to needs, as long as the slew rate can be improved, so that the slew rate of the high-voltage operational amplifier can be kept stable.

Further, the bootstrap switch circuit includes an NMOS transistor NM1 and an NMOS transistor NM2, the gate terminal of the NMOS transistor NM1, the drain terminal of the NMOS transistor NM1 and the source terminal of the NMOS transistor NM2 are connected to the differential output terminal OUTN, and the source terminal of the NMOS transistor NM1, the drain terminal of the NMOS transistor NM2 and the gate terminal of the NMOS transistor NM2 are connected to the differential output terminal OUTP.

The embodiment of the utility model provides an in, constitute bootstrap switch circuit through NMOS pipe NM1, NMOS pipe NM2, when differential output OUTN and differential output OUTP within a definite time differential are greater than 0.7V, NMOS pipe NM1 or NMOS pipe NM2 switch on to make bootstrap switch circuit automatic switch-on, make operational amplifier's the rapid grow of slew rate, realize that the slew rate promotes, thereby make high pressure operational amplifier's slew rate remain stable.

Claims (6)

1. A low-noise fully-differential high-voltage operational amplifier comprises an input stage circuit, an output stage circuit, an upper cascode circuit and a lower cascode circuit, wherein the upper cascode circuit is in adaptive connection with the output stage circuit; the method is characterized in that: the voltage slew rate maintaining circuit is adaptively connected with the differential output end OUTN and the differential output end OUTP of the output stage circuit, and the bias power supply circuit can provide power supplies required by the input stage circuit, the output stage circuit, the upper cascode circuit and the lower cascode circuit; when the current flowing through the upper cascode circuit is reduced through the bias power supply circuit, the slew rate of the voltage output by the differential output terminal OUTN and the differential output terminal OUTP of the output stage circuit can be improved by using the slew rate retaining circuit, so that the slew rate of the high-voltage operational amplifier is kept stable.

2. The low noise fully differential high voltage operational amplifier of claim 1, wherein: the input stage circuit comprises a PMOS tube PM20 and a PMOS tube PM21, the gate end of the PMOS tube PM20 is connected with the differential input signal INP, and the gate end of the PMOS tube PM21 is connected with the differential input signal INN; the source end of the PMOS pipe PM20 and the source end of the PMOS pipe PM21 are connected with the drain end of a PMOS pipe PM5 in the bias power supply circuit;

the gate terminal of the PMOS tube PM5 is connected with the gate terminal of a PMOS tube PM4, the gate terminal of a PMOS tube PM1, the drain terminal of a PMOS tube PM1, the drain terminal of an NMOS tube NM19 and the gate terminal of a PMOS tube PM17 in the bias power supply circuit;

the source terminal of a PMOS pipe PM1, the source terminal of a PMOS pipe PM2, the source terminal of a PMOS pipe PM3, the source terminal of a PMOS pipe PM16 in the upper cascode circuit, the source terminal of a PMOS pipe PM18 and the source terminal of a PMOS pipe PM19 are all connected with voltage VDD, and the gate terminal of a PMOS pipe PM2 is connected with the gate terminal of a PMOS pipe PM3, the drain terminal of a PMOS pipe PM4 and the drain terminal of an NMOS pipe NM 20; the drain end of the PMOS pipe PM3 is connected with the source end of the PMOS pipe PM5, the drain end of the PMOS pipe PM2 is connected with the source end of the PMOS pipe PM4, the gate end of the PMOS pipe PM19 is connected with the gate end of the PMOS pipe PM18 and the gate end of the PMOS pipe PM16, and the drain end of the PMOS pipe PM17 and the drain end of the NMOS pipe NM10 are connected;

the gate terminal of the NMOS tube NM19, the gate terminal of the NMOS tube NM20, the gate terminal of the NMOS tube NM18, the gate terminal of the NMOS tube NM17 and the drain terminal of the NMOS tube NM17 are all connected with one output terminal of the bias current source (1), and the gate terminal of the NMOS tube NM10, the gate terminal of the NMOS tube NM14, the gate terminal of the NMOS tube NM15, the gate terminal of the NMOS tube NM16 and the drain terminal of the NMOS tube NM18 are all connected with the other output terminal of the bias current source (1); the source terminal of the NMOS tube NM18 is connected with the drain terminal of the NMOS tube NM16, the source terminal of the NMOS tube NM19 is connected with the drain terminal of the NMOS tube NM15, the source terminal of the NMOS tube NM20 is connected with the drain terminal of the NMOS tube NM14, the drain terminal of the PMOS tube PM20 is connected with the drain terminal of the NMOS tube NM13 and the drain terminal of the NMOS tube NM13, the drain terminal of the PMOS tube PM21 is connected with the drain terminal of the NMOS tube NM12 and the gate terminal of the NMOS tube NM12, the source terminals of the NMOS tube NM10, NM12, NMOS tube NM13, NM14, NM15, NM16 and NM17 are all grounded, the drain terminals of the PMOS tube PM20, PMOS tube PM21 are also connected with the output stage circuit, and the drain terminals of the PMOS tube PM18 and PM19 are adapted to the output stage circuit.

3. The low noise fully differential high voltage operational amplifier of claim 2, wherein: the offset voltage storage circuit is used for storing offset voltage of the input stage circuit and comprises a PMOS tube PM22 and a PMOS tube PM23, the grid end of the PMOS tube PM22 is connected with one end of a capacitor C2, the grid end of the PMOS tube PM23 is connected with one end of a capacitor C1, the drain end of the PMOS tube PM22 is connected with the drain end of the PMOS tube PM20, and the drain end of the PMOS tube PM23 is connected with the drain end of a PMOS tube PM 21; the other end of the capacitor C1 and the other end of the capacitor C2 are both grounded;

the source terminal of the PMOS tube PM22 and the source terminal of the PMOS tube PM23 are connected with the drain terminal of the PMOS tube PM7, the gate terminal of the PMOS tube PM7 is connected with the gate terminal of the PMOS tube PM5, the source terminal of the PMOS tube PM7 is connected with the drain terminal of the PMOS tube PM6, the gate terminal of the PMOS tube PM6 is connected with the gate terminal of the PMOS tube PM3, and the source terminal of the PMOS tube PM6 is connected with the voltage VDD.

4. The low noise fully differential high voltage operational amplifier of claim 2, wherein: the common-mode voltage generating circuit can provide common-mode voltage required by the output-stage circuit, and comprises a PMOS tube PM24, a PMOS tube PM25, an NMOS tube NM8 and an NMOS tube NM 9;

the gate terminal of the NMOS tube NM9 and the gate terminal of the NMOS tube NM8 are connected with the gate terminal of the NMOS tube NM18, the source terminal of the NMOS tube NM9 is connected with the drain terminal of the NMOS tube NM10, the drain terminal of the PMOS tube PM24 and the drain terminal of the PMOS tube PM25, and the drain terminal of the NMOS tube NM9 is connected with the drain terminal of the PMOS tube PM17, the gate terminal of the PMOS tube PM16, the gate terminal of the PMOS tube PM18 and the gate terminal of the PMOS tube PM 19; the grid end of the PMOS pipe PM24 and the grid end of the PMOS pipe PM25 are connected with the drain end of the PMOS pipe PM9, the drain end of the NMOS pipe NM11 and the grid end of the NMOS pipe NM11, and the source end of the NMOS pipe NM11 is grounded;

the source end of the PMOS pipe PM24 is connected with the drain end of the PMOS pipe PM11 and an output stage circuit, the source end of the PMOS pipe PM25 is connected with the drain end of the PMOS pipe PM13 and an output stage circuit, the drain end of the NMOS pipe NM8 is connected with the drain end of the PMOS pipe PM15, the gate end of an NMOS pipe NM7 and the gate end of an NMOS pipe NM6 in the lower cascode circuit, and the gate end of the NMOS pipe NM5 is connected; the source terminal of the NMOS tube NM5, the source terminal of the NMOS tube NM6 and the source terminal of the NMOS tube NM7 are all grounded, the drain terminal of the NMOS tube NM7 is connected with the source terminal of the NMOS tube NM8 and the output stage circuit, and the drain terminal of the NMOS tube NM5 and the drain terminal of the NMOS tube NM6 are connected with the output stage circuit;

the gate terminal of the PMOS transistor PM9 is connected with the gate terminal of the PMOS transistor PM5, the gate terminal of the PMOS transistor PM11, the gate terminal of the PMOS transistor PM13 and the gate terminal of the PMOS transistor PM15, the source terminal of the PMOS transistor PM9 is connected with the drain terminal of the PMOS transistor PM8, the source terminal of the PMOS transistor PM11 is connected with the drain terminal of the PMOS transistor PM10, the source terminal of the PMOS transistor PM13 is connected with the drain terminal of the PMOS transistor PM12, the source terminal of the PMOS transistor PM15 is connected with the drain terminal of the PMOS transistor PM14, the source terminal of the PMOS transistor PM8, the source terminal of the PMOS transistor PM10, the source terminal of the PMOS transistor PM12 and the source terminal of the PMOS transistor PM14 are all connected with the voltage VDD, and the gate terminal of the PMOS transistor PM8 is connected with the gate terminal of the PMOS transistor PM3, the gate terminal of the PMOS transistor PM 573.

5. The low noise fully differential high voltage operational amplifier according to claim 4, wherein: the output stage circuit comprises a first gain amplifier (2) and a second gain amplifier (3), wherein the input end of the first gain amplifier (2) is respectively connected with the drain end of a PMOS pipe PM19, the drain end of a PMOS pipe PM18, the drain end of a PMOS pipe PM16 and the source end of a PMOS pipe PM17, one output end of the first gain amplifier (2) is connected with the gate end of the PMOS pipe PM28, the other output end of the first gain amplifier (2) is connected with the gate end of the PMOS pipe PM29, the drain end of the PMOS pipe PM28 is connected with the gate end of a PMOS pipe PM26 and the drain end of an NMOS pipe NM3, the drain end of the PMOS pipe PM29 is connected with the drain ends of a PMOS pipe PM27 and an NMOS pipe NM4, the source end of a PMOS pipe PM26 is connected with the source end of a PMOS pipe PM25, the source end of the PMOS pipe PM27 is connected with the drain end of a PMOS pipe PM24, and the drain ends of the PMOS pipe PM26 and;

the grid end of the NMOS tube NM3 is connected with one output end of the second gain amplifier (3), the grid end of the NMOS tube NM4 is connected with the other output end of the second gain amplifier (3), the source end of the NMOS tube NM3 is connected with the drain end of the NMOS tube NM6, one input end of the second gain amplifier (3) and the drain end of the PMOS tube PM20, the drain end of the NMOS tube NM4 is connected with the drain end of the NMOS tube NM5, the other input end of the second gain amplifier (3) and the drain end of the PMOS tube PM21, and the third input end of the second gain amplifier (3) is connected with the source end of the NMOS tube NM8 and the drain end of the NMOS tube NM 7;

the drain end of the PMOS pipe PM28, the gate end of the PMOS pipe PM26 and the drain end of the NMOS pipe NM3 are mutually connected to form a differential output end OUTN, and the drain end of the PMOS pipe PM29, the gate end of the PMOS pipe PM27 and the drain end of the NMOS pipe NM4 are mutually connected to form a differential output end OUTP; the slew rate maintaining circuit comprises a bootstrap switch circuit, and the bootstrap switch circuit is in adaptive connection with the differential output end OUTN and the differential output end OUTP.

6. The low noise fully differential high voltage operational amplifier according to claim 5, wherein: the bootstrap switch circuit comprises an NMOS tube NM1 and an NMOS tube NM2, the grid end of the NMOS tube NM1, the drain end of the NMOS tube NM1 and the source end of the NMOS tube NM2 are connected with a differential output end OUTN, and the source end of the NMOS tube NM1, the drain end of the NMOS tube NM2 and the grid end of the NMOS tube NM2 are connected with a differential output end OUTP.

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