CN103746661B - Dual-mode low-noise amplifier - Google Patents
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- CN103746661B CN103746661B CN201410035310.7A CN201410035310A CN103746661B CN 103746661 B CN103746661 B CN 103746661B CN 201410035310 A CN201410035310 A CN 201410035310A CN 103746661 B CN103746661 B CN 103746661B
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Abstract
The invention discloses a dual-mode low-noise amplifier and belongs to the field of radio frequency circuit design. The dual-mode low-noise amplifier comprises a low-noise amplifier LAN core circuit and a dual-mode switch-controllable replicating biasing circuit; the dual-mode switch-controllable replicating biasing circuit provides the core circuit with all biases required; a switch S of the dual-mode switch-controllable replicating biasing circuit is controlled to drive the LNA core circuit to operate in two different modes, namely a high gain mode and a high linearity mode; when the fixed end of the switch S is connected with the moving end a of the switch S, the LNA operates in the high linearity mode; when the fixed end c of the switch S is connected with a contact moving end b of the switch S, the LNA operates in the high gain mode. The dual-mode switch-controllable replicating biasing circuit fully replicates an amplifier circuit and is in a current mirror structure, so that current of the whole circuit is controlled through a reference current source and influences of PVT changes are suppressed.
Description
Technical field
The invention belongs to field of radio frequency circuit design is and in particular to a kind of dual-mode low-noise amplifier.
Background technology
In recent years, wireless communication technology obtains swift and violent development, plays more and more important role in social life.
The development of radio communication is put forward higher requirement to transceiver front ends circuit.
The rf analog front-end circuit of receiver haves such problems as that components and parts number is many, high cost, power consumption are big, volume is big,
But for transceiver, either transmitting or receiving data, very big carrier signal can persistently be launched by antenna, and carrier signal is led to
Cross circulator or directional coupler leaks into receiver front end, energy can reach more than 0dbm, is far longer than receipt signal
Energy.Again due to receiving in most of communication system with sending signal as same carrier frequency it is impossible to hold logical in front of the receiver
Cross the carrier signal that radio frequency band filter will leak out to filter so that receiver front end produces desensitization and obstruction, have a strong impact on
The dynamic range of receives link.How in the case of ensureing certain sensitivity, the shadow that suppressing carrier leakage causes to receiver
Ring, be the key improving receiver performance.
And solve it is critical only that between the linearity and gain and the noiseproof feature of receiver front end circuit of this difficult point
Compromise, a kind of common trade-off strategies are operated in two patterns it may be assumed that reading model and listening mode for RF front-end circuit, read
Reading mode ensures that front end linearity degree, listening mode ensure noise coefficient.For tackling this strategy, front-end circuit must operate at two
Pattern.Additionally, RF front-end circuit changes ten to process-voltage-temperature (pvt, process-voltage-temperature)
Divide sensitivity, the change of pvt have impact on circuit performance often largely.
At present, in communication system carrier leak problem in RF identification (radiofrequencyidentification) skill
Especially prominent in art, and study discovery, it is more suitable for future, particularly in commercial offers chain, application is ultra-high frequency band system,
Therefore, the simulation frequency of the present invention is set as ultra-high frequency band.
Content of the invention
Technical problem: the present invention solves the problems, such as, for RF front-end circuit, the strategy that carrier leak is proposed, in order to provide
It is proposed that a kind of dual-mode low-noise amplifier, this circuit can suppress pvt to change effectively simultaneously for reading model and mode of operation
Impact to circuit performance.
Technical scheme: described amplifier comprises fully differential amplifying circuit and double mode biasing circuit；Described fully differential amplifies
The load biasing of circuit, the biasing of mutual conductance pipe and tail current source biasing are provided by double mode biasing circuit.This biasing circuit is adopted
Use replication form biasing circuit, biasing circuit replicates differential amplifier circuit.This biasing circuit provides two kinds for low-noise amplifier
Mode of operation: high gain mode and high linearity mode.When switch s is closed into a, the mode of operation of this low-noise amplifier is
High gain mode, during high gain mode, this biasing circuit is supplied to the low bias voltage of amplifying circuit mutual conductance pipe it is ensured that mutual conductance pipe
It is operated in saturation region, now amplifying circuit has higher gain and preferable noiseproof feature；When switch s is closed into b, should
The mode of operation of low-noise amplifier is high linearity mode, and during high linearity, this biasing circuit is supplied to amplifying circuit mutual conductance pipe
So as to be operated in linear zone, now amplifying circuit has the higher linearity to high bias voltage.Additionally, this biasing circuit is adopted
Replication form bias circuit construction is so as to electric current is as the electric current holding of amplifying circuit, and is controlled by a baseband current,
Thus inhibiting the impact to circuit for the pvt change.
The present invention is to solve above-mentioned technical problem, adopts the following technical scheme that
The dual-mode low-noise amplifier of the present invention comprises low-noise amplifier lna core circuit and two mode switch is controlled
Replication form biasing circuit, and to switch controlled replication form biasing circuit be that core circuit provides required all biasings；Pass through
The switch s of the controlled replication form biasing circuit of controlling switch making lna core circuit work in different two states, i.e. high increasing
Beneficial pattern and high linearity mode；Wherein, when switching the moved end a of not moved end c connecting valve s of s, lna works in High Linear
Degree pattern；When switching the contact moved end b of not moved end c connecting valve s of s, lna works in high gain mode.
In described lna core circuit, a nmos pipe drain electrode is connected with the 3rd nmos pipe source electrode；2nd nmos pipe drain electrode with
4th nmos pipe source electrode is connected；3rd nmos pipe drain electrode is connected with a pmos pipe drain electrode；4th nmos pipe drain electrode and second
The drain electrode of pmos pipe is connected；The grid of the grid of the 3rd nmos pipe and nm4 is connected with one end of first resistor, second resistance respectively；
First resistor, another termination supply voltage of second resistance；The source electrode of the first pmos pipe, the 2nd pmos pipe source electrode respectively with electricity
Source voltage is connected；First pmos pipe, the grid of the 2nd pmos pipe connect the 3rd bias voltage respectively；First nmos pipe source electrode and grid
Between connect the first electric capacity, a nmos pipe source electrode is connected with first inductance one end；2nd nmos pipe source electrode be connected between grid
Two electric capacity；2nd nmos pipe source electrode is connected with second inductance one end；The first inductance other end, the second inductance other end respectively with work
Drain electrode for the 5th nmos pipe of full-differential circuits tail current source is connected；5th nmos pipe source ground, the 5th nmos tube grid
Connect one end of the 5th resistance, the 5th resistance another termination the second bias voltage；First nmos tube grid and the 3rd inductance one end phase
Even, the 3rd inductance is another is terminated input signal and is connected with 3rd resistor one end, 3rd resistor another termination the first bias voltage；
2nd nmos tube grid is connected with the 4th inductance one end, another termination input signal of the 4th inductance (l4) and with the 4th resistance one end
It is connected, the 4th resistance another termination the first bias voltage；3rd electric capacity one end is drained and the 4th nmos with the 2nd nmos pipe respectively
Pipe source electrode is connected, and the 3rd electric capacity other end is connected with the grid of the 3rd nmos pipe；One end of 4th electric capacity respectively with a nmos
The source electrode of the drain electrode of pipe and the 3rd nmos pipe is connected, and the 4th electric capacity other end is connected with the grid of the 4th nmos pipe；Common-mode feedback
Circuit anode is connected with the positive output end of the differential output signal of full-differential circuits, the negative output terminal of negative pole and differential output signal
Connect, the output of common mode feedback circuit is connected with the grid of the 5th nmos pipe.
In the controlled replication form biasing circuit of described two mode switch, the 7th nmos pipe drain electrode manages (nm9) with the 9th nmos
Source electrode is connected；8th nmos pipe drain electrode is connected with the tenth nmos pipe source electrode；9th nmos pipe (nm9) drain electrode and the 3rd pmos pipe
Drain electrode is connected；Tenth nmos pipe drain electrode is connected with the drain electrode of the 4th pmos pipe；9th nmos tube grid, the tenth nmos tube grid divide
It is not connected with one end of the 6th resistance, the 7th resistance；6th resistance, the other end of the 7th resistance and the 3rd pmos pipe, the 4th
The source electrode of pmos pipe (pm4) is connected with power supply respectively；3rd pmos tube grid source the 4th pmos tube grid is connected and is simultaneously connected with the
Three bias voltages；The grid of the 3rd pmos pipe is connected with drain electrode；7th nmos tube grid is connected simultaneously with the 8th nmos tube grid
Connect the first biasing；7th nmos pipe source electrode is connected with the 11st nmos pipe drain electrode；8th nmos pipe source electrode and the 12nd nmos pipe
Drain electrode is connected；11st nmos tube grid, the 12nd nmos tube grid are connected with the 6th nmos tube grid and connect the second biasing simultaneously
Voltage；11st nmos pipe source electrode, the 12nd nmos pipe source electrode, the 6th nmos pipe source electrode are all grounded；6th nmos tube grid with
Drain electrode is connected to drain simultaneously and is connected with reference current source；Another termination power of reference current source；The moved end a of single-pole double-throw switch (SPDT)
End is connected with the 8th nmos pipe drain electrode, moved end b end is connected with the 12nd nmos tube grid, not moved end c end and the 8th nmos pipe grid
Extremely connected.
Actual gain: the present invention proposes a kind of dual-mode low-noise amplifier.Described amplifier is by double mode biasing
Two kinds of mode of operations of circuit, provide two kinds of bias voltages so that amplifying circuit works in two work for differential amplifier circuit
Pattern: high gain mode and high linearity mode, both of which provides two kinds of mode of operations for receiver front end circuit, thus
Solve the problems, such as carrier leak.Additionally, this biasing circuit replicates differential amplifier circuit completely, and adopt reference current source control
System, restrained effectively the impact to circuit performance for the pvt change.
Brief description
Fig. 1 is a kind of dual-mode low-noise amplifier circuit structure that the present invention provides；
Fig. 2 (a) is that process corner is that tt, voltage are respectively in the high-gain mode for the dual-mode low-noise amplifier of the present invention
When 1.6v, 1.8v, 2.0v, s21 varies with temperature curve chart；
Fig. 2 (b) is that process corner is that tt, voltage are respectively in the high-gain mode for the dual-mode low-noise amplifier of the present invention
When 1.6v, 1.8v, 2.0v, s11 varies with temperature curve chart；
Fig. 2 (c) is that process corner is that tt, voltage are respectively in the high-gain mode for the dual-mode low-noise amplifier of the present invention
When 1.6v, 1.8v, 2.0v, nf varies with temperature curve chart；
Fig. 2 (d) is that process corner is that tt, voltage are respectively in the high-gain mode for the dual-mode low-noise amplifier of the present invention
When 1.6v, 1.8v, 2.0v, p1db varies with temperature curve chart；
Fig. 3 (a) be the present invention dual-mode low-noise amplifier under high linearity mode process corner be tt, voltage respectively
Vary with temperature curve chart for s21 when 1.6v, 1.8v, 2.0v；
Fig. 3 (b) be the present invention dual-mode low-noise amplifier under high linearity mode process corner be tt, voltage respectively
Vary with temperature curve chart for s11 when 1.6v, 1.8v, 2.0v；
Fig. 3 (c) be the present invention dual-mode low-noise amplifier under high linearity mode process corner be tt, voltage respectively
Vary with temperature curve chart for nf when 1.6v, 1.8v, 2.0v；
Fig. 3 (d) be the present invention dual-mode low-noise amplifier under high linearity mode process corner be tt, voltage respectively
Vary with temperature curve chart for p1db when 1.6v, 1.8v, 2.0v.
Specific embodiment
Below in conjunction with the accompanying drawings, it is further elaborated with a kind of dual-mode low-noise amplifier of the present invention.
With reference to Fig. 1, a kind of dual-mode low-noise amplifier provided by the present invention by fully differential low-noise amplifier with double
The combination of model duplication type biasing circuit constitutes this amplifier circuit positive and negative two-way input, output, and this two-way circuit is full symmetric
Design.rfopPositive output end for difference amplifier；rfonNegative output terminal for difference amplifier.
In described lna core circuit, a nmos pipe nm1 drain electrode is connected with the 3rd nmos pipe nm3 source electrode；2nd nmos pipe
Nm2 drain electrode is connected with the 4th nmos pipe nm4 source electrode；3rd nmos pipe nm3 drain electrode is connected with a pmos pipe pm1 drain electrode；4th
Nmos pipe nm4 drain electrode is connected with the 2nd pmos pipe pm2 drain electrode；The grid of the grid of the 3rd nmos pipe nm3 and nm4 is respectively with first
Resistance r1, one end of second resistance r2 are connected；First resistor r1, another termination supply voltage vdd of second resistance r2；First
The source electrode of pmos pipe pm1, the source electrode of the 2nd pmos pipe pm2 are connected with supply voltage vdd respectively；First pmos pipe pm1, second
The grid of pmos pipe pm2 meets the 3rd bias voltage vbias3 respectively；First nmos pipe nm1 source electrode be connected the first electric capacity between grid
C1, a nmos pipe nm1 source electrode is connected with first inductance l1 one end；2nd nmos pipe nm2 source electrode be connected between grid second electricity
Hold c2；2nd nmos pipe nm2 source electrode is connected with second inductance l2 one end；The first inductance l1 other end, the second inductance l2 other end
It is connected with the drain electrode of the 5th nmos pipe nm5 as full-differential circuits tail current source respectively；5th nmos pipe nm5 source ground,
5th nmos pipe nm5 grid connects one end of the 5th resistance r5, the 5th resistance r5 another termination the second bias voltage vbias2；First
Nmos pipe nm1 grid is connected with the 3rd inductance l3 one end, the 3rd inductance l3 another termination input signal and with 3rd resistor r3 mono-
End is connected, 3rd resistor r3 another termination the first bias voltage vbias1；2nd nmos pipe nm2 grid and the 4th inductance l4 one end
It is connected, the 4th inductance l4 another termination input signal is simultaneously connected with the 4th resistance r4 one end, another termination first of the 4th resistance r4
Bias voltage vbias1；3rd electric capacity c3 one end is connected with the 2nd nmos pipe nm2 drain electrode and the 4th nmos pipe nm4 source electrode respectively,
The 3rd electric capacity c3 other end is connected with the grid of the 3rd nmos pipe nm3；One end of 4th electric capacity c4 respectively with a nmos pipe nm1
Drain electrode and the 3rd nmos pipe nm3 source electrode be connected, the 4th electric capacity c4 other end is connected with the grid of the 4th nmos pipe nm4；Altogether
Cmfb circuit cmfb positive pole is connected with the positive output end of the differential output signal of full-differential circuits, negative pole and differential output signal
Negative output terminal connect, the output of common mode feedback circuit cmfb is connected with the grid of the 5th nmos pipe nm5.
With reference in the controlled replication form biasing circuit of two mode switch described in Fig. 1, the 7th nmos pipe nm7 drains and the 9th
Nmos pipe nm9 source electrode is connected；8th nmos pipe nm8 drain electrode is connected with the tenth nmos pipe nm10 source electrode；9th nmos pipe nm9 drain electrode
Drain electrode with the 3rd pmos pipe pm3 is connected；Tenth nmos pipe nm10 drain electrode is connected with the drain electrode of the 4th pmos pipe pm4；9th
Nmos pipe nm9 grid, the tenth nmos pipe nm10 grid are connected with one end of the 6th resistance r6, the 7th resistance r7 respectively；6th electricity
Resistance r6, the other end of the 7th resistance r7 and the 3rd pmos pipe pm3, the 4th pmos pipe pm4 source electrode respectively with power supply vdd phase
Even；3rd pmos pipe pm3 gate source the 4th pmos pipe pm4 grid is connected and is simultaneously connected with the 3rd bias voltage vbias3；3rd
The grid of pmos pipe pm3 is connected with drain electrode；7th nmos pipe nm7 grid is connected with the 8th nmos pipe nm8 grid and connects first simultaneously
Biasing vbias1；7th nmos pipe nm7 source electrode is connected with the 11st nmos pipe nm11 drain electrode；8th nmos pipe nm8 source electrode and
12 nmos pipe nm12 drain electrodes are connected；11st nmos pipe nm11 grid, the 12nd nmos pipe nm12 grid and the 6th nmos pipe
Nm6 grid is connected and meets the second bias voltage vbias2 simultaneously；11st nmos pipe nm11 source electrode, the 12nd nmos pipe nm12 source
Pole, the 6th nmos pipe nm6 source electrode are all grounded；6th nmos pipe nm6 grid is connected with drain electrode and drains and reference current source simultaneously
Iref is connected；Another termination power of reference current source iref；The moved end a end of single-pole double-throw switch (SPDT) s and the 8th nmos pipe nm8 leakage
Extremely be connected, moved end b end be connected with the 12nd nmos pipe nm12 grid, not moved end c end be connected with the 8th nmos pipe nm8 grid.
Mode bias circuit, the grid of its pm4 meets the vbise3 of differential amplifier circuit, and the c termination of single-pole double-throw switch (SPDT) s is poor
Divide the vbise1, the vbise2 of the b terminating differential amplifying circuit of single-pole double-throw switch (SPDT) s of amplifying circuit.
With reference to Fig. 1, the 6th nmos pipe is managed with the 11st nmos respectively, the 12nd nmos pipe, the 3rd pmos pipe constitute electric current
Mirror, the left side string branch current of such biasing circuit is controlled by reference current source iref, and the branch road on the right then replicates completely
The structure of differential amplifier circuit, makes the two-way electric current completely the same by designing circuit devcie size, figure it is seen that
The branch road on the right is just the same with the branch current on the left side, is so achieved that reference current source controls whole low noise amplification
Electric current in circuit is so that the operating current in circuit is no longer changed by pvt is affected.
Fig. 2 show the dual-mode low-noise amplifier of the present invention in the high-gain mode process corner be tt, voltage respectively
Vary with temperature curve chart for s21 (a), s11 (b), nf (c), p1db (d) when 1.6v, 1.8v, 2.0v.It can be seen that with temperature
Between -40 DEG C to 85 DEG C change when, low-noise amplifier provided by the present invention gain in the high-gain mode 1.6v,
10db-12db is maintained under the different supply voltage of 1.8v, 2v；S11 now is respectively less than -10db, and circuit input coupling is good；
Noise coefficient maintains between 2～3db, and noiseproof feature is preferable；1db compression point is less than -10, and is more than -15, and the linearity is general.
Illustrate that the present invention gain and noiseproof feature in high gain mode are good, and inhibit the impact to circuit performance for the pvt change.
Fig. 3 show that the dual-mode low-noise amplifier of present invention process corner under high linearity mode is tt, voltage divides
Not Wei 1.6v, 1.8v, 2.0v when s21 (a), s11 (b), nf (c), p1db (d) vary with temperature curve chart.It can be seen that with temperature
When degree changes between -40 DEG C to 85 DEG C, low-noise amplifier provided by the present invention gain in the high-gain mode exists
4db-6db is maintained under the different supply voltage of 1.6v, 1.8v, 2v；S11 now is respectively less than -10db, and circuit input coupling is good
Good；Noise coefficient maintains between 2.5～4.5db, and noiseproof feature is general；1db compression point maintains between -3dbm～1dbm,
The linearity is preferable.Illustrate that present invention linearity in high linearity mode is higher, and inhibit pvt to change to circuit performance
Impact.
In sum, dual-mode low-noise amplifier proposed by the present invention provides high-gain and high linearity mode, and
Preferable performance is all had to restrained effectively the impact to circuit for the pvt change in both modes, this is receiver front end circuit
Provide two kinds of mode of operations, solve the problems, such as carrier leak, have wide in hyperfrequency rfid receiver front end circuit
Application prospect.For those skilled in the art, association's others can be easy to according to above implementation of class excellent
Point and deformation.Therefore, the invention is not limited in above-mentioned instantiation, it enters as just example to a kind of form of the present invention
Detailed, the exemplary explanation of row.In the range of without departing substantially from present inventive concept, those of ordinary skill in the art are according to above-mentioned concrete
Example, by the technical scheme obtained by various equivalents, should be included in scope of the presently claimed invention and its waits homotype
Within enclosing.
Claims (1)
1. a kind of dual-mode low-noise amplifier is it is characterised in that this amplifier comprises low-noise amplifier core circuit and double
The controlled replication form biasing circuit of mode switch, and the controlled replication form biasing circuit of two mode switch is low-noise amplifier core
Electrocardio road provides required all biasings；By controlling the single-pole double throw hilted broadsword of the controlled replication form biasing circuit of two mode switch
Commutator s making low-noise amplifier core circuit work in different two states, i.e. high gain mode and high linearity
Pattern；Wherein, when the not moved end c of single-pole double throw single-pole double-throw switch (SPDT) s connects the moved end a of single-pole double throw single-pole double-throw switch (SPDT) s,
Low-noise amplifier core circuit works in high linearity mode；When the not moved end c of single-pole double throw single-pole double-throw switch (SPDT) s connects list
During the contact moved end b of dpdt double-pole double-throw (DPDT) single-pole double-throw switch (SPDT) s, low-noise amplifier core circuit works in high gain mode；High-gain
During pattern, this biasing circuit is supplied to the low bias voltage of amplifying circuit mutual conductance pipe it is ensured that mutual conductance pipe is operated in saturation region；High line
Property when spending this biasing circuit be supplied to the high bias voltage of amplifying circuit mutual conductance pipe so as to be operated in linear zone, now amplify electricity
Road has the higher linearity；
Wherein:
In described low-noise amplifier core circuit, a nmos pipe nm1 drain electrode is connected with the 3rd nmos pipe nm3 source electrode；Second
Nmos pipe nm2 drain electrode is connected with the 4th nmos pipe nm4 source electrode；3rd nmos pipe nm3 drain electrode and pmos pipe pm1 drain electrode phase
Even；4th nmos pipe nm4 drain electrode is connected with the 2nd pmos pipe pm2 drain electrode；The grid of the grid of the 3rd nmos pipe nm3 and nm4 divides
It is not connected with one end of first resistor r1, second resistance r2；First resistor r1, another termination supply voltage of second resistance r2
vdd；The source electrode of the first pmos pipe pm1, the source electrode of the 2nd pmos pipe pm2 are connected with supply voltage vdd respectively；First pmos pipe
Pm1, the grid of the 2nd pmos pipe pm2 meet the 3rd bias voltage vbias3 respectively；First nmos pipe nm1 source electrode is connected between grid
First electric capacity c1, a nmos pipe nm1 source electrode is connected with first inductance l1 one end；Connect between the 2nd nmos pipe nm2 source electrode and grid
Meet the second electric capacity c2；2nd nmos pipe nm2 source electrode is connected with second inductance l2 one end；The first inductance l1 other end, the second inductance
The l2 other end is connected with the drain electrode of the 5th nmos pipe nm5 respectively；5th nmos pipe nm5 source ground, the 5th nmos pipe nm5 grid
Connect one end of the 5th resistance r5, the 5th resistance r5 another termination the second bias voltage vbias2；First nmos pipe nm1 grid and
Three inductance l3 one end are connected, and the 3rd inductance l3 another termination input signal is simultaneously connected with 3rd resistor r3 one end, 3rd resistor r3
Another termination the first bias voltage vbias1；2nd nmos pipe nm2 grid is connected with the 4th inductance l4 one end, and the 4th inductance l4 is another
One termination input signal is simultaneously connected with the 4th resistance r4 one end, the 4th resistance r4 another termination the first bias voltage vbias1；The
Three electric capacity c3 one end respectively with the 2nd nmos pipe nm2 drain electrode and the 4th nmos pipe nm4 source electrode be connected, the 3rd electric capacity c3 other end and
The grid of the 3rd nmos pipe nm3 is connected；One end of 4th electric capacity c4 is managed with the drain electrode of a nmos pipe nm1 and the 3rd nmos respectively
The source electrode of nm3 is connected, and the 4th electric capacity c4 other end is connected with the grid of the 4th nmos pipe nm4；Common mode feedback circuit cmfb positive pole
It is connected with the drain terminal of the 3rd nmos pipe nm3, common mode feedback circuit cmfb negative pole is connected with the drain terminal of the 4th nmos pipe nm4, common mode
The output of feedback circuit cmfb is connected with the grid of the 5th nmos pipe nm5；
In the controlled replication form biasing circuit of described two mode switch, the 7th nmos pipe nm7 drains and the 9th nmos pipe nm9 source electrode
It is connected；8th nmos pipe nm8 drain electrode is connected with the tenth nmos pipe nm10 source electrode；9th nmos pipe nm9 drain electrode and the 3rd pmos pipe
The drain electrode of pm3 is connected；Tenth nmos pipe nm10 drain electrode is connected with the drain electrode of the 4th pmos pipe pm4；9th nmos pipe nm9 grid,
Tenth nmos pipe nm10 grid is connected with one end of the 6th resistance r6, the 7th resistance r7 respectively；6th resistance r6, the 7th resistance r7
The other end and the 3rd pmos pipe pm3, the source electrode of the 4th pmos pipe pm4 be connected with power supply vdd respectively；3rd pmos pipe pm3
Gate source the 4th pmos pipe pm4 grid is connected derives the 3rd bias voltage vbias3 simultaneously；The grid of the 3rd pmos pipe pm3 and leakage
Extremely connected；7th nmos pipe nm7 grid is connected with the 8th nmos pipe nm8 grid derives the first biasing vbias1 simultaneously；7th
Nmos pipe nm7 source electrode is connected with the 11st nmos pipe nm11 drain electrode；8th nmos pipe nm8 source electrode and the 12nd nmos pipe nm12 leakage
Extremely connected；11st nmos pipe nm11 grid, the 12nd nmos pipe nm12 grid are connected with the 6th nmos pipe nm6 grid and lead simultaneously
Go out the second bias voltage vbias2；11st nmos pipe nm11 source electrode, the 12nd nmos pipe nm12 source electrode, the 6th nmos pipe nm6
Source electrode is all grounded；6th nmos pipe nm6 grid is connected to drain with drain electrode simultaneously and is connected with reference current source iref；Reference current source
Another termination power of iref；The moved end a end of single-pole double-throw switch (SPDT) s is connected with the 8th nmos pipe nm8 drain electrode, moved end b end and the
12 nmos pipe nm12 grids be connected, not moved end c end be connected with the 8th nmos pipe nm8 grid.
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| CN109088604B (en) * | 2018-08-06 | 2022-02-15 | 上海华虹宏力半导体制造有限公司 | Variable gain low noise amplifier |
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| JP2003347870A (en) * | 2002-05-22 | 2003-12-05 | Mitsubishi Electric Corp | Power amplifier |
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|---|---|---|---|---|
| CN101098127A (en) * | 2006-06-19 | 2008-01-02 | 株式会社瑞萨科技 | RF power amplifier |
| CN102096079A (en) * | 2009-12-12 | 2011-06-15 | 杭州中科微电子有限公司 | Method for constructing radio frequency front end of multi-mode multi-band satellite navigation receiver and module thereof |
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| CN103746661A (en) | 2014-04-23 |
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