CN103746661A - Dual-mode low-noise amplifier - Google Patents
Dual-mode low-noise amplifier Download PDFInfo
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- CN103746661A CN103746661A CN201410035310.7A CN201410035310A CN103746661A CN 103746661 A CN103746661 A CN 103746661A CN 201410035310 A CN201410035310 A CN 201410035310A CN 103746661 A CN103746661 A CN 103746661A
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Abstract
The invention discloses a dual-mode low-noise amplifier and belongs to the field of radio frequency circuit design. The dual-mode low-noise amplifier comprises a low-noise amplifier LAN core circuit and a dual-mode switch-controllable replicating biasing circuit; the dual-mode switch-controllable replicating biasing circuit provides the core circuit with all biases required; a switch S of the dual-mode switch-controllable replicating biasing circuit is controlled to drive the LNA core circuit to operate in two different modes, namely a high gain mode and a high linearity mode; when the fixed end of the switch S is connected with the moving end a of the switch S, the LNA operates in the high linearity mode; when the fixed end c of the switch S is connected with a contact moving end b of the switch S, the LNA operates in the high gain mode. The dual-mode switch-controllable replicating biasing circuit fully replicates an amplifier circuit and is in a current mirror structure, so that current of the whole circuit is controlled through a reference current source and influences of PVT changes are suppressed.
Description
Technical field
The invention belongs to radio frequency integrated circuit design field, be specifically related to a kind of double mode low noise amplifier.
Background technology
In recent years, wireless communication technology obtains swift and violent development, is playing the part of in social life more and more important role.The development of radio communication is had higher requirement to transceiver front ends circuit.
There is the problems such as components and parts number is many, cost is high, power consumption is large, volume is large in the rf analog front-end circuit of receiver, but for transceiver, no matter be transmitting or reception data, antenna can continue the carrier signal that transmitting is very large, carrier signal is leaked and is entered receiver front end by circulator or directional coupler, more than energy can reach 0dBm, be far longer than the energy that receives signal.Again because reception and transmitted signal in most of communication system are same carrier frequency, cannot receiver front end by radio frequency band filter by leak carrier signal filtering, receiver front end is produced and subtract quick and block, had a strong impact on the dynamic range of receiver.How, in the situation that guaranteeing natural sensitivity, the impact that suppressing carrier leakage causes receiver, is the key that improves receiver performance.
And the key that solves this difficult point is the compromise between the linearity and gain and the noiseproof feature of receiver front end circuit, a kind of common compromise strategy is that radio-frequency (RF) front-end circuit is operated in two patterns, that is: reading model and listen mode, reading model guarantees that the front end linearity, listen mode guarantee noise factor.For tackling this strategy, front-end circuit must operate at two patterns.In addition, radio-frequency (RF) front-end circuit changes very responsive to technique-voltage-temperature (PVT, Process-Voltage-Temperature), and the variation of PVT has usually affected circuit performance significantly.
At present, in communication system, carrier leak problem is particularly outstanding in radio-frequency (RF) identification (RadioFrequencyIdentification) technology, and research is found, be more suitable for future, what particularly in commercial offers chain, apply is ultra-high frequency band system, therefore, stimulation frequency of the present invention is set as ultra-high frequency band.
Summary of the invention
Technical problem: the present invention is directed to radio-frequency (RF) front-end circuit and solve the strategy that carrier leak problem proposes, for reading model and mode of operation are provided, proposed a kind of double mode low noise amplifier, this circuit can effectively suppress PVT and changes the impact on circuit performance simultaneously.
Technical scheme: described amplifier comprises fully differential amplifying circuit and double mode biasing circuit; Load biasing, the biasing of mutual conductance pipe and the tail current source biasing of described fully differential amplifying circuit provide by double mode biasing circuit.This biasing circuit adopts science biasing circuit, and biasing circuit copies differential amplifier circuit.This biasing circuit provides two kinds of mode of operations for low noise amplifier: high gain mode and high linearity pattern.When switch S is closed into a, the mode of operation of this low noise amplifier is high gain mode, during high gain mode, this biasing circuit offers the low bias voltage of amplifying circuit mutual conductance pipe, guarantees that mutual conductance pipe is operated in saturation region, and now amplifying circuit has higher gain and good noiseproof feature; When switch S is closed into b, the mode of operation of this low noise amplifier is high linearity pattern, and during high linearity, this biasing circuit offers the high bias voltage of amplifying circuit mutual conductance pipe, makes it be operated in linear zone, and now amplifying circuit has the higher linearity.In addition, the science bias circuit construction that this biasing circuit adopts, makes its electric current keep the same with the electric current of amplifying circuit, and by a baseband current control, thereby suppressed PVT, changes the impact on circuit.
The present invention, for solving the problems of the technologies described above, adopts following technical scheme:
Double mode low noise amplifier of the present invention comprises low noise amplifier LNA core circuit and the controlled science biasing circuit of double mode switch, and the controlled science biasing circuit of switch provides required all biasings for core circuit; Switch S by the controlled science biasing circuit of control switch makes LNA core circuit work in different two states, i.e. high gain mode and high linearity pattern; Wherein, when the moved end a of the not moved end of switch S c connecting valve S, LNA works in high linearity pattern; When moved end, the contact b of the not moved end of switch S c connecting valve S, LNA works in high gain mode.
In described LNA core circuit, a NMOS pipe drain electrode is connected with the 3rd NMOS pipe source electrode; The 2nd NMOS pipe drain electrode is connected with the 4th NMOS pipe source electrode; The 3rd NMOS pipe drain electrode is connected with a PMOS pipe drain electrode; The 4th NMOS pipe drain electrode is connected with the 2nd PMOS pipe drain electrode; The 3rd grid of NMOS pipe and the grid of NM4 are connected with one end of the first resistance, the second resistance respectively; Another termination supply voltage of the first resistance, the second resistance; The source electrode of the one PMOS pipe, the source electrode of the 2nd PMOS pipe are connected with supply voltage respectively; The grid of the one PMOS pipe, the 2nd PMOS pipe connects respectively the 3rd bias voltage; Between the one NMOS pipe source electrode and grid, be connected the first electric capacity, a NMOS pipe source electrode is connected with first inductance one end; Between the 2nd NMOS pipe source electrode and grid, be connected the second electric capacity; The 2nd NMOS pipe source electrode is connected with second inductance one end; The first inductance other end, the second inductance other end are connected with the drain electrode of the 5th NMOS pipe as fully differential circuit tail current source respectively; The 5th NMOS pipe source ground, the 5th NMOS tube grid connects one end of the 5th resistance, another termination second bias voltage of the 5th resistance; The one NMOS tube grid is connected with the 3rd inductance one end, and another termination input signal of the 3rd inductance is also connected with the 3rd resistance one end, another termination first bias voltage of the 3rd resistance; The 2nd NMOS tube grid is connected with the 4th inductance one end, and the 4th another termination input signal of inductance (L4) is also connected with the 4th resistance one end, another termination first bias voltage of the 4th resistance; The 3rd electric capacity one end is connected with the 2nd NMOS pipe drain electrode and the 4th NMOS pipe source electrode respectively, and the 3rd electric capacity other end is connected with the grid of the 3rd NMOS pipe; One end of the 4th electric capacity is connected with the drain electrode of a NMOS pipe and the source electrode of the 3rd NMOS pipe respectively, and the 4th electric capacity other end is connected with the grid of the 4th NMOS pipe; Common mode feedback circuit positive pole is connected with the positive output end of the differential output signal of fully differential circuit, and negative pole is connected with the negative output terminal of differential output signal, and the output of common mode feedback circuit is connected with the grid of the 5th NMOS pipe.
In the controlled science biasing circuit of described double mode switch, the 7th NMOS pipe drain electrode is managed (NM9) source electrode with the 9th NMOS and is connected; The 8th NMOS pipe drain electrode is connected with the tenth NMOS pipe source electrode; The 9th NMOS pipe (NM9) drain electrode is connected with the drain electrode of the 3rd PMOS pipe; The tenth NMOS pipe drain electrode is connected with the drain electrode of the 4th PMOS pipe; The 9th NMOS tube grid, the tenth NMOS tube grid are connected with one end of the 6th resistance, the 7th resistance respectively; The source electrode of the other end of the 6th resistance, the 7th resistance and the 3rd PMOS pipe, the 4th PMOS pipe (PM4) is connected with power supply respectively; The 3rd gate pmos utmost point source the 4th gate pmos is extremely connected and connects the 3rd bias voltage simultaneously; The grid of the 3rd PMOS pipe is connected with drain electrode; The 7th NMOS tube grid is connected and connects the first biasing simultaneously with the 8th NMOS tube grid; The 7th NMOS pipe source electrode is connected with the 11 NMOS pipe drain electrode; The 8th NMOS pipe source electrode is connected with the 12 NMOS pipe drain electrode; The 11 NMOS tube grid, the 12 NMOS tube grid are connected and connect the second bias voltage simultaneously with the 6th NMOS tube grid; The 11 NMOS pipe source electrode, the 12 NMOS pipe source electrode, all ground connection of the 6th NMOS pipe source electrode; The 6th NMOS tube grid is connected to drain with drain electrode simultaneously and is connected with reference current source; Another termination power of reference current source; The moved end a end of single-pole double-throw switch (SPDT) is connected with the 8th NMOS pipe drain electrode, b end in moved end is connected with the 12 NMOS tube grid, c end in moved end is not connected with the 8th NMOS tube grid.
Actual gain: the present invention proposes a kind of double mode low noise amplifier.Described amplifier is by two kinds of mode of operations of double mode biasing circuit, for differential amplifier circuit provides two kinds of bias voltages, make amplifying circuit work in two mode of operations: high gain mode and high linearity pattern, two kinds of patterns provide two kinds of mode of operations for receiver front end circuit, thereby have solved the problem of carrier leak.In addition, this biasing circuit copies differential amplifier circuit completely, and adopts reference current source control, has effectively suppressed PVT and has changed the impact on circuit performance.
Accompanying drawing explanation
Fig. 1 is the double mode amplifier circuit in low noise structure of one provided by the invention;
Fig. 2 (a) be double mode low noise amplifier of the present invention process corner under high gain mode be tt, voltage while being respectively 1.6V, 1.8V, 2.0V S21 vary with temperature curve chart;
Fig. 2 (b) be double mode low noise amplifier of the present invention process corner under high gain mode be tt, voltage while being respectively 1.6V, 1.8V, 2.0V S11 vary with temperature curve chart;
Fig. 2 (c) be double mode low noise amplifier of the present invention process corner under high gain mode be tt, voltage while being respectively 1.6V, 1.8V, 2.0V NF vary with temperature curve chart;
Fig. 2 (d) be double mode low noise amplifier of the present invention process corner under high gain mode be tt, voltage while being respectively 1.6V, 1.8V, 2.0V P1dB vary with temperature curve chart;
Fig. 3 (a) be double mode low noise amplifier of the present invention process corner under high linearity pattern be tt, voltage while being respectively 1.6V, 1.8V, 2.0V S21 vary with temperature curve chart;
Fig. 3 (b) be double mode low noise amplifier of the present invention process corner under high linearity pattern be tt, voltage while being respectively 1.6V, 1.8V, 2.0V S11 vary with temperature curve chart;
Fig. 3 (c) be double mode low noise amplifier of the present invention process corner under high linearity pattern be tt, voltage while being respectively 1.6V, 1.8V, 2.0V NF vary with temperature curve chart;
Fig. 3 (d) be double mode low noise amplifier of the present invention process corner under high linearity pattern be tt, voltage while being respectively 1.6V, 1.8V, 2.0V P1dB vary with temperature curve chart.
Embodiment
Below in conjunction with accompanying drawing, further illustrate a kind of double mode low noise amplifier of the present invention.
With reference to Fig. 1, the double mode low noise amplifier of one provided by the present invention constitutes this amplifier circuit by fully differential low noise amplifier and double mode science biasing circuit has positive and negative two-way input, output, this two-way circuit full symmetric design.RF
opfor the positive output end of differential amplifier; RF
onfor the negative output terminal of differential amplifier.
In described LNA core circuit, a NMOS pipe NM1 drain electrode is connected with the 3rd NMOS pipe NM3 source electrode; The 2nd NMOS pipe NM2 drain electrode is connected with the 4th NMOS pipe NM4 source electrode; The 3rd NMOS pipe NM3 drain electrode is connected with a PMOS pipe PM1 drain electrode; The 4th NMOS pipe NM4 drain electrode is connected with the 2nd PMOS pipe PM2 drain electrode; The 3rd NMOS pipe grid of NM3 and the grid of NM4 are connected with one end of the first resistance R 1, the second resistance R 2 respectively; Another termination supply voltage VDD of the first resistance R 1, the second resistance R 2; The source electrode of the one PMOS pipe PM1, the source electrode of the 2nd PMOS pipe PM2 are connected with supply voltage VDD respectively; The grid of the one PMOS pipe PM1, the 2nd PMOS pipe PM2 meets respectively the 3rd bias voltage Vbias3; Between the one NMOS pipe NM1 source electrode and grid, being connected the first capacitor C 1, the one NMOS pipe NM1 source electrode is connected with first inductance L 1 one end; Between the 2nd NMOS pipe NM2 source electrode and grid, be connected the second capacitor C 2; The 2nd NMOS pipe NM2 source electrode is connected with second inductance L 2 one end; First inductance L 1 other end, second inductance L 2 other ends are connected with the drain electrode of the 5th NMOS pipe NM5 as fully differential circuit tail current source respectively; The 5th NMOS pipe NM5 source ground, the 5th NMOS pipe NM5 grid meets one end of the 5th resistance R 5, the 5th resistance R 5 another termination the second bias voltage Vbias2; The one NMOS pipe NM1 grid is connected with the 3rd inductance L 3 one end, and the 3rd inductance L 3 another termination input signals are also connected with the 3rd resistance R 3 one end, the 3rd resistance R 3 another termination the first bias voltage Vbias1; The 2nd NMOS pipe NM2 grid is connected with the 4th inductance L 4 one end, and the 4th inductance L 4 another termination input signals are also connected with the 4th resistance R 4 one end, the 4th resistance R 4 another termination the first bias voltage Vbias1; The 3rd capacitor C 3 one end are connected with the 2nd NMOS pipe NM2 drain electrode and the 4th NMOS pipe NM4 source electrode respectively, and the 3rd capacitor C 3 other ends are connected with the grid of the 3rd NMOS pipe NM3; One end of the 4th capacitor C 4 is connected with the drain electrode of a NMOS pipe NM1 and the source electrode of the 3rd NMOS pipe NM3 respectively, and the 4th capacitor C 4 other ends are connected with the grid of the 4th NMOS pipe NM4; Common mode feedback circuit CMFB positive pole is connected with the positive output end of the differential output signal of fully differential circuit, and negative pole is connected with the negative output terminal of differential output signal, and the output of common mode feedback circuit CMFB is connected with the grid of the 5th NMOS pipe NM5.
In the controlled science biasing circuit of double mode switch described in Fig. 1, the 7th NMOS pipe NM7 drain electrode is connected with the 9th NMOS pipe NM9 source electrode; The 8th NMOS pipe NM8 drain electrode is connected with the tenth NMOS pipe NM10 source electrode; The 9th NMOS pipe NM9 drain electrode is connected with the drain electrode of the 3rd PMOS pipe PM3; The tenth NMOS pipe NM10 drain electrode is connected with the drain electrode of the 4th PMOS pipe PM4; The 9th NMOS pipe NM9 grid, the tenth NMOS pipe NM10 grid are connected with one end of the 6th resistance R 6, the 7th resistance R 7 respectively; The source electrode of the other end of the 6th resistance R 6, the 7th resistance R 7 and the 3rd PMOS pipe PM3, the 4th PMOS pipe PM4 is connected with power vd D respectively; The 3rd PMOS pipe PM3 gate source the 4th PMOS pipe PM4 grid is connected and connects the 3rd bias voltage Vbias3 simultaneously; The grid of the 3rd PMOS pipe PM3 is connected with drain electrode; The 7th NMOS pipe NM7 grid is connected and meets the first biasing Vbias1 simultaneously with the 8th NMOS pipe NM8 grid; The 7th NMOS pipe NM7 source electrode is connected with the 11 NMOS pipe NM11 drain electrode; The 8th NMOS pipe NM8 source electrode is connected with the 12 NMOS pipe NM12 drain electrode; The 11 NMOS pipe NM11 grid, the 12 NMOS pipe NM12 grid are connected and meet the second bias voltage Vbias2 simultaneously with the 6th NMOS pipe NM6 grid; The 11 NMOS pipe NM11 source electrode, the 12 NMOS pipe NM12 source electrode, all ground connection of the 6th NMOS pipe NM6 source electrode; The 6th NMOS pipe NM6 grid is connected to drain with drain electrode simultaneously and is connected with reference current source Iref; Another termination power of reference current source Iref; The moved end a end of single-pole double-throw switch (SPDT) S is connected with the 8th NMOS pipe NM8 drain electrode, b end in moved end is connected with the 12 NMOS pipe NM12 grid, c end in moved end is not connected with the 8th NMOS pipe NM8 grid.
Pattern biasing circuit, the grid of its PM4 meets the Vbise3 of differential amplifier circuit, the Vbise1 of the c termination differential amplifier circuit of single-pole double-throw switch (SPDT) S, the Vbise2 of the b termination differential amplifier circuit of single-pole double-throw switch (SPDT) S.
With reference to Fig. 1, the 6th NMOS pipe is managed with the 11 NMOS respectively, the 12 NMOS pipe, the 3rd PMOS pipe forms current mirror, the left side one row branch current of biasing circuit is controlled by reference current source Iref like this, the branch road on the right has copied the structure of differential amplifier circuit completely, by design circuit device size, make two-way electric current in full accord, as can be seen from Figure 2, the branch road on the right and the branch current on the left side are just the same, the electric current in whole low noise amplifier circuit of so just having realized reference current source control, the impact that makes like this operating current in circuit changed by PVT.
Figure 2 shows that double mode low noise amplifier of the present invention process corner under high gain mode be tt, voltage while being respectively 1.6V, 1.8V, 2.0V S21 (a), S11 (b), NF (c), P1dB (d) vary with temperature curve chart.Can find out while changing between-40 ℃ to 85 ℃ with temperature, the gain of low noise amplifier provided by the present invention under high gain mode maintains 10dB-12dB under the different supply voltage of 1.6V, 1.8V, 2V; All be less than-10dB of S11 now, circuit Input matching is good; Noise factor maintains between 2～3dB, and noiseproof feature is better; 1dB compression point is less than-10, and is greater than-15, and the linearity is general.Illustrated that the present invention gains when high gain mode and noiseproof feature is good, and suppressed PVT and change the impact on circuit performance.
Figure 3 shows that double mode low noise amplifier of the present invention process corner under high linearity pattern be tt, voltage while being respectively 1.6V, 1.8V, 2.0V S21 (a), S11 (b), NF (c), P1dB (d) vary with temperature curve chart.Can find out while changing between-40 ℃ to 85 ℃ with temperature, the gain of low noise amplifier provided by the present invention under high gain mode maintains 4dB-6dB under the different supply voltage of 1.6V, 1.8V, 2V; All be less than-10dB of S11 now, circuit Input matching is good; Noise factor maintains between 2.5～4.5dB, and noiseproof feature is general; Between maintain-3dBm～1dBm of 1dB compression point, the linearity is better.Illustrated that the present invention's linearity when high linearity pattern is higher, and suppressed PVT and change the impact on circuit performance.
In sum, the double mode low noise amplifier that the present invention proposes provides high-gain and high linearity pattern, and under two kinds of patterns, all there is good performance effectively to suppress PVT and change the impact on circuit, this provides two kinds of mode of operations for receiver front end circuit, solved carrier leak problem, in ultrahigh frequency RFID receiver front end circuit, had broad application prospects.For those skilled in the art, according to above implementation of class, can be easy to other advantage and distortion of association.Therefore, the present invention is not limited to above-mentioned instantiation, and it carries out detailed, exemplary explanation as just example to a kind of form of the present invention.Not deviating from the scope of aim of the present invention, those of ordinary skills are equal to by various the technical scheme that replacement obtains according to above-mentioned instantiation, within all should being included in claim scope of the present invention and equivalency range thereof.
Claims (3)
1. a double mode low noise amplifier, it is characterized in that, this amplifier comprises low noise amplifier LNA core circuit and the controlled science biasing circuit of double mode switch, and the controlled science biasing circuit of switch provides required all biasings for core circuit; Switch S by the controlled science biasing circuit of control switch makes LNA core circuit work in different two states, i.e. high gain mode and high linearity pattern; Wherein, when the moved end a of the not moved end of switch S c connecting valve S, LNA works in high linearity pattern; When moved end, the contact b of the not moved end of switch S c connecting valve S, LNA works in high gain mode.
2. the double mode low noise amplifier of one as claimed in claim 1, is characterized in that in described LNA core circuit, and NMOS pipe (NM1) drain electrode is connected with the 3rd NMOS pipe (NM3) source electrode; The 2nd NMOS pipe (NM2) drain electrode is connected with the 4th NMOS pipe (NM4) source electrode; The 3rd NMOS pipe (NM3) drain electrode is connected with PMOS pipe (PM1) drain electrode; The 4th NMOS pipe (NM4) drain electrode is connected with the 2nd PMOS pipe (PM2) drain electrode; The 3rd NMOS pipe grid of (NM3) and the grid of NM4 are connected with one end of the first resistance (R1), the second resistance (R2) respectively; Another termination supply voltage (VDD) of the first resistance (R1), the second resistance (R2); The source electrode of the one PMOS pipe (PM1), the source electrode of the 2nd PMOS pipe (PM2) are connected with supply voltage (VDD) respectively; The grid of the one PMOS pipe (PM1), the 2nd PMOS pipe (PM2) connects respectively the 3rd bias voltage (Vbias3); Between the one NMOS pipe (NM1) source electrode and grid, be connected the first electric capacity (C1), NMOS pipe (NM1) source electrode is connected with the first inductance (L1) one end; Between the 2nd NMOS pipe (NM2) source electrode and grid, be connected the second electric capacity (C2); The 2nd NMOS pipe (NM2) source electrode is connected with the second inductance (L2) one end; The first inductance (L1) other end, the second inductance (L2) other end are connected with the drain electrode of the 5th NMOS pipe (NM5) as fully differential circuit tail current source respectively; The 5th NMOS pipe (NM5) source ground, the 5th NMOS pipe (NM5) grid connects one end of the 5th resistance (R5), another termination second bias voltage (Vbias2) of the 5th resistance (R5); The one NMOS pipe (NM1) grid is connected with the 3rd inductance (L3) one end, and the 3rd another termination input signal of inductance (L3) is also connected with the 3rd resistance (R3) one end, another termination first bias voltage (Vbias1) of the 3rd resistance (R3); The 2nd NMOS pipe (NM2) grid is connected with the 4th inductance (L4) one end, and the 4th another termination input signal of inductance (L4) is also connected with the 4th resistance (R4) one end, another termination first bias voltage (Vbias1) of the 4th resistance (R4); The 3rd electric capacity (C3) one end is connected with the 2nd NMOS pipe (NM2) drain electrode and the 4th NMOS pipe (NM4) source electrode respectively, and the 3rd electric capacity (C3) other end is connected with the grid that the 3rd NMOS manages (NM3); One end of the 4th electric capacity (C4) is connected with the drain electrode of a NMOS pipe (NM1) and the source electrode of the 3rd NMOS pipe (NM3) respectively, and the 4th electric capacity (C4) other end is connected with the grid that the 4th NMOS manages (NM4); Common mode feedback circuit (CMFB) positive pole is connected with the positive output end of the differential output signal of fully differential circuit, and negative pole is connected with the negative output terminal of differential output signal, and the output of common mode feedback circuit (CMFB) is connected with the grid that the 5th NMOS manages (NM5).
3. the double mode low noise amplifier of one as claimed in claim 1, is characterized in that in the controlled science biasing circuit of described double mode switch, and the 7th NMOS pipe (NM7) drain electrode is connected with the 9th NMOS pipe (NM9) source electrode; The 8th NMOS pipe (NM8) drain electrode is connected with the tenth NMOS pipe (NM10) source electrode; The 9th NMOS pipe (NM9) drain electrode is connected with the drain electrode of the 3rd PMOS pipe (PM3); The tenth NMOS pipe (NM10) drain electrode is connected with the drain electrode of the 4th PMOS pipe (PM4); The 9th NMOS pipe (NM9) grid, the tenth NMOS pipe (NM10) grid are connected with one end of the 6th resistance (R6), the 7th resistance (R7) respectively; The source electrode of the other end of the 6th resistance (R6), the 7th resistance (R7) and the 3rd PMOS pipe (PM3), the 4th PMOS pipe (PM4) is connected with power supply (VDD) respectively; The 3rd PMOS pipe (PM3) gate source the 4th PMOS pipe (PM4) grid is connected and connects the 3rd bias voltage (Vbias3) simultaneously; The grid of the 3rd PMOS pipe (PM3) is connected with drain electrode; The 7th NMOS pipe (NM7) grid and the 8th NMOS manage (NM8) grid and are connected and connect the first biasing (Vbias1) simultaneously; The 7th NMOS pipe (NM7) source electrode is managed (NM11) drain electrode with the 11 NMOS and is connected; The 8th NMOS pipe (NM8) source electrode is managed (NM12) drain electrode with the 12 NMOS and is connected; The 11 NMOS pipe (NM11) grid, the 12 NMOS pipe (NM12) grid and the 6th NMOS manage (NM6) grid and are connected and connect the second bias voltage (Vbias2) simultaneously; The 11 NMOS pipe (NM11) source electrode, the 12 NMOS pipe (NM12) source electrode, all ground connection of the 6th NMOS pipe (NM6) source electrode; The 6th NMOS pipe (NM6) grid is connected and drains and be connected with reference current source (Iref) simultaneously with drain electrode; Another termination power of reference current source (Iref); The moved end a end of single-pole double-throw switch (SPDT) (S) is connected with the 8th NMOS pipe (NM8) drain electrode, b end in moved end is connected with the 12 NMOS pipe (NM12) grid, c end in moved end is not connected with the 8th NMOS pipe (NM8) grid.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108321158A (en) * | 2018-04-11 | 2018-07-24 | 南京邮电大学 | Static random access memory (sram) cell and preparation method thereof based on photoelectric device |
| CN109088604A (en) * | 2018-08-06 | 2018-12-25 | 上海华虹宏力半导体制造有限公司 | A kind of variable gain low-noise amplifier |
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| CN101098127A (en) * | 2006-06-19 | 2008-01-02 | 株式会社瑞萨科技 | RF power amplifier |
| CN102096079A (en) * | 2009-12-12 | 2011-06-15 | 杭州中科微电子有限公司 | Method for constructing radio frequency front end of multi-mode multi-band satellite navigation receiver and module thereof |
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| US20030218500A1 (en) * | 2002-05-22 | 2003-11-27 | Mitsubishi Denki Kabushiki Kaisha | Power amplifier capable of switching gain while suppressing noise power in reception band |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108321158A (en) * | 2018-04-11 | 2018-07-24 | 南京邮电大学 | Static random access memory (sram) cell and preparation method thereof based on photoelectric device |
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| CN109088604A (en) * | 2018-08-06 | 2018-12-25 | 上海华虹宏力半导体制造有限公司 | A kind of variable gain low-noise amplifier |
| CN109088604B (en) * | 2018-08-06 | 2022-02-15 | 上海华虹宏力半导体制造有限公司 | Variable gain low noise amplifier |
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| CN103746661B (en) | 2017-01-18 |
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