CN211830713U

CN211830713U - High-adaptability low-noise fully-differential high-voltage operational amplifier

Info

Publication number: CN211830713U
Application number: CN202020827104.0U
Authority: CN
Inventors: 张明; 马学龙; 焦炜杰; 杨金权; 石方敏
Original assignee: Runshixin Technology Shenzhen Co Ltd
Current assignee: Runshixin Technology Shenzhen Co Ltd
Priority date: 2020-05-18
Filing date: 2020-05-18
Publication date: 2020-10-30
Anticipated expiration: 2030-05-18

Abstract

The utility model relates to a high adaptability's low noise fully differential high pressure operational amplifier, it includes input stage circuit, output stage circuit, goes up cascode circuit and lower cascode circuit; the power supply circuit also comprises a bias power supply circuit which can provide power supplies required by the input stage circuit, the output stage circuit, the upper cascode circuit and the lower cascode circuit, and a voltage clamping protection circuit which can be adaptively connected with the bias power supply circuit, the input stage circuit and the lower cascode circuit; the drain voltage of the low-voltage NMOS device in the lower cascode circuit can be clamped within the working voltage range of the low-voltage NMOS device through the matching of the bias power supply circuit and the voltage clamping protection circuit. The utility model discloses can effectively guarantee the reliability of the lower cascode circuit who adopts the low pressure device to can improve the job stabilization nature of whole high pressure operational amplifier circuit, and under the condition of effective noise reduction, keep operational amplifier's slew rate index, safe and reliable.

Description

High-adaptability low-noise fully-differential high-voltage operational amplifier

Technical Field

The utility model relates to an operational amplifier, especially a low noise fully differential high voltage operational amplifier of high adaptability belongs to high voltage operational amplifier's technical field.

Background

The high-voltage operational amplifier has the common characteristic functions of signal acquisition, comparison, amplification, operation and the like, is very suitable for occasions requiring small volume and large output power due to the characteristic of high voltage and large current, is widely applied to all electronic devices requiring high-power output at the final stage, and has wide application in various fields of industrial control systems, communication, automotive electronics, rail transit, new energy conservation, military/civil aerospace, weaponry and the like.

At present, for a high-voltage operational amplifier adopting a cascode architecture (cascode), the cascode architecture in the high-voltage operational amplifier includes an upper cascode circuit and a lower cascode circuit, and the lower cascode circuit is generally formed by NMOS transistors. When the output voltage of the high-voltage operational amplifier changes, the drain terminal voltage of the NMOS transistor in the lower cascode circuit is higher, and since the NMOS transistor in the lower cascode circuit is mostly a low-voltage device with a working voltage of 5V, when the drain terminal voltage of the NMOS transistor is higher, the working life of the lower cascode circuit can be affected, and further the normal use of the whole high-voltage operational amplifier can be affected. If the lower cascode circuit adopts a high-voltage device, the performance is poor compared with a low-voltage device, and meanwhile, the area of the lower cascode circuit is increased, so that the area of the whole high-voltage operational amplifier is increased, and even the cost of the high-voltage operational amplifier is increased.

Disclosure of Invention

The utility model aims at overcoming the not enough of existence among the prior art, provide a low noise fully differential high pressure operational amplifier of high adaptability, its reliability that can effectively guarantee the lower cascode circuit who adopts the low pressure device to can improve the job stabilization nature of whole high pressure operational amplifier circuit, and under the condition of effective noise reduction, keep operational amplifier's slew rate index, safe and reliable.

According to the technical scheme provided by the utility model, the low-noise fully-differential high-voltage operational amplifier with high adaptability comprises an input stage circuit, an output stage circuit, an upper cascode circuit in adaptive connection with the output stage circuit and a lower cascode circuit in adaptive connection with the output stage circuit;

the power supply circuit also comprises a bias power supply circuit which can provide power supplies required by the input stage circuit, the output stage circuit, the upper cascode circuit and the lower cascode circuit, and a voltage clamping protection circuit which can be adaptively connected with the bias power supply circuit, the input stage circuit and the lower cascode circuit; the drain voltage of the low-voltage NMOS device in the lower cascode circuit can be clamped within the working voltage range of the low-voltage NMOS device through the matching of the bias power supply circuit and the voltage clamping protection circuit.

The input stage circuit comprises a PMOS tube PM20 and a PMOS tube PM21, the gate end of the PMOS tube PM20 is connected with the differential input signal INP, and the gate end of the PMOS tube PM21 is connected with the differential input signal INN;

the voltage clamp protection circuit comprises a PMOS tube PM32, a PMOS tube PM33 and a constant voltage driving circuit connected with the grid terminal of the PMOS tube PM32 and the grid terminal of the PMOS tube PM33, the constant voltage driving circuit is connected with the output end of a bias current source in the bias power supply circuit, and the constant voltage driving circuit and the bias current source can generate required fixed driving voltages at the grid terminal of the PMOS tube PM32 and the grid terminal of the PMOS tube PM 33;

the source end of the PMOS pipe PM32 is connected with the drain end of the PMOS pipe PM20, one input end of the output stage circuit and the drain end of the NMOS pipe NM6 in the lower cascode circuit, the source end of the PMOS pipe PM33 is connected with the drain end of the PMOS pipe PM21, the other input end of the output stage circuit and the drain end of the NMOS pipe NM5 in the lower cascode circuit, and the drain end of the PMOS pipe PM32 and the drain end of the PMOS pipe PM33 are grounded; the source terminal of the PMOS transistor PM20 and the source terminal of the PMOS transistor PM21 are connected to the bias power supply circuit.

The bias power supply circuit comprises a PMOS tube PM5, and the drain end of the PMOS tube PM5 is connected with the source end of the PMOS tube PM20 and the source end of the PMOS tube PM 21;

the gate terminal of the PMOS tube PM5 is connected with the gate terminal of a PMOS tube PM4, the gate terminal of a PMOS tube PM1, the drain terminal of a PMOS tube PM1, the drain terminal of an NMOS tube NM19 and the gate terminal of a PMOS tube PM17 in the bias power supply circuit;

the source terminal of a PMOS pipe PM1, the source terminal of a PMOS pipe PM2, the source terminal of a PMOS pipe PM3, the source terminal of a PMOS pipe PM16 in the upper cascode circuit, the source terminal of a PMOS pipe PM18 and the source terminal of a PMOS pipe PM19 are all connected with voltage VDD, and the gate terminal of a PMOS pipe PM2 is connected with the gate terminal of a PMOS pipe PM3, the drain terminal of a PMOS pipe PM4 and the drain terminal of an NMOS pipe NM 20; the drain end of the PMOS pipe PM3 is connected with the source end of the PMOS pipe PM5, the drain end of the PMOS pipe PM2 is connected with the source end of the PMOS pipe PM4, the gate end of the PMOS pipe PM19 is connected with the gate end of the PMOS pipe PM18 and the gate end of the PMOS pipe PM16, and the drain end of the PMOS pipe PM17 and the drain end of the NMOS pipe NM10 are connected;

the gate terminal of the NMOS tube NM19, the gate terminal of the NMOS tube NM20, the gate terminal of the NMOS tube NM18, the gate terminal of the NMOS tube NM17 and the drain terminal of the NMOS tube NM17 are all connected with one output terminal of a bias current source, and the gate terminal of the NMOS tube NM10, the gate terminal of the NMOS tube NM14, the gate terminal of the NMOS tube NM15, the gate terminal of the NMOS tube NM16 and the drain terminal of the NMOS tube NM18 are all connected with the other output terminal of the bias current source; the source terminal of the NMOS transistor NM18 is connected with the drain terminal of the NMOS transistor NM16, the source terminal of the NMOS transistor NM19 is connected with the drain terminal of the NMOS transistor NM15, the source terminal of the NMOS transistor NM20 is connected with the drain terminal of the NMOS transistor NM14, the source terminal of the NMOS transistor NM10, the source terminal of the NMOS transistor NM14, the source terminal of the NMOS transistor NM15, the source terminal of the NMOS transistor NM16 and the source terminal of the NMOS transistor NM17 are all grounded, and the drain terminal of the PMOS transistor PM18 and the drain terminal of the PMOS transistor PM19 are in adaptive connection.

The constant voltage driving circuit comprises a PMOS tube PM30 connected with the output end of a bias current source, a source terminal of a PMOS tube PM30 is connected with the output end of the bias current source, a grid terminal of the PMOS tube PM30 and a drain terminal of a PMOS tube PM30 are connected with a source terminal of a PMOS tube PM31, a grid terminal of a PMOS tube PM31 is connected with a drain terminal of a PMOS tube PM31, a grid terminal of a PMOS tube PM32, a grid terminal of a PMOS tube PM33, a drain terminal of an NMOS tube NM30 and a grid terminal of an NMOS tube NM30, a source terminal of an NMOS tube NM30 is connected with grid terminals of a drain terminal NM31 and a drain terminal NM31 of an NMOS tube NM31, and.

The offset voltage storage circuit is used for storing offset voltage of the input stage circuit and comprises a PMOS tube PM22 and a PMOS tube PM23, the grid end of the PMOS tube PM22 is connected with one end of a capacitor C2, the grid end of the PMOS tube PM23 is connected with one end of a capacitor C1, the drain end of the PMOS tube PM22 is connected with the drain end of the PMOS tube PM20, and the drain end of the PMOS tube PM23 is connected with the drain end of a PMOS tube PM 21; the other end of the capacitor C1 and the other end of the capacitor C2 are both grounded;

the source terminal of the PMOS tube PM22 and the source terminal of the PMOS tube PM23 are connected with the drain terminal of the PMOS tube PM7, the gate terminal of the PMOS tube PM7 is connected with the gate terminal of the PMOS tube PM5, the source terminal of the PMOS tube PM7 is connected with the drain terminal of the PMOS tube PM6, the gate terminal of the PMOS tube PM6 is connected with the gate terminal of the PMOS tube PM3, and the source terminal of the PMOS tube PM6 is connected with the voltage VDD.

The common-mode voltage generating circuit can provide common-mode voltage required by the output-stage circuit, and comprises a PMOS tube PM24, a PMOS tube PM25, an NMOS tube NM8 and an NMOS tube NM 9;

the gate terminal of the NMOS tube NM9 and the gate terminal of the NMOS tube NM8 are connected with the gate terminal of the NMOS tube NM18, the source terminal of the NMOS tube NM9 is connected with the drain terminal of the NMOS tube NM10, the drain terminal of the PMOS tube PM24 and the drain terminal of the PMOS tube PM25, and the drain terminal of the NMOS tube NM9 is connected with the drain terminal of the PMOS tube PM17, the gate terminal of the PMOS tube PM16, the gate terminal of the PMOS tube PM18 and the gate terminal of the PMOS tube PM 19; the grid end of the PMOS pipe PM24 and the grid end of the PMOS pipe PM25 are connected with the drain end of the PMOS pipe PM9, the drain end of the NMOS pipe NM11 and the grid end of the NMOS pipe NM11, and the source end of the NMOS pipe NM11 is grounded;

the source end of the PMOS pipe PM24 is connected with the drain end of the PMOS pipe PM11 and the output stage circuit, the source end of the PMOS pipe PM25 is connected with the drain end of the PMOS pipe PM13 and the output stage circuit, the drain end of the NMOS pipe NM8 is connected with the drain end of the PMOS pipe PM15 and the gate end of the NMOS pipe NM7, the gate end of the NMOS pipe NM6 and the gate end of the NMOS pipe NM 5; the source terminal of the NMOS tube NM5, the source terminal of the NMOS tube NM6 and the source terminal of the NMOS tube NM7 are all grounded, the drain terminal of the NMOS tube NM7 is connected with the source terminal of the NMOS tube NM8 and the output stage circuit, and the drain terminal of the NMOS tube NM5 and the drain terminal of the NMOS tube NM6 are connected with the output stage circuit; the gate terminal of the PMOS transistor PM9 is connected with the gate terminal of the PMOS transistor PM5, the gate terminal of the PMOS transistor PM11, the gate terminal of the PMOS transistor PM13 and the gate terminal of the PMOS transistor PM15, the source terminal of the PMOS transistor PM9 is connected with the drain terminal of the PMOS transistor PM8, the source terminal of the PMOS transistor PM11 is connected with the drain terminal of the PMOS transistor PM10, the source terminal of the PMOS transistor PM13 is connected with the drain terminal of the PMOS transistor PM12, the source terminal of the PMOS transistor PM15 is connected with the drain terminal of the PMOS transistor PM14, the source terminal of the PMOS transistor PM8, the source terminal of the PMOS transistor PM10, the source terminal of the PMOS transistor PM12 and the source terminal of the PMOS transistor PM14 are all connected with the voltage VDD, and the gate terminal of the PMOS transistor PM8 is connected with the gate terminal of the PMOS transistor PM3, the gate terminal of the PMOS transistor PM 573.

The output stage circuit comprises a first gain amplifier and a second gain amplifier, wherein the input end of the first gain amplifier is respectively connected with the drain end of a PMOS pipe PM19, the drain end of a PMOS pipe PM18, the drain end of a PMOS pipe PM16 and the source end of a PMOS pipe PM17, one output end of the first gain amplifier is connected with the gate end of a PMOS pipe PM28, the other output end of the first gain amplifier is connected with the gate end of a PMOS pipe PM29, the drain end of the PMOS pipe PM28 is connected with the gate end of a PMOS pipe PM26 and the drain end of an NMOS pipe NM3, the drain end of a PMOS pipe PM29 is connected with the gate end of a PMOS pipe PM27 and the drain end of an NMOS pipe NM4, the source end of a PMOS pipe PM26 is connected with the source end of a PMOS pipe PM25, the source end of a PMOS pipe PM 48 is connected with the source end of a PMOS pipe PM24, and the drain ends of a PMOS pipe PM;

the grid end of the NMOS tube NM3 is connected with one output end of the second gain amplifier, the grid end of the NMOS tube NM4 is connected with the other output end of the second gain amplifier, the source end of the NMOS tube NM3 is connected with the drain end of the NMOS tube NM6, one input end of the second gain amplifier and the drain end of the PMOS tube PM20, the source end of the NMOS tube NM4 is connected with the drain end of the NMOS tube NM5, the other input end of the second gain amplifier and the drain end of the PMOS tube PM21, and the third input end of the second gain amplifier is connected with the source end of the NMOS tube NM8 and the drain end of the NMOS tube NM 7.

The drain end of the PMOS pipe PM28, the gate end of the PMOS pipe PM26 and the drain end of the NMOS pipe NM3 are mutually connected to form a differential output end OUTN, and the drain end of the PMOS pipe PM29, the gate end of the PMOS pipe PM27 and the drain end of the NMOS pipe NM4 are mutually connected to form a differential output end OUTP;

the voltage swing rate maintaining circuit is adaptively connected with the differential output end OUTN and the differential output end OUTP of the output stage circuit, and when the current flowing through the upper cascode circuit is reduced through the bias power supply circuit, the voltage swing rate of the voltage output by the differential output end OUTN and the differential output end OUTP of the output stage circuit can be improved by the voltage swing rate maintaining circuit, so that the voltage swing rate of the high-voltage operational amplifier is kept stable.

The slew rate maintaining circuit comprises a bootstrap switch circuit, and the bootstrap switch circuit is in adaptive connection with the differential output end OUTN and the differential output end OUTP.

The bootstrap switch circuit comprises an NMOS tube NM1 and an NMOS tube NM2, the grid end of the NMOS tube NM1, the drain end of the NMOS tube NM1 and the source end of the NMOS tube NM2 are connected with a differential output end OUTN, and the source end of the NMOS tube NM1, the drain end of the NMOS tube NM2 and the grid end of the NMOS tube NM2 are connected with a differential output end OUTP.

The utility model has the advantages that: the voltage clamping circuit can be connected with the lower cascode circuit, the input stage circuit and the bias power supply circuit, and the drain voltage of the low-voltage NMOS device in the lower cascode circuit can be clamped within the working voltage range of the low-voltage NMOS device through the voltage clamping circuit, so that the reliability of the lower cascode circuit adopting the low-voltage power semiconductor device can be effectively ensured, and the performance of the high-voltage operational amplifier can be ensured;

a slew rate improving circuit is added between a differential output end OUTN and a differential output end OUTP of an output stage circuit, and when the current flowing through an upper cascode circuit is reduced through a bias power supply circuit, the slew rate of the voltage output by the differential output end OUTN and the differential output end OUTP of the output stage circuit can be improved by using a slew rate maintaining circuit, so that the slew rate of the high-voltage operational amplifier is kept stable, and the slew rate index of the operational amplifier is maintained under the condition of effectively reducing noise, and the high-voltage operational amplifier is safe and reliable.

Drawings

Fig. 1 is a schematic circuit diagram of the present invention.

Description of reference numerals: 1-a bias current source, 2-a first gain amplification circuit, and 3-a second gain amplification circuit.

Detailed Description

The invention is further described with reference to the following specific drawings and examples.

As shown in fig. 1: in order to effectively ensure the reliability of a lower cascode circuit adopting a low-voltage device and improve the working stability of the whole high-voltage operational amplifier circuit, the utility model comprises an input stage circuit, an output stage circuit, an upper cascode circuit in adaptive connection with the output stage circuit and a lower cascode circuit in adaptive connection with the output stage circuit;

Specifically, the input stage circuit, the output stage circuit, the upper cascode circuit, and the lower cascode circuit may all adopt the existing commonly used circuit form, and the process and the principle of amplifying the differential signal by the specific coordination among the bias power supply circuit, the input stage circuit, the output stage circuit, the upper cascode circuit, and the lower cascode circuit are consistent with those in the prior art, and are specifically known to those skilled in the art, and are not described herein again. The embodiment of the utility model provides an in, can provide input stage circuit, output stage circuit, go up cascode circuit and the required power of cascode circuit work down through the biasing power supply circuit, voltage clamp protection circuit and biasing power supply circuit, input stage circuit and cascode circuit adaptation connection down.

As can be seen from the above description, in order to ensure the performance of the high-voltage operational amplifier, the lower cascode circuit is formed by using low-voltage NMOS devices, which are typically 5V devices. When the input voltage of the high-voltage operational amplifier changes, after the high-voltage operational amplifier performs operational amplification, the drain of the low-voltage NMOS device in the lower cascode circuit generates a higher voltage, and the higher drain voltage may cause damage to the low-voltage NMOS device, further cause damage to the high-voltage operational amplifier.

In the embodiment of the present invention, when the input voltage of the high-voltage operational amplifier changes, the drain voltage of the low-voltage NMOS device in the lower cascode circuit can be clamped within the working voltage range of the low-voltage NMOS device by the voltage clamp protection circuit, that is, the drain voltage of the low-voltage NMOS device can be clamped within 5V by the voltage clamp protection circuit; when the high-voltage operational amplifier works normally, the voltage clamping protection circuit cannot influence the drain voltage of the low-voltage NMOS device in the lower cascode circuit; specifically, the clamping of the voltage clamping protection circuit on the drain voltage of the low-voltage NMOS device in the lower cascode circuit may only occur when the input voltage of the high-voltage operational amplifier changes; when the high-voltage operational amplifier works normally, the voltage clamping protection circuit is in a closed state, the voltage clamping circuit in the closed state cannot influence the drain terminal voltage of the low-voltage NMOS device in the lower cascode circuit, and the drain voltage of the low-voltage NMOS device is in the working voltage range of the low-voltage NMOS device, so that the working state of the lower cascode circuit is not influenced, and the power consumption of the high-voltage operational amplifier can be reduced. Therefore, when the input voltage of the high-voltage operational amplifier changes, the drain voltage of the low-voltage NMOS device in the lower cascode circuit can be clamped within the working voltage range of the low-voltage NMOS device through the cooperation of the bias power supply circuit and the voltage clamping protection circuit, so that the reliability of the lower cascode circuit adopting the low-voltage device can be effectively ensured, and the performance of the high-voltage operational amplifier can be ensured under the condition of not adopting the high-voltage device.

Further, the input stage circuit comprises a PMOS transistor PM20 and a PMOS transistor PM21, the gate terminal of the PMOS transistor PM20 is connected with the differential input signal INP, and the gate terminal of the PMOS transistor PM21 is connected with the differential input signal INN;

the voltage clamping protection circuit comprises a PMOS tube PM32, a PMOS tube PM33 and a constant voltage driving circuit connected with the grid terminal of the PMOS tube PM32 and the grid terminal of the PMOS tube PM33, the constant voltage driving circuit is connected with the output end of a bias current source 1 in a bias power supply circuit, and required fixed driving voltages can be generated at the grid terminal of the PMOS tube PM32 and the grid terminal of the PMOS tube PM33 through the bias current source 1 and the constant voltage driving circuit;

In the embodiment of the utility model, PMOS pipe PM20 and PMOS pipe PM21 constitute the input stage circuit. The voltage clamp protection circuit can be formed by the PMOS transistor PM32, the PMOS transistor PM33 and the constant voltage driving circuit, and a desired fixed driving voltage can be generated at the gate terminal of the PMOS transistor PM32 and the gate terminal of the PMOS transistor PM33 by the bias current source 1 and the constant voltage driving circuit.

Specifically, when the operational amplifier is in operation, a fixed driving voltage of 2V to 3V can be generated at the gate terminal of the PMOS transistor PM32 and the gate terminal of the PMOS transistor PM33 by the bias current source 1 and the constant voltage driving circuit. When the differential input signal INP and the differential input signal INN have a difference, at this time, the input voltage of the high-voltage operational amplifier changes, and then the corresponding voltages can be generated at the source terminals of the PMOS transistor PM32 and the PMOS transistor PM33 through the PMOS transistor PM20 and the PMOS transistor PM21, respectively, and when the corresponding gate-source voltages of the PMOS transistor PM32 and the PMOS transistor PM33 reach the required turn-on voltage, the PMOS transistor PM32 and the PMOS transistor PM33 are turned on, and after the PMOS transistor PM32 and the PMOS transistor PM33 are turned on, the voltage clamps at the drain terminal of the NMOS transistor NM5 in the lower cascode circuit and the drain terminal of the NMOS transistor NM6 in the lower cascode circuit can be below 5V by using the PMOS transistor PM32 and the PMOS transistor PM33, so as to ensure the operational reliability of the NMOS transistor NM5 and the NMOS transistor NM6, and realize the operational reliability of the lower cascode circuit.

When there is no difference between the differential input signal INP and the differential input signal INN, at this time, the high-voltage operational amplifier is in a normal operating state, and it can be known from the connection between the PMOS transistor PM32 and the PMOS transistor PM33 and the PMOS transistor PM20 and the PMOS transistor PM21, when the voltage difference between the source terminal of the PMOS transistor PM32 and the gate terminal of the PMOS transistor PM32 does not satisfy the turn-on voltage of the PMOS transistor PM32, the PMOS transistor PM32 cannot be conducted, the state of the PMOS transistor PM33 is the same as the state of the PMOS transistor PM32, and the voltage at the drain terminal of the NMOS transistor NM5 in the lower cascode circuit and the voltage at the drain terminal of the NMOS transistor NM6 in the lower cascode circuit are not affected by the PMOS transistor PM32 and the PMOS transistor PM33 in the non-conducting state.

Further, the constant voltage driving circuit comprises a PMOS tube PM30 connected with an output end of a bias current source 1, a source terminal of a PMOS tube PM30 is connected with an output end of the bias current source 1, a gate terminal of a PMOS tube PM30 and a drain terminal of a PMOS tube PM30 are connected with a source terminal of a PMOS tube PM4, a gate terminal of a PMOS tube PM31 is connected with a drain terminal of a PMOS tube PM31, a gate terminal of the PMOS tube PM32, a gate terminal of a PMOS tube PM33, a drain terminal of an NMOS tube NM30 and a gate terminal of an NMOS tube NM30, a source terminal of an NMOS tube NM30 is connected with a drain terminal of an NMOS tube NM31 and a gate terminal of an NMOS tube NM31, and a source terminal of.

The embodiment of the utility model provides an in, PMOS pipe PM30, PMOS pipe PM31 can form constant current voltage with the cooperation of bias current source 1, and NMOS pipe NM30 and NMOS pipe NM31 can be equivalent to resistance, and can adopt resistance to replace, specifically can select according to actual need, and it is no longer repeated here.

Further, the bias power supply circuit comprises a PMOS transistor PM5, and the drain end of the PMOS transistor PM5 is connected with the source end of the PMOS transistor PM20 and the source end of the PMOS transistor PM 21;

the gate terminal of the NMOS tube NM19, the gate terminal of the NMOS tube NM20, the gate terminal of the NMOS tube NM18, the gate terminal of the NMOS tube NM17 and the drain terminal of the NMOS tube NM17 are all connected with one output terminal of the bias current source 1, and the gate terminal of the NMOS tube NM10, the gate terminal of the NMOS tube NM14, the gate terminal of the NMOS tube NM15, the gate terminal of the NMOS tube NM16 and the drain terminal of the NMOS tube NM18 are all connected with the other output terminal of the bias current source 1; the source terminal of the NMOS transistor NM18 is connected with the drain terminal of the NMOS transistor NM16, the source terminal of the NMOS transistor NM19 is connected with the drain terminal of the NMOS transistor NM15, the source terminal of the NMOS transistor NM20 is connected with the drain terminal of the NMOS transistor NM14, the source terminal of the NMOS transistor NM10, the source terminal of the NMOS transistor NM14, the source terminal of the NMOS transistor NM15, the source terminal of the NMOS transistor NM16 and the source terminal of the NMOS transistor NM17 are all grounded, and the drain terminal of the PMOS transistor PM18 and the drain terminal of the PMOS transistor PM19 are in adaptive connection.

The embodiment of the utility model provides an in, PMOS pipe PM16, PMOS pipe PM18, PMOS pipe PM19 constitutes the cascode circuit, PMOS pipe PM1, PMOS pipe PM2, PMOS pipe PM3, PMOS pipe PM4, PMOS pipe PM5, PMOS pipe PM17, NMOS pipe NM17, NMOS pipe NM18, NMOS pipe NM19, NMOS pipe NM20, NMOS pipe NM16, NMOS pipe NM15, NMOS pipe NM14 and NMOS pipe NM10 constitute a part of biasing power supply circuit.

The magnitude of the voltage VDD is selected according to actual needs, and is well known to those skilled in the art. The bias current source 1 may adopt a conventional form, and the output end of the bias current source 1 outputs a current with the same magnitude as the current loaded to the constant voltage driving circuit by the bias current source 1. The NMOS transistor NM17 can be matched with a bias current source 1 to provide bias voltages required by an NMOS transistor NM18, an NMOS transistor NM19, an NMOS transistor NM20, an NMOS transistor NM16, an NMOS transistor NM15, an NMOS transistor NM14, an NMOS transistor NM10 and the like, and the PMOS transistor PM1 can be matched with a voltage VDD to provide bias voltages required by a PMOS transistor PM2, a PMOS transistor PM3, a PMOS transistor PM4, a PMOS transistor PM5 and a PMOS transistor PM 17.

According to the circuit, the NMOS tube NM18, the NMOS tube NM19, the NMOS tube NM20, the NMOS tube NM16, the NMOS tube NM15, the NMOS tube NM14 and the NMOS tube NM10 form a current mirror, and the current of the upper cascode circuit can form a channel through the PMOS tube PM17 and the NMOS tube NM10, so that the current flowing through the upper cascode circuit can be adjusted when the current flowing through the NMOS tube NM10 is controlled or adjusted. The embodiment of the utility model provides an in, through reducing the electric current that flows through NMOS pipe NM10, can reduce the electric current of the cascode circuit of flowing through, simultaneously, can reduce the electric current of the cascode circuit under flowing through, the mode and the process that the NMOS pipe NM10 electric current was flowed through in specific reduction are known for this technical field personnel, and no longer repeated here.

The offset voltage storage circuit comprises a PMOS pipe PM22 and a PMOS pipe PM23, the gate end of the PMOS pipe PM22 is connected with one end of a capacitor C2, the gate end of the PMOS pipe PM23 is connected with one end of a capacitor C1, the drain end of the PMOS pipe PM22 is connected with the drain end of the PMOS pipe PM20, and the drain end of the PMOS pipe PM23 is connected with the drain end of a PMOS pipe PM 21; the other end of the capacitor C1 and the other end of the capacitor C2 are both grounded;

The embodiment of the utility model provides an in, the drain terminal of PMOS pipe PM22, the drain terminal of PMOS pipe PM23 still with output stage circuit connection, through PMOS pipe PM22 and electric capacity C2 cooperation and PMOS pipe PM23 and electric capacity C1 cooperation, offset voltage storage circuit can detect and store input stage circuit's offset voltage, and output stage circuit can offset the offset voltage that offset voltage storage circuit obtained to can realize the low detuning and the purpose that the low temperature floats.

The embodiment of the utility model provides an in, NMOS pipe NM5, NMOS pipe NM6 constitute cascade circuit down, NMOS pipe NM8, NMOS pipe NM9, PMOS pipe PM24, PMOS pipe PM25, PMOS pipe PM10, PMOS pipe PM11, PMOS pipe PM12, PMOS pipe PM13, PMOS pipe PM14 and PMOS pipe PM15 constitute common mode voltage and produce the circuit. As can be seen from fig. 1, the gate terminal of the NMOS transistor NM9, the gate terminal of the NMOS transistor NM8 and the gate terminal of the NMOS transistor NM18 are connected, that is, connected to the drain terminal of the NMOS transistor NM17 and the gate terminal of the NMOS transistor NM 17.

Further, the output stage circuit comprises a first gain amplifier 2 and a second gain amplifier 3, an input end of the first gain amplifier 2 is connected with a drain end of a PMOS transistor PM19, a drain end of a PMOS transistor PM18, a drain end of a PMOS transistor PM16 and a source end of the PMOS transistor PM17 respectively, an output end of the first gain amplifier 2 is connected with a gate end of the PMOS transistor PM28, another output end of the first gain amplifier 2 is connected with a gate end of the PMOS transistor PM29, a drain end of the PMOS transistor PM28 is connected with a gate end of the PMOS transistor PM26 and a drain end of the NMOS transistor 3, an NM end of the PMOS transistor PM29 is connected with a gate end of the PMOS transistor PM27 and a drain end of the NMOS transistor NM4, a source end of the PMOS transistor PM26 is connected with a source end of the PMOS transistor PM25, a source end of the PMOS transistor PM27 is connected with a source end of the PMOS transistor PM24, and drain ends of the PMOS transistor PM26 and the PM 27;

the gate terminal of the NMOS transistor NM3 is connected to an output terminal of the second gain amplifier 3, the gate terminal of the NMOS transistor NM4 is connected to another output terminal of the second gain amplifier 3, the source terminal of the NMOS transistor NM3 is connected to the drain terminal of the NMOS transistor NM6, an input terminal of the second gain amplifier 3, and the drain terminal of the PMOS transistor PM20, the source terminal of the NMOS transistor NM4 is connected to the drain terminal of the NMOS transistor NM5, another input terminal of the second gain amplifier 3, and the drain terminal of the PMOS transistor PM21, and the third input terminal of the second gain amplifier 3 is connected to the source terminal of the NMOS transistor NM8, and the drain terminal of the NMOS transistor NM 7.

The embodiment of the utility model provides an in, can carry out required gain through first gain amplifier 2, second gain amplifier 3 and amplify, generally, first gain amplifier 2 adopts identical circuit structure with second gain amplifier 3, and first gain amplifier 2, second gain amplifier 3 can adopt current commonly used circuit form, specifically can select as required, and here is no longer repeated. When the offset voltage storage circuit exists, the drain end of the PMOS transistor PM22 and the drain end of the PMOS transistor PM23 of the offset voltage storage circuit are connected to the corresponding input ends of the second gain amplifier 3, that is, the drain end of the PMOS transistor PM22 is connected to the drain end of the PMOS transistor PM20, and the drain end of the PMOS transistor PM23 is connected to the drain end of the PMOS transistor PM 21. As can be seen from the above description, the source terminal of the NMOS transistor NM3 and the drain terminal of the PMOS transistor PM22 are further connected to the source terminal of the PMOS transistor PM32, and the source terminal of the NMOS transistor NM4 and the drain terminal of the PMOS transistor PM23 are further connected to the source terminal of the PMOS transistor PM 33.

Further, the drain end of the PMOS transistor PM28, the gate end of the PMOS transistor PM26, and the drain end of the NMOS transistor NM3 are connected to each other to form a differential output terminal OUTN, and the drain end of the PMOS transistor PM29, the gate end of the PMOS transistor PM27, and the drain end of the NMOS transistor NM4 are connected to each other to form a differential output terminal OUTP;

The utility model discloses it is realIn an embodiment, a slew rate holding circuit is added between a differential output terminal OUTN and a differential output terminal OUTP of an output stage circuit, a power supply required by the operation of an input stage circuit, the output stage circuit, an upper cascode circuit, a lower cascode circuit and the slew rate holding circuit can be provided through a bias power supply circuit, and the current state relation among the upper cascode circuit, the lower cascode circuit and the input stage circuit is consistent with the current relation in the technology, namely the current of the input stage circuit is I₁The current of the upper cascode circuit is I₂The current of the lower cascode circuit is I₃，I₃＝0.5I₁+I₂. According to the transfer relation of the current, the current flowing through the upper cascode circuit can be reduced by adjusting the parameters of the bias power supply circuit, and when the current flowing through the upper cascode circuit is reduced, the current flowing through the lower cascode circuit is reduced, and the noise of the fully differential high-voltage operational amplifier can be reduced according to the corresponding relation between the current and the transconductance and the corresponding relation between the transconductance and the noise.

After the current flowing through the upper cascode circuit and the lower cascode circuit is reduced, the slew rate of the fully differential high-voltage operational amplifier is reduced. The embodiment of the utility model provides an in, increase slew rate holding circuit between difference output OUTN, difference output OUTP, can promote through difference output OUTN, difference output OUTP output voltage's slew rate through slew rate holding circuit to make high-pressure operational amplifier's slew rate remain stable. Specifically, the slew rate of the high-voltage operational amplifier is kept stable, that is, the slew rate of the high-voltage operational amplifier is consistent with the slew rate under the condition that the current flowing through the upper cascode circuit and the current flowing through the lower cascode circuit are reduced without reducing the corresponding current flowing through the upper cascode circuit and the corresponding current flowing through the lower cascode circuit, the slew rate can fluctuate within an allowable range in accordance with the consistent slew rate, the specific allowable range can be set according to the requirements of practical applications, and the specific setting process is well known by those skilled in the art and is not described herein again.

Further, the slew rate maintaining circuit comprises a bootstrap switch circuit, and the bootstrap switch circuit is adaptively connected with the differential output terminal OUTN and the differential output terminal OUTP.

During specific implementation, the slew rate holding circuit adopts a bootstrap switch circuit, and the characteristics of the bootstrap switch circuit can be utilized to realize the improvement of the slew rates of the output voltages of the differential output terminal OUTN and the differential output terminal OUTP. Of course, in specific implementation, the slew rate holding circuit may also adopt other circuit forms, which may be specifically selected according to needs, as long as the slew rate can be improved, so that the slew rate of the high-voltage operational amplifier can be kept stable.

Further, the bootstrap switch circuit includes an NMOS transistor NM1 and an NMOS transistor NM2, the gate terminal of the NMOS transistor NM1, the drain terminal of the NMOS transistor NM1 and the source terminal of the NMOS transistor NM2 are connected to the differential output terminal OUTN, and the source terminal of the NMOS transistor NM1, the drain terminal of the NMOS transistor NM2 and the gate terminal of the NMOS transistor NM2 are connected to the differential output terminal OUTP.

The embodiment of the utility model provides an in, constitute bootstrap switch circuit through NMOS pipe NM1, NMOS pipe NM2, when differential output OUTN and differential output OUTP within a definite time differential are greater than 0.7V, NMOS pipe NM1 or NMOS pipe NM2 switch on to make bootstrap switch circuit automatic switch-on, make operational amplifier's the rapid grow of slew rate, realize that the slew rate promotes, thereby make high pressure operational amplifier's slew rate remain stable.

Claims

1. A high-adaptability low-noise fully-differential high-voltage operational amplifier comprises an input stage circuit, an output stage circuit, an upper cascode circuit and a lower cascode circuit, wherein the upper cascode circuit is in adaptive connection with the output stage circuit; the method is characterized in that:

2. The highly adaptable low noise fully differential high voltage operational amplifier according to claim 1, wherein: the input stage circuit comprises a PMOS tube PM20 and a PMOS tube PM21, the gate end of the PMOS tube PM20 is connected with the differential input signal INP, and the gate end of the PMOS tube PM21 is connected with the differential input signal INN;

the voltage clamp protection circuit comprises a PMOS tube PM32, a PMOS tube PM33 and a constant voltage driving circuit connected with the grid terminal of the PMOS tube PM32 and the grid terminal of the PMOS tube PM33, the constant voltage driving circuit is connected with the output end of a bias current source (1) in the bias power supply circuit, and the constant voltage driving circuit and the bias current source (1) can generate required fixed driving voltage at the grid terminal of the PMOS tube PM32 and the grid terminal of the PMOS tube PM 33;

3. The highly adaptable low noise fully differential high voltage operational amplifier according to claim 2, wherein: the bias power supply circuit comprises a PMOS tube PM5, and the drain end of the PMOS tube PM5 is connected with the source end of the PMOS tube PM20 and the source end of the PMOS tube PM 21;

the gate terminal of the NMOS tube NM19, the gate terminal of the NMOS tube NM20, the gate terminal of the NMOS tube NM18, the gate terminal of the NMOS tube NM17 and the drain terminal of the NMOS tube NM17 are all connected with one output terminal of the bias current source (1), and the gate terminal of the NMOS tube NM10, the gate terminal of the NMOS tube NM14, the gate terminal of the NMOS tube NM15, the gate terminal of the NMOS tube NM16 and the drain terminal of the NMOS tube NM18 are all connected with the other output terminal of the bias current source (1); the source terminal of the NMOS transistor NM18 is connected with the drain terminal of the NMOS transistor NM16, the source terminal of the NMOS transistor NM19 is connected with the drain terminal of the NMOS transistor NM15, the source terminal of the NMOS transistor NM20 is connected with the drain terminal of the NMOS transistor NM14, the source terminal of the NMOS transistor NM10, the source terminal of the NMOS transistor NM14, the source terminal of the NMOS transistor NM15, the source terminal of the NMOS transistor NM16 and the source terminal of the NMOS transistor NM17 are all grounded, and the drain terminal of the PMOS transistor PM18 and the drain terminal of the PMOS transistor PM19 are in adaptive connection.

4. The highly adaptable low noise fully differential high voltage operational amplifier according to claim 2, wherein: the constant voltage driving circuit comprises a PMOS tube PM30 connected with the output end of a bias current source (1), the source end of a PMOS tube PM30 is connected with the output end of the bias current source (1), the grid end of a PMOS tube PM30 and the drain end of a PMOS tube PM30 are connected with the source end of a PMOS tube PM4, the grid end of a PMOS tube PM31 is connected with the drain end of a PMOS tube PM31, the grid end of the PMOS tube PM32, the grid end of a PMOS tube PM33, the drain end of an NMOS tube NM30 and the grid end of an NMOS tube NM30, the source end of an NMOS tube NM30 is connected with the drain end of an NMOS tube NM31 and the grid end of an NMOS tube NM31, and the source end of.

5. The highly adaptable low noise fully differential high voltage operational amplifier according to claim 3, wherein: the offset voltage storage circuit is used for storing offset voltage of the input stage circuit and comprises a PMOS tube PM22 and a PMOS tube PM23, the grid end of the PMOS tube PM22 is connected with one end of a capacitor C2, the grid end of the PMOS tube PM23 is connected with one end of a capacitor C1, the drain end of the PMOS tube PM22 is connected with the drain end of the PMOS tube PM20, and the drain end of the PMOS tube PM23 is connected with the drain end of a PMOS tube PM 21; the other end of the capacitor C1 and the other end of the capacitor C2 are both grounded;

6. The highly adaptable low noise fully differential high voltage operational amplifier according to claim 5, wherein: the common-mode voltage generating circuit can provide common-mode voltage required by the output-stage circuit, and comprises a PMOS tube PM24, a PMOS tube PM25, an NMOS tube NM8 and an NMOS tube NM 9;

the source end of the PMOS pipe PM24 is connected with the drain end of the PMOS pipe PM11 and the output stage circuit, the source end of the PMOS pipe PM25 is connected with the drain end of the PMOS pipe PM13 and the output stage circuit, the drain end of the NMOS pipe NM8 is connected with the drain end of the PMOS pipe PM15 and the gate end of the NMOS pipe NM7, the gate end of the NMOS pipe NM6 and the gate end of the NMOS pipe NM 5; the source terminal of the NMOS tube NM5, the source terminal of the NMOS tube NM6 and the source terminal of the NMOS tube NM7 are all grounded, the drain terminal of the NMOS tube NM7 is connected with the source terminal of the NMOS tube NM8 and the output stage circuit, and the drain terminal of the NMOS tube NM5 and the drain terminal of the NMOS tube NM6 are connected with the output stage circuit;

the gate terminal of the PMOS transistor PM9 is connected with the gate terminal of the PMOS transistor PM5, the gate terminal of the PMOS transistor PM11, the gate terminal of the PMOS transistor PM13 and the gate terminal of the PMOS transistor PM15, the source terminal of the PMOS transistor PM9 is connected with the drain terminal of the PMOS transistor PM8, the source terminal of the PMOS transistor PM11 is connected with the drain terminal of the PMOS transistor PM10, the source terminal of the PMOS transistor PM13 is connected with the drain terminal of the PMOS transistor PM12, the source terminal of the PMOS transistor PM15 is connected with the drain terminal of the PMOS transistor PM14, the source terminal of the PMOS transistor PM8, the source terminal of the PMOS transistor PM10, the source terminal of the PMOS transistor PM12 and the source terminal of the PMOS transistor PM14 are all connected with the voltage VDD, and the gate terminal of the PMOS transistor PM8 is connected with the gate terminal of the PMOS transistor PM3, the gate terminal of the PMOS transistor PM 573.

7. The highly adaptable low noise fully differential high voltage operational amplifier according to claim 6, wherein: the output stage circuit comprises a first gain amplifier (2) and a second gain amplifier (3), wherein the input end of the first gain amplifier (2) is respectively connected with the drain end of a PMOS pipe PM19, the drain end of a PMOS pipe PM18, the drain end of a PMOS pipe PM16 and the source end of a PMOS pipe PM17, one output end of the first gain amplifier (2) is connected with the gate end of the PMOS pipe PM28, the other output end of the first gain amplifier (2) is connected with the gate end of the PMOS pipe PM29, the drain end of the PMOS pipe PM28 is connected with the gate end of a PMOS pipe PM26 and the drain end of an NMOS pipe NM3, the drain end of the PMOS pipe PM29 is connected with the drain ends of a PMOS pipe PM27 and an NMOS pipe NM4, the source end of a PMOS pipe PM26 is connected with the source end of a PMOS pipe PM25, the source end of the PMOS pipe PM27 is connected with the drain end of a PMOS pipe PM24, and the drain ends of the PMOS pipe PM26 and;

the grid end of the NMOS tube NM3 is connected with one output end of the second gain amplifier (3), the grid end of the NMOS tube NM4 is connected with the other output end of the second gain amplifier (3), the source end of the NMOS tube NM3 is connected with the drain end of the NMOS tube NM6, one input end of the second gain amplifier (3) and the drain end of the PMOS tube PM20, the drain end of the NMOS tube NM4 is connected with the drain end of the NMOS tube NM5, the other input end of the second gain amplifier (3) and the drain end of the PMOS tube PM21, and the third input end of the second gain amplifier (3) is connected with the source end of the NMOS tube NM8 and the drain end of the NMOS tube NM 7.

8. The highly adaptable low noise fully differential high voltage operational amplifier according to claim 7, wherein: the drain end of the PMOS pipe PM28, the gate end of the PMOS pipe PM26 and the drain end of the NMOS pipe NM3 are mutually connected to form a differential output end OUTN, and the drain end of the PMOS pipe PM29, the gate end of the PMOS pipe PM27 and the drain end of the NMOS pipe NM4 are mutually connected to form a differential output end OUTP;

9. The highly adaptable low noise fully differential high voltage operational amplifier according to claim 8, wherein: the slew rate maintaining circuit comprises a bootstrap switch circuit, and the bootstrap switch circuit is in adaptive connection with the differential output end OUTN and the differential output end OUTP.

10. The highly adaptable low noise fully differential high voltage operational amplifier according to claim 9, wherein: the bootstrap switch circuit comprises an NMOS tube NM1 and an NMOS tube NM2, the grid end of the NMOS tube NM1, the drain end of the NMOS tube NM1 and the source end of the NMOS tube NM2 are connected with a differential output end OUTN, and the source end of the NMOS tube NM1, the drain end of the NMOS tube NM2 and the grid end of the NMOS tube NM2 are connected with a differential output end OUTP.