CN115996044A

CN115996044A - Fast comparator

Info

Publication number: CN115996044A
Application number: CN202310282200.XA
Authority: CN
Inventors: 漆星宇; 张明
Original assignee: Jiangsu Runic Technology Co ltd
Current assignee: Jiangsu Runic Technology Co ltd
Priority date: 2023-03-22
Filing date: 2023-03-22
Publication date: 2023-04-21
Anticipated expiration: 2043-03-22
Also published as: CN115996044B

Abstract

The invention discloses a fast comparator, which comprises a differential input pair tube, a tail current, a load circuit, a common source amplifying circuit and a digital logic circuit, wherein the differential input pair tube, the tail current and the load circuit are sequentially connected, and the common source amplifying circuit and the digital logic circuit are sequentially connected; the power supply circuit further comprises a Class-AB output control circuit and a clamping circuit, wherein the input end of the Class-AB output control circuit is connected with the load circuit, the output end of the Class-AB output control circuit is connected with one end of the clamping circuit, and the other end of the clamping circuit is connected with the input end of the common source amplifying circuit. The fast comparator can prevent the related MOS tube in the circuit from entering the deep linear region by adding the Class-AB output control circuit and the clamping circuit, ensure that the key node does not generate larger voltage fluctuation, realize the characteristic of smaller transmission delay of the comparator and improve the performance of the comparator.

Description

Fast comparator

Technical Field

The invention belongs to the technical field of electronic circuits, and particularly relates to a fast comparator.

Background

In general, a comparator includes three parts, i.e., a differential input stage, an intermediate load stage and a digital logic output stage, which are sequentially connected, and the differential input structure is used to increase the data transmission rate of the comparator and reduce noise, however, when a differential voltage occurs during the operation of the comparator, the NMOS in the intermediate load stage enters a deep linear region, at which time the output of the digital logic output stage is at a low level, and the PMOS in the intermediate load stage enters a deep linear region, at which time the output of the digital logic output stage is at a high level. When the high-low level is converted, the related MOS transistors are converted between the deep linear region and the saturation region, so that long conversion time is required, and the transmission delay of the comparator is long.

Taking fig. 1 as an example, a structure diagram of a general push-pull output comparator is provided, wherein a differential input stage comprises an input pair of transistors formed by two NMOS transistors NM1 and NM2 and a current source (tail current) IB, an intermediate load stage comprises two groups of load transistors, one group of load transistors comprises PMOS transistors PM3, PM4, PM5 and PM6, the other group of load transistors comprises NMOS transistors NM3, NM4, NM5 and NM6, and the intermediate load stage integrally forms a folded cascode amplifier which can amplify signals of the differential input stage by a larger factor; the circuit structure also comprises a common source amplifying stage, wherein the NMOS tube NM9 and the PMOS tube PM8 are used for further amplifying the input small differential mode signals; the output of the common source amplifying stage is connected to a digital buffer, and the PMOS tubes PM9 and PM10 and the NMOS tubes NM10 and NM11 output comparison results; the specific circuit connection relationship is shown in fig. 1, and will not be described again.

In operation, as in FIG. 1, the input pair tube current I1+I2 is equal to the tail current IB, and when VIP is greater than VIN, I2 increases and I1 decreases, i.e., I2> I1; while i3=i5-I1, i4=i6-I2. Since PM5/PM6 is the same in size and the gate-source voltage is the same, NM3/NM4 is the same in size and the gate-source voltage is the same, if PM5/PM6 is in the saturation region, i5=i6, i3=i4. Then since I1 is not equal to I2, it is stated that PM5/PM6, NM3/NM4 have devices into the linear region. By setting a reasonable bias voltage V1/V2/V5, PM3/PM5/NM5/NM3 can be ensured to work in a saturation region. Typically, I6 is less than or equal to I5, I4 is less than or equal to I3, and I2 is now greater than I1, then I4 must be less than I3, and it can be inferred that NM4 enters the linear region, i.e., point a is a relatively low voltage. At this time, the NM9 is in an off or weak on state, the NM9 drain output voltage is high, and VOUT outputs a logic high level after passing through the digital buffer.

Similarly, the input pair tube current I1+I2 is equal to the tail current IB, and when VIP is less than VIN, I2 is reduced and I1 is increased, i.e. I2< I1; while i3=i5-I1, i4=i6-I2. Since PM5/PM6 is the same in size and the gate-source voltage is the same, NM3/NM4 is the same in size and the gate-source voltage is the same, if PM5/PM6 is in the saturation region, i5=i6, i3=i4. Then since I1 is not equal to I2, it is stated that PM5/PM6, NM3/NM4 have devices into the linear region. By setting a reasonable bias voltage V1/V2/V5, PM3/PM5/NM5/NM3 can be ensured to work in a saturation region. Normally, I6 is less than or equal to I5, I4 is less than or equal to I3, I2 is now less than I1, if PM4 does not enter the linear region, I6 is equal to I5, I4 is greater than I3, which is not possible, so PM6 enters the linear region, point a is at a higher potential, NM9 is in a strong conduction state, the drain is pulled strongly to a lower potential, and VOUT outputs a logic low level after passing through the digital buffer.

As can be seen from the above working principle, when the input differential mode voltage is large enough, the output can be inverted correspondingly, and then the load tube of the folded cascode amplifier can switch between the linear region and the saturation region in the operation process of the comparator, that is, the node a changes greatly, referring to fig. 2, the switching usually takes a long time, so that the transmission delay of the comparator is long.

Disclosure of Invention

The invention aims to provide a fast comparator which can shorten the transmission delay of the comparator and improve the performance of the comparator.

In order to achieve the above object, the solution of the present invention is:

the fast comparator comprises differential input pair tubes, tail current, a load circuit, a common source amplifying circuit and a digital logic circuit, wherein the differential input pair tubes, the tail current and the load circuit are sequentially connected, the common source amplifying circuit and the digital logic circuit are sequentially connected, and the differential input pair tubes and the tail current comprise connected differential input pair tubes and a current source; the power supply circuit further comprises a Class-AB output control circuit and a clamping circuit, wherein the input end of the Class-AB output control circuit is connected with the load circuit, the output end of the Class-AB output control circuit is connected with one end of the clamping circuit, and the other end of the clamping circuit is connected with the input end of the common source amplifying circuit.

The differential input pair pipe adopts an NMOS input pair pipe formed by NMOS tubes, a PMOS input pair pipe formed by PMOS tubes or an input pair pipe formed by NMOS tubes and PMOS tubes.

The load circuit comprises a first load and a second load, wherein the first load is connected to a power supply terminal, and the second load is connected to a ground terminal.

The first load adopts a PMOS tube, a PNP triode, a resistor or a combination of any two or three of the PMOS tube, the PNP triode and the resistor, and the second load adopts an NMOS tube, an NPN triode and the resistor or a combination of any two or three of the NMOS tube, the NPN triode and the resistor.

The differential input pair tube comprises a first NMOS tube and a second NMOS tube, wherein the drain electrode of the first NMOS tube and the drain electrode of the second NMOS tube are respectively connected to a first load, the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are commonly grounded, the grid electrode of the first NMOS tube is used as the negative input end of the fast comparator, and the grid electrode of the second NMOS tube is used as the positive input end of the fast comparator.

The Class-AB output control circuit comprises a first PMOS tube, a seventh NMOS tube and a second PMOS tube, wherein the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube, the source electrode and the drain electrode of the first PMOS tube are respectively used as the input end of the Class-AB output control circuit, the drain electrode of the seventh NMOS tube is connected with the source electrode of the second PMOS tube, the source electrode of the seventh NMOS tube is connected with the drain electrode of the second PMOS tube, and the grid electrode of the seventh NMOS tube is connected with the bias voltage; the clamping circuit comprises a seventh PMOS tube and an eighth NMOS tube, and the drain electrode of the seventh PMOS tube is connected with the drain electrode of the eighth NMOS tube and is commonly connected to the common source amplifying circuit; the source electrode and the grid electrode of the seventh PMOS tube are connected in parallel and are connected with the drain electrode of the seventh NMOS tube and the source electrode of the second PMOS tube together; the source electrode and the grid electrode of the eighth NMOS tube are connected in parallel and are commonly connected with the source electrode of the seventh NMOS tube and the drain electrode of the second PMOS tube.

The common source amplifying circuit comprises an eighth PMOS tube and a ninth NMOS tube, wherein the source electrode of the eighth PMOS tube is connected with a power supply, the source electrode of the ninth NMOS tube is grounded, and the drain electrode of the eighth PMOS tube is connected with the drain electrode of the ninth NMOS tube and is commonly connected with the drain electrode of the seventh PMOS tube and the drain electrode of the eighth NMOS tube; the grid electrode of the eighth PMOS tube is connected to the drain electrode of the seventh NMOS tube, the source electrode of the second PMOS tube, the source electrode of the seventh PMOS tube and the grid electrode of the seventh PMOS tube, and the grid electrode of the ninth NMOS tube is connected to the source electrode of the seventh NMOS tube, the drain electrode of the second PMOS tube, the source electrode of the eighth NMOS tube and the grid electrode of the eighth NMOS tube in parallel.

The load circuit comprises a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube;

the grid electrode of the fifth PMOS tube is connected with the grid electrode of the sixth PMOS tube, the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are both connected to a power supply, and the drain electrode of the fifth PMOS tube is connected with the source electrode of the third PMOS tube and is connected to the differential input pair tube and the first output end of tail current; the drain electrode of the sixth PMOS tube is connected with the source electrode of the fourth PMOS tube and is connected to the differential input pair tube and the second output end of the tail current; the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube, the drain electrode of the third PMOS tube is connected to the source electrode of the first PMOS tube in the Class-AB output control circuit, and the drain electrode of the fourth PMOS tube is respectively connected to the drain electrode of the seventh NMOS tube and the source electrode of the second PMOS tube in the Class-AB output control circuit;

the grid electrode of the fifth NMOS tube is connected with the grid electrode of the sixth NMOS tube, the drain electrode of the fifth NMOS tube is connected to the drain electrode of the first PMOS tube in the Class-AB output control circuit, and the drain electrode of the sixth NMOS tube is respectively connected to the source electrode of the seventh NMOS tube and the drain electrode of the second PMOS tube in the Class-AB output control circuit; the source electrode of the fifth NMOS tube is connected with the drain electrode of the third NMOS tube, and the source electrode of the sixth NMOS tube is connected with the drain electrode of the fourth NMOS tube; the source electrode of the third NMOS tube and the source electrode of the fourth NMOS tube are grounded, and the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube and is connected to the drain electrode of the first PMOS tube in the Class-AB output control circuit.

The load circuit comprises a fifth PNP triode, a sixth PNP triode, a third PMOS tube, a fourth PMOS tube, a fifth NMOS tube, a sixth NMOS tube, a third NPN triode and a fourth NPN triode;

the base electrode of the fifth PNP triode is connected with the base electrode of the sixth PNP triode, the emitter electrode of the fifth PNP triode and the emitter electrode of the sixth PNP triode are both connected to a power supply, and the collector electrode of the fifth PNP triode is connected with the source electrode of the third PMOS tube and is connected to the differential input pair tube and the first output end of tail current; the collector electrode of the sixth PNP triode is connected with the source electrode of the fourth PMOS tube and is connected to the differential input pair tube and the second output end of the tail current; the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube, the drain electrode of the third PMOS tube is connected to the drain electrode of the first PMOS tube in the Class-AB output control circuit, and the drain electrode of the fourth PMOS tube is respectively connected to the source electrode of the seventh NMOS tube and the drain electrode of the second PMOS tube in the Class-AB output control circuit;

the grid electrode of the fifth NMOS tube is connected with the grid electrode of the sixth NMOS tube, the drain electrode of the fifth NMOS tube is connected to the drain electrode of the first PMOS tube in the Class-AB output control circuit, and the drain electrode of the sixth NMOS tube is respectively connected to the source electrode of the seventh NMOS tube and the drain electrode of the second PMOS tube in the Class-AB output control circuit; the source electrode of the fifth NMOS tube is connected with the collector electrode of the third NPN triode, and the source electrode of the sixth NMOS tube is connected with the collector electrode of the fourth NPN triode; the emitter of the third NPN triode and the emitter of the fourth NPN triode are grounded, and the base electrode of the third NPN triode is connected with the base electrode of the fourth NPN triode and is connected to the drain electrode of the first PMOS tube in the Class-AB output control circuit.

The load circuit comprises a first resistor, a second resistor, a third PMOS tube, a fourth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube;

one end of the first resistor is connected with a power supply, and the other end of the first resistor is connected with the source electrode of the third PMOS tube and is connected to the differential input pair tube and the first output end of tail current; one end of the second resistor is connected with a power supply, and the other end of the second resistor is connected with the source electrode of the fourth PMOS tube and is connected to the differential input pair tube and the second output end of the tail current; the grid electrode of the third PMOS tube is connected to the drain electrode of the first PMOS tube in the Class-AB output control circuit, the grid electrode of the fourth PMOS tube is connected, and the drain electrodes of the third PMOS tube and the fourth PMOS tube are respectively connected to the source electrode of the seventh NMOS tube and the drain electrode of the second PMOS tube in the Class-AB output control circuit;

The load circuit comprises a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube;

one end of the first resistor is connected with a power supply, and the other end of the first resistor is connected with the source electrode of the fifth PMOS tube; one end of the second resistor is connected with a power supply, and the other end of the second resistor is connected with the source electrode of the sixth PMOS tube; the grid electrode of the fifth PMOS tube is connected with the grid electrode of the sixth PMOS tube, the drain electrode of the fifth PMOS tube is connected with the source electrode of the third PMOS tube and is connected to the differential input pair tube and the first input end of the tail current; the drain electrode of the sixth PMOS tube is connected with the source electrode of the fourth PMOS tube and is connected to the differential input pair tube and the second input end of the tail current; the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube, the drain electrode of the third PMOS tube is connected to the drain electrode of the first PMOS tube in the Class-AB output control circuit, and the drain electrode of the fourth PMOS tube is respectively connected to the source electrode of the seventh NMOS tube and the drain electrode of the second PMOS tube in the Class-AB output control circuit;

the grid electrode of the fifth NMOS tube is connected with the grid electrode of the sixth NMOS tube, the drain electrode of the fifth NMOS tube is connected to the drain electrode of the first PMOS tube in the Class-AB output control circuit, and the drain electrode of the sixth NMOS tube is respectively connected to the source electrode of the seventh NMOS tube and the drain electrode of the second PMOS tube in the Class-AB output control circuit; the source electrode of the fifth NMOS tube is connected with the drain electrode of the third NMOS tube, and the source electrode of the sixth NMOS tube is connected with the drain electrode of the fourth NMOS tube; the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube and is connected to the drain electrode of the first PMOS tube in the Class-AB output control circuit; the source electrode of the third NMOS tube is connected with one end of a third resistor, and the other end of the third resistor is grounded; and a source electrode of the fourth NMOS tube is connected with one end of a fourth resistor, and the other end of the fourth resistor is grounded.

After the scheme is adopted, the Class-AB output control circuit and the clamping circuit are added, so that the related MOS tube in the circuit can be prevented from entering a deep linear region, the key node is ensured not to generate larger voltage fluctuation, the characteristic of smaller transmission delay of the comparator is realized, and the performance of the comparator is improved.

Drawings

FIG. 1 is a block diagram of a conventional generic push-pull output comparator;

FIG. 2 is a diagram of the operational characteristics of the generic push-pull output comparator of FIG. 1;

FIG. 3 is an overall block diagram of the fast comparator of the present invention;

fig. 4 is a circuit configuration diagram of a first embodiment of the present invention;

FIG. 5 is a diagram of the operational characteristics of the circuit shown in FIG. 4;

fig. 6 is a circuit configuration diagram of a second embodiment of the present invention;

fig. 7 is a circuit configuration diagram of a third embodiment of the present invention;

fig. 8 is a circuit configuration diagram of a fourth embodiment of the present invention.

Detailed Description

The technical scheme and beneficial effects of the present invention will be described in detail below with reference to the accompanying drawings.

The invention provides a fast comparator, which comprises a differential input pair tube, a load circuit, a common source amplifying circuit and a digital logic circuit which are sequentially connected, and can be matched with the diagram shown in figure 3, and further comprises a Class-AB output control circuit and a clamping circuit, wherein the input end of the Class-AB output control circuit is connected with the load circuit, the output end of the Class-AB output control circuit is connected with one end of the clamping circuit, and the other end of the clamping circuit is connected with the input end of the common source amplifying circuit.

As a preferred embodiment of the present invention, the differential input pair tube may be an NMOS input pair tube only comprising an NMOS tube, a PMOS input pair tube only comprising a PMOS tube, or an input pair tube formed by commonly connecting an NMOS tube and a PMOS tube.

As a preferred embodiment of the present invention, the load circuit includes a first load and a second load, wherein the first load is connected to the power supply terminal, and the second load is connected to the ground terminal; the first load can be a PMOS tube, a PNP triode, a resistor or a combination of any two or three of the PMOS tube, the PNP triode and the resistor, and the second load can be an NMOS tube, an NPN triode, the resistor or a combination of any two or three of the three.

As shown in fig. 4, a first preferred implementation circuit structure of the fast comparator provided by the present invention is shown, wherein the differential input pair tube adopts an input pair tube composed of two NMOS tubes NM1 and NM2, the first load adopts a combination of all PMOS tubes, and the second load adopts a combination of all NMOS tubes; the common source amplifying circuit comprises an NMOS tube NM9 and a PMOS tube PM8, and is also used as an output tube of the Class-AB output control circuit; the digital logic circuit adopts the structure of a digital buffer, and the connecting structure is similar to the existing structure and is not repeated.

In the preferred implementation circuit structure provided by the invention, a Class-AB output control circuit is connected between a first load and a second load, and specifically comprises a PMOS tube PM1, an NMOS tube NM7 and a PMOS tube PM2, wherein the grid electrode of the PM1 is connected with the grid electrode of the PM2, the drain electrode of the NM7 is connected with the source electrode of the PM2, and the source electrode of the NM7 is connected with the drain electrode of the PM 2; the clamping circuit comprises a PMOS tube PM7 and an NMOS tube NM8, wherein the drain electrode of the PM7 is connected with the drain electrode of the NM8 and is defined as a Q point, and the Q point is also connected to the common source amplifying circuit; the source electrode and the grid electrode of PM7 are connected in parallel and defined as a P point, and the P point is also connected with the drain electrode of NM7 and the source electrode of PM 2; the source electrode and the grid electrode of NM8 are connected in parallel and are defined as N point, and the N point is also connected with the source electrode of NM7 and the drain electrode of PM 2; the control potential of the Class-AB output pipes PM8 and NM9 is separated by using a Class-AB output control circuit, and the swing amplitude of P and N points is limited by using a clamp transistor PM7/NM8, so that the load pipe of the folded cascode amplifier is not switched back and forth between a linear area and a saturation area, and the propagation delay is reduced.

When VIP is larger than VIN, NM4 enters the linear region, P point and N point are at a lower potential, Q point is at a high level, PM7 is conducted when Q point is at a high level, the potential of clamping P point is lower than Q point by a threshold voltage, at the moment, a current path from Q point to PM7, NM7 and NM6 to NM4 exists, and NM4 can be prevented from entering the linear region by reasonably designing the size of NM 7.

Similarly, when VIP is smaller than VIN, PM6 will enter the linear region, point P and point N are at a higher potential, point Q is at a low level, in fact, when point Q is at a low level, NM8 is turned on, the potential at the clamped point N is higher than point Q by a threshold voltage, and at this time, there is a current path through PM6, PM4, PM2 to NM8 by power supply, and PM6 can be ensured not to enter the linear region by reasonably designing the size of PM 2.

The operating characteristics of the P-point and the N-point are shown with reference to fig. 5.

As shown in fig. 6, a circuit structure diagram of a second embodiment of the present invention is different from the first embodiment in that the load circuit structure is a combination structure of PMOS transistors and PNP transistors, and specifically includes PNP transistors PM5 and PM6 and PMOS transistors PM3 and PM4, wherein the common base of PM5 and PM6 is connected, the emitter of PM5 and the emitter of PM6 are both connected to the power supply VDD, the collector of PM5 is connected to the source of PM3, and the collector of PM6 is connected to the source of PM 4; PM3 and PM4 are connected through a common gate, the drain electrode of PM3 is connected to the source electrode of PM1 in the Class-AB output control circuit, and the drain electrode of PM4 is connected to point P; the second load adopts a combined structure of an NMOS tube and an NPN triode, and specifically comprises NMOS tubes NM5 and NM6 and NPN triodes NM3 and NM4, wherein the NM5 and NM6 are connected with a common grid, the drain electrode of the NM5 is connected to the drain electrode of PM1 in a Class-AB output control circuit, the source electrode of the NM5 is connected with the collector electrode of NM3, the drain electrode of the NM6 is connected with the N point, and the source electrode of the NM6 is connected with the collector electrode of NM 4; the common base of NM3 and NM4 is connected, and the emitter of NM3 and the emitter of NM4 are grounded GND.

As shown in fig. 7, a circuit structure diagram of a third embodiment of the present invention is different from the first embodiment in that the load circuit structure is a combination structure of PMOS transistors and resistors, and specifically includes resistors R1 and R2 and PMOS transistors PM3 and PM4, wherein one ends of R1 and R2 are connected to a power supply VDD, the other end of R1 is connected to a source of PM3, and the other end of R2 is connected to a source of PM 4; PM3 and PM4 are connected through a common gate, the drain electrode of PM3 is connected to the source electrode of PM1 in the Class-AB output control circuit, and the drain electrode of PM4 is connected to point P; the second load has the same structure as the first embodiment, and a combination of all NMOS transistors is adopted, which is not described herein.

As shown in fig. 8, a circuit structure diagram of a fourth embodiment of the present invention is different from the first embodiment in that the load circuit structure is a combination structure of PMOS transistors and resistors, and specifically includes PMOS transistors PM3, PM4, PM5, PM6 and resistors R1, R2, wherein one ends of R1 and R2 are connected to a power supply VDD, the other end of R1 is connected to a source of PM5, and the other end of R2 is connected to a source of PM 6; PM5 and PM6 are connected in common with the grid electrode, the drain electrode of PM5 is connected with the source electrode of PM3, and the drain electrode of PM6 is connected with the source electrode of PM 4; PM3 and PM4 are connected through a common gate, the drain electrode of PM3 is connected to the source electrode of PM1 in the Class-AB output control circuit, and the drain electrode of PM4 is connected to point P; the second load adopts a combined structure of NMOS (N-channel metal oxide semiconductor) tubes and resistors, and specifically comprises NMOS tubes NM3, NM4, NM5 and NM6 and resistors R3 and R4, wherein the NM5 and NM6 are connected with a common grid, the drain electrode of the NM5 is connected to the drain electrode of PM1 in a Class-AB output control circuit, the source electrode of the NM5 is connected with the drain electrode of NM3, the drain electrode of the NM6 is connected to an N point, and the source electrode of the NM6 is connected with the drain electrode of NM 4; NM3 and NM4 are connected in common, a source electrode of NM3 is connected with one end of R3, a source electrode of NM4 is connected with one end of R4, and the other end of R3 and the other end of R4 are grounded GND.

The above embodiments are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereto, and any modification made on the basis of the technical scheme according to the technical idea of the present invention falls within the protection scope of the present invention.

Claims

1. The fast comparator comprises differential input pair tubes, tail current, a load circuit, a common source amplifying circuit and a digital logic circuit, wherein the differential input pair tubes, the tail current and the load circuit are sequentially connected, the common source amplifying circuit and the digital logic circuit are sequentially connected, and the differential input pair tubes and the tail current comprise connected differential input pair tubes and a current source; the method is characterized in that: the power supply circuit further comprises a Class-AB output control circuit and a clamping circuit, wherein the input end of the Class-AB output control circuit is connected with the load circuit, the output end of the Class-AB output control circuit is connected with one end of the clamping circuit, and the other end of the clamping circuit is connected with the input end of the common source amplifying circuit;

2. The fast comparator of claim 1, wherein: the differential input pair pipe adopts an NMOS input pair pipe formed by NMOS tubes, a PMOS input pair pipe formed by PMOS tubes or an input pair pipe formed by NMOS tubes and PMOS tubes.

3. The fast comparator of claim 1, wherein: the load circuit comprises a first load and a second load, wherein the first load is connected to a power supply terminal, and the second load is connected to a ground terminal.

4. A fast comparator according to claim 3, characterized in that: the first load adopts a PMOS tube, a PNP triode, a resistor or a combination of any two or three of the PMOS tube, the PNP triode and the resistor, and the second load adopts an NMOS tube, an NPN triode and the resistor or a combination of any two or three of the NMOS tube, the NPN triode and the resistor.

5. A fast comparator according to claim 3, characterized in that: the differential input pair tube comprises a first NMOS tube and a second NMOS tube, the drain electrodes of the first NMOS tube and the second NMOS tube are respectively connected to a first load, the source electrode of the first NMOS tube and the source electrode of the second NMOS tube are grounded together, the grid electrode of the first NMOS tube is used as the negative input end of the fast comparator, and the grid electrode of the second NMOS tube is used as the positive input end of the fast comparator.

6. The fast comparator of claim 1, wherein: the common source amplifying circuit comprises an eighth PMOS tube and a ninth NMOS tube, wherein the source electrode of the eighth PMOS tube is connected with a power supply, the source electrode of the ninth NMOS tube is grounded, and the drain electrode of the eighth PMOS tube is connected with the drain electrode of the ninth NMOS tube and is commonly connected with the drain electrode of the seventh PMOS tube and the drain electrode of the eighth NMOS tube; the grid electrode of the eighth PMOS tube is connected to the drain electrode of the seventh NMOS tube, the source electrode of the second PMOS tube, the source electrode of the seventh PMOS tube and the grid electrode of the seventh PMOS tube, and the grid electrode of the ninth NMOS tube is connected to the source electrode of the seventh NMOS tube, the drain electrode of the second PMOS tube, the source electrode of the eighth NMOS tube and the grid electrode of the eighth NMOS tube in parallel.

7. The fast comparator of claim 1, wherein: the load circuit comprises a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube;

8. The fast comparator of claim 1, wherein: the load circuit comprises a fifth PNP triode, a sixth PNP triode, a third PMOS tube, a fourth PMOS tube, a fifth NMOS tube, a sixth NMOS tube, a third NPN triode and a fourth NPN triode;

9. The fast comparator of claim 1, wherein: the load circuit comprises a first resistor, a second resistor, a third PMOS tube, a fourth PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube;

one end of the first resistor is connected with a power supply, and the other end of the first resistor is connected with the source electrode of the third PMOS tube and is connected to the differential input pair tube and the first output end of tail current; one end of the second resistor is connected with a power supply, and the other end of the second resistor is connected with the source electrode of the fourth PMOS tube and is connected to the differential input pair tube and the second output end of the tail current; the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube, the drain electrode of the third PMOS tube is connected to the drain electrode of the first PMOS tube in the Class-AB output control circuit, and the drain electrode of the fourth PMOS tube is respectively connected to the source electrode of the seventh NMOS tube and the drain electrode of the second PMOS tube in the Class-AB output control circuit;

10. The fast comparator of claim 1, wherein: the load circuit comprises a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube;