CN103208300A - Sense amplifier comparison circuit - Google Patents
Sense amplifier comparison circuit Download PDFInfo
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- CN103208300A CN103208300A CN2012100076139A CN201210007613A CN103208300A CN 103208300 A CN103208300 A CN 103208300A CN 2012100076139 A CN2012100076139 A CN 2012100076139A CN 201210007613 A CN201210007613 A CN 201210007613A CN 103208300 A CN103208300 A CN 103208300A
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Abstract
The invention discloses a sense amplifier comparison circuit. The sense amplifier comparison circuit comprises a memory unit circuit, clamp circuits comprising first and second clamp circuits, and first and second current conversion voltage circuits; a first current source generation circuit, wherein the output end of the first current source generation circuit is connected with the first clamp unit and the memory unit circuit; and a second current source generation circuit, wherein the output end of the second current source generation circuit is connected with the second clamp circuit and a reference unit circuit; the fist current conversion voltage circuit is connected between ground and the first clamp circuit, and the second current conversion voltage circuit is connected between the ground and the second clamp circuit; and one input end of a comparator is connected with a connection point between the first current conversion voltage circuit and the first clamp circuit, and the other input end of the comparator is connected with a connection point between the second current conversion voltage circuit and the second clamp circuit. The sense amplifier comparison circuit can be used under a low power supply voltage condition.
Description
Technical field
The present invention relates to circuit field, relate in particular to a kind of sense amplifier comparator circuit of reading.
Background technology
In storer memory, data are with 1 and the storage of 0 two kind of form, corresponding erase unit Erase cell and these two kinds of basic memory cells of programming unit Program cell respectively.When reading memory data, be Erase cell or Program cell in order to judge certain memory cell, just memory cell and a reference unit need be compared, this just need use sense amplifier sense amplifier comparator circuit.
Traditional sense amplifier structure comprises as shown in Figure 1: left and right sides two parts circuit and a comparer; This comparer comprises two input ends, an output terminal.
In the left-half circuit, floating gate type metal-oxide-semiconductor memory spare Mcell represents a memory cell of being chosen by column decode circuitry and array decoding circuit, its source ground, the control grid connects column decode circuitry, read voltage WL and be added in by column decode circuitry on the control grid of this memory cell Mcell, produce electric current I cell; The drain electrode of this memory cell Mcell is connected to the source electrode of N-type metal-oxide-semiconductor MN1 and the grid of N-type metal-oxide-semiconductor MN3 by array decoding circuit; The drain voltage of this memory cell Mcell is BL.
The voltage of the tie point of described array decoding circuit and N-type metal-oxide-semiconductor MN1, MN3 is sensebl; This tie point also is connected the end of the drain terminal capacitor C BL of described memory cell, the other end ground connection of this drain terminal capacitor C BL.
Described N-type metal-oxide-semiconductor MN1 is a clamper tube, its objective is voltage sensebl clamper between 0.8V～1.2V, to avoid drain stress (drain stress) effect of memory cell.The drain electrode of clamper tube MN1 links to each other with drain and gate as the P type metal-oxide-semiconductor MP1 of load pipe, and grid links to each other with the drain electrode of described N-type metal-oxide-semiconductor MN3.
Described N-type metal-oxide-semiconductor MN3 is a feedback pipe, its source ground, and drain electrode also links to each other with the drain electrode of P type metal-oxide-semiconductor MP3, for generation of the required bias voltage Vfb of described clamper tube MN1.
The grid of described P type metal-oxide-semiconductor MP3 connects bias voltage Vbias, and source electrode connects voltage source V
DD, be used to described feedback pipe MN3 that bias voltage is provided.
The source electrode of described load pipe MP1 connects voltage source V
DDDescribed electric current I cell is by described array decoding circuit, and clamper tube MN1, finally is applied on the load pipe MP1 of a diode type of attachment, thereby produces voltage sain in grid and the drain electrode of this load pipe MP1, as an input of described comparer; Obviously different memory cells produce different electric current I cell, thereby produce different comparative voltage sain.
In the right half part circuit, floating gate type metal-oxide-semiconductor memory spare Mref represents reference unit, is used for providing one can supply benchmark relatively, and row reference voltage Rowref is applied on the control grid of this reference unit Mref, produces a reference current Iref.The source ground of this reference unit Mref, drain electrode is connected to the source electrode of N-type metal-oxide-semiconductor Mcol, and drain voltage is RBL.
Described N-type metal-oxide-semiconductor Mcol is the column decoding pipe, and row reference voltage Colref is applied on the grid of this column decoding pipe Mcol; The drain electrode of this column decoding pipe Mcol is connected to the source electrode of N-type metal-oxide-semiconductor MN2, and the grid of N-type metal-oxide-semiconductor MN4, and the voltage of this tie point is rsensebl.
Described N-type metal-oxide-semiconductor MN2 is a clamper tube, its objective is voltage rsensebl clamper between 0.8V～1.2V, to avoid drain stress (drain stress) effect.The drain electrode of clamper tube MN2 links to each other with drain and gate as the P type metal-oxide-semiconductor MP2 of load pipe, and grid links to each other with the drain electrode of described N-type metal-oxide-semiconductor MN4.
Described N-type metal-oxide-semiconductor MN4 is a feedback pipe, its source ground, and drain electrode also links to each other with the drain electrode of P type metal-oxide-semiconductor MP4, for generation of the required bias voltage Vrfb of described clamper tube MN2.
The grid of described P type metal-oxide-semiconductor MP4 connects bias voltage Vrefbias, and source electrode connects voltage source V
DD, be used to described feedback pipe MN4 that bias voltage is provided.
The source electrode of described load pipe MP2 connects voltage source V
DDDescribed electric current I ref is by described column decoding pipe Mcol, and clamper tube MN2, finally be applied on the load pipe MP2 of a diode type of attachment, thereby produce voltage sainref in grid and the drain electrode of this load pipe MP1, as another input of described comparer.
Finally, described comparer comparative voltage sain and voltage sainref produce or 0 or 1 output signal SAout, thereby have finished the data read to memory cell.
In the top traditional structure, for generation of voltage, its source leakage can consume bigger voltage margin as load for load pipe MP1 and MP2, possesses enough precision and speed to guarantee comparator circuit, and this has just limited its application under the low supply voltage situation.Along with development of technology, employed supply voltage progressively reduces, and has been down to 1.8V at present and even below the 1.5V, and in this case, the sense amplifier comparator circuit of above-mentioned traditional structure is just no longer suitable.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of can being applied in and reads the sense amplifier comparator circuit under the low supply voltage situation.
In order to address the above problem, the invention provides a kind of sense amplifier comparator circuit of reading, comprising: comparer; Memory cell circuits, clamping circuit, first, second clamping circuit, first, second current conversion potential circuit;
The first electric current source generating circuit, output terminal connect described first clamping circuit and memory cell circuits;
The second electric current source generating circuit, output terminal connect described second clamping circuit and reference cell scheme;
The described first current conversion potential circuit be connected and first clamping circuit between, the described second current conversion potential circuit be connected and second clamping circuit between;
An input end of described comparer connects the tie point between the described first current conversion potential circuit and described first clamping circuit, and another input end connects the tie point of the described second current conversion potential circuit and described second clamping circuit.
Further, described first clamping circuit comprises:
First clamper tube, be used to described first clamper tube that first biasing circuit of bias voltage is provided;
Described first clamper tube is a P type metal-oxide-semiconductor, and the grid of this P type metal-oxide-semiconductor connects described first biasing circuit, and source electrode connects the output terminal of the described first electric current source generating circuit, and drain electrode connects the described first current conversion potential circuit.
Further, described first biasing circuit comprises:
A P type metal-oxide-semiconductor and a N-type metal-oxide-semiconductor, this P type metal-oxide-semiconductor is connected the grid of described first clamper tube with the common leak source of N-type metal-oxide-semiconductor;
The source electrode of described P type metal-oxide-semiconductor connects high level, and grid connects first bias voltage;
The source ground of described N-type metal-oxide-semiconductor, grid connect the source electrode of described first clamper tube.
Further, the described first current conversion potential circuit is first load that is connected between described first clamper tube drain electrode and the ground.
Further, described first load comprises the N-type metal-oxide-semiconductor of a diode type of attachment; The source ground of the N-type metal-oxide-semiconductor in this first load, drain and gate links to each other with the drain electrode of described first clamper tube.
Further, described second clamping circuit comprises:
Second clamper tube, be used to described second clamper tube that second biasing circuit of bias voltage is provided;
Described second clamper tube is a P type metal-oxide-semiconductor, and the grid of this P type metal-oxide-semiconductor connects described second biasing circuit, and source electrode connects the output terminal of the described second electric current source generating circuit, and drain electrode connects the described second current conversion potential circuit.
Further, described second biasing circuit comprises:
A P type metal-oxide-semiconductor and a N-type metal-oxide-semiconductor, this P type metal-oxide-semiconductor is connected the grid of described second clamper tube with the common leak source of N-type metal-oxide-semiconductor;
The source electrode of described P type metal-oxide-semiconductor connects high level, and grid connects second bias voltage;
The source ground of described N-type metal-oxide-semiconductor, grid connect the source electrode of described second clamper tube.
Further, the described second current conversion potential circuit is second load that is connected between described second clamper tube drain electrode and the ground.
Further, described second load comprises the N-type metal-oxide-semiconductor of a diode type of attachment; The source ground of the N-type metal-oxide-semiconductor in this second load, drain and gate links to each other with the drain electrode of described second clamper tube.
Further, described first clamping circuit is used for voltage clamper with the output terminal of the described first electric current source generating circuit between 0.8V～1.2V; Described second clamping circuit is used for voltage clamper with the output terminal of the described second electric current source generating circuit between 0.8V～1.2V.
Further, described memory cell circuits comprises:
Column decode circuitry, array decoding circuit, be connected the electric capacity between array decoding circuit and the ground;
Memory cell is a floating gate type metal-oxide-semiconductor memory spare, and the control grid connects described column decode circuitry, source ground, and drain electrode connects described first clamping circuit, the first electric current source generating circuit and described electric capacity by described array decoding circuit;
Described reference cell scheme comprises:
Reference unit is a floating gate type metal-oxide-semiconductor memory spare, source ground, and the control grid connects the row reference voltage;
The column decoding pipe is a N-type metal-oxide-semiconductor, and source electrode links to each other with the drain electrode of described reference unit, and grid connects the row reference voltage, and drain electrode connects described second clamping circuit and the second electric current source generating circuit.
Further, described first, second electric current source generating circuit respectively comprises:
A P type metal-oxide-semiconductor, grid connects the 3rd bias voltage, and source electrode connects voltage source, and drain electrode is as output terminal.
The present invention has folded load pipe and the clamper tube that is stacked on the storage unit top originally to get off, thereby has eliminated load pipe two ends attrition voltage nargin adverse effect in the traditional structure, has realized the application under low supply voltage.
Description of drawings
Fig. 1 is traditional structural representation of reading the sense amplifier comparator circuit;
Fig. 2 is the structural representation of reading the sense amplifier comparator circuit of embodiment one;
Fig. 3 is for reading the structural representation of sense amplifier comparator circuit in the example of embodiment one.
Embodiment
Below in conjunction with drawings and Examples technical scheme of the present invention is described in detail.
Need to prove that if do not conflict, each feature among the embodiment of the invention and the embodiment can mutually combine, all within protection scope of the present invention.
Embodiment one, and a kind of sense amplifier comparator circuit of reading as shown in Figure 2, comprising: comparer, memory cell circuits, reference cell scheme, first, second clamping circuit;
The first electric current source generating circuit, output terminal connect described first clamping circuit and memory cell circuits;
The second electric current source generating circuit, output terminal connect described second clamping circuit and reference cell scheme;
The first current conversion potential circuit, be connected and first clamping circuit between;
The second current conversion potential circuit, be connected and second clamping circuit between;
An input end of described comparer connects the tie point between the described first current conversion potential circuit and described first clamping circuit, and another input end connects the tie point of the described second current conversion potential circuit and described second clamping circuit.
In the present embodiment, described first clamping circuit can but be not limited to for described first current source is produced the voltage clamper of circuit output end between 0.8V～1.2V; Described second clamping circuit can but be not limited to for described second current source is produced the voltage clamper of circuit output end between 0.8V～1.2V.
In the present embodiment, described memory cell circuits can but be not limited to comprise:
Column decode circuitry, array decoding circuit, be connected the electric capacity between array decoding circuit and the ground;
Memory cell is a floating gate type metal-oxide-semiconductor memory spare, and the control grid connects described column decode circuitry, source ground, and drain electrode connects described first clamping circuit, the first electric current source generating circuit and described electric capacity by described array decoding circuit.
In the present embodiment, described memory cell, column decode circuitry, array decoding circuit and electric capacity choose and annexation can be with reference to the existing sense amplifier comparator circuit of reading; If the memory cell circuits of reading in the sense amplifier comparator circuit has other form, be applicable to present embodiment too.
In the present embodiment, described reference cell scheme can but be not limited to comprise:
Reference unit is a floating gate type metal-oxide-semiconductor memory spare, source ground, and the control grid connects the row reference voltage;
The column decoding pipe is a N-type metal-oxide-semiconductor, and source electrode links to each other with the drain electrode of described reference unit, and grid connects the row reference voltage, and drain electrode connects described second clamping circuit and the second electric current source generating circuit.
In the present embodiment, the value of the choosing of described reference unit, reference voltage can be with reference to the existing sense amplifier comparator circuit of reading; If the reference cell scheme of reading in the sense amplifier comparator circuit has other form, be applicable to present embodiment too.
In the present embodiment, described first clamping circuit can but be not limited to comprise:
First clamper tube, be used to described first clamper tube that first biasing circuit of bias voltage is provided.
In the present embodiment, described first clamper tube can but be not limited to a P type metal-oxide-semiconductor, the grid of this P type metal-oxide-semiconductor connects described first biasing circuit, and source electrode connects the output terminal of the described first electric current source generating circuit, and drain electrode connects the described first current conversion potential circuit.
In the present embodiment, described second clamping circuit can but be not limited to comprise:
Second clamper tube, be used to described second clamper tube that second biasing circuit of bias voltage is provided.
In the present embodiment, described second clamper tube can but be not limited to a P type metal-oxide-semiconductor, the grid of this P type metal-oxide-semiconductor connects described second biasing circuit, and source electrode connects the output terminal of the described second electric current source generating circuit, and drain electrode connects the described second current conversion potential circuit.
In the present embodiment, described the first/the second clamping circuit also can adopt other clamper element to realize, such as clamp diode etc., or adopts other circuit with clamper function to realize.
In the present embodiment, the described first current conversion potential circuit can but be not limited to first load that is connected between the drain electrode of described first clamper tube and the ground; The described second current conversion potential circuit can but be not limited to second load that is connected between the drain electrode of described second clamper tube and the ground.
During practical application, also can be that other can be element or the circuit of voltage with current conversion.
In the present embodiment, described first load can but be not limited to comprise the N-type metal-oxide-semiconductor of a diode type of attachment, the source ground of the N-type metal-oxide-semiconductor in this first load, drain and gate links to each other with the drain electrode of described first clamper tube.
In the present embodiment, described second load can but be not limited to comprise the N-type metal-oxide-semiconductor of a diode type of attachment, the source ground of the N-type metal-oxide-semiconductor in this second load, drain and gate links to each other with the drain electrode of described second clamper tube.
During practical application, described first, second load also can be resistance etc. other can be used as element or the circuit that load is used.
In the present embodiment, described first biasing circuit specifically can comprise:
A P type metal-oxide-semiconductor and a N-type metal-oxide-semiconductor, this P type metal-oxide-semiconductor is connected the grid of described first clamper tube with the common leak source of N-type metal-oxide-semiconductor;
The source electrode of described P type metal-oxide-semiconductor connects high level, and grid connects first bias voltage;
The source ground of described N-type metal-oxide-semiconductor, grid connect the source electrode of described first clamper tube.
In the present embodiment, described second biasing circuit specifically can comprise:
A P type metal-oxide-semiconductor and a N-type metal-oxide-semiconductor, this P type metal-oxide-semiconductor is connected the grid of described second clamper tube with the common leak source of N-type metal-oxide-semiconductor;
The source electrode of described P type metal-oxide-semiconductor connects high level, and grid connects second bias voltage;
The source ground of described N-type metal-oxide-semiconductor, grid connect the source electrode of described second clamper tube.
Wherein, first, second bias voltage in first, second biasing circuit can be identical or different.
First, second biasing circuit also can adopt other embodiment during practical application, and the load that is connected between voltage source and the ground such as employing to provide described bias voltage for described first, second clamper tube.
In the present embodiment, the realization of described clamping circuit, current conversion potential circuit can be with reference to the existing sense amplifier comparator circuit of reading; If read the sense amplifier comparator circuit other way of realization is arranged, be applicable to present embodiment too.
In the present embodiment, each can comprise described first, second electric current source generating circuit:
A P type metal-oxide-semiconductor, grid connects the 3rd bias voltage, and source electrode connects high level, and drain electrode is as output terminal.
Wherein, the 3rd bias voltage in first, second electric current source generating circuit can be identical or different.
Also other embodiment be can adopt during practical application, such as directly adopting a current source etc., can also load or other element be increased on the basis of P type metal-oxide-semiconductor.
In the present embodiment, described current comparison circuit can also comprise that one is used for providing the voltage source of described high level; Described high level is not limited to be produced by voltage source, also can be other external high level.
An object lesson of present embodiment comprises as shown in Figure 3: left and right sides two parts circuit and a comparator C; This comparator C comprises two input ends, an output terminal.
In the left-half circuit, memory cell circuits comprises drain terminal capacitor C BL2, column decode circuitry and the array decoding circuit of memory cell Mcell2, described memory cell.
Floating gate type metal-oxide-semiconductor memory spare Mcell2 represents a memory cell of being chosen by column decode circuitry and array decoding circuit, its source ground, the control grid connects column decode circuitry, reads voltage WL and is added in by column decode circuitry on the control grid of this memory cell Mcell2, produces electric current I cell; The drain electrode of this memory cell Mcell2 is connected to the drain electrode of P type metal-oxide-semiconductor MP9, the source electrode of P type metal-oxide-semiconductor MP5 and the grid of N-type metal-oxide-semiconductor MN7 by array decoding circuit; The drain voltage of this memory cell Mcell is BL.
Described P type metal-oxide-semiconductor MP9 source electrode connects voltage source V
DD, bias voltage Vpbias imports the grid of this P type metal-oxide-semiconductor MP9; This P type metal-oxide-semiconductor MP9 is as the first electric current source generating circuit, for the left-half circuit provides current source.
The voltage of the tie point of described array decoding circuit and P type metal-oxide-semiconductor MP9, MP5, N-type metal-oxide-semiconductor MN7 is sensebl; This tie point also is connected the end of the drain terminal capacitor C BL2 of described memory cell, the other end ground connection of this drain terminal capacitor C BL2.
Described P type metal-oxide-semiconductor MP5 is first clamper tube, its objective is voltage sensebl clamper between 0.8V～1.2V, to avoid drain stress (drain stress) effect of memory cell.The drain electrode of clamper tube MP5 links to each other with drain and gate as the N-type metal-oxide-semiconductor MN5 of load pipe, and grid links to each other with the drain electrode of described N-type metal-oxide-semiconductor MN7.
In first biasing circuit, described N-type metal-oxide-semiconductor MN7 is a feedback pipe, as first load, and its source ground, drain electrode also links to each other with the drain electrode of P type metal-oxide-semiconductor MP7, for generation of the required bias voltage Vfb of described clamper tube MP5, and provides feedback control loop for it.The grid of described P type metal-oxide-semiconductor MP7 connects bias voltage Vbias, and source electrode connects voltage source V
DD, be used to described feedback pipe MN7 that bias voltage is provided.
The source ground of described load pipe MN5, described electric current I cell is by described array decoding circuit, and clamper tube MP5, finally be applied to the diode form and be connected on the load pipe MN5 in the circuit, thereby grid and drain electrode at this load pipe MN5 produce voltage sain, as an input of described comparer; Obviously different memory cells produce different electric current I cell, thereby produce different comparative voltage sain.
In the right half part circuit, floating gate type metal-oxide-semiconductor memory spare Mref2 represents reference unit, is used for providing one can supply benchmark relatively, and row reference voltage Rowref is applied on the control grid of this N-type metal-oxide-semiconductor Mref, produces a reference current Iref.The source ground of this reference unit Mref2, drain electrode is connected to the source electrode of N-type metal-oxide-semiconductor Mcol2, and drain voltage is RBL.
Described N-type metal-oxide-semiconductor Mcol2 is the column decoding pipe, and voltage Colref is applied on the grid of this column decoding pipe Mcol2; The drain electrode of this column decoding pipe Mcol2 is connected to the drain electrode of P type metal-oxide-semiconductor MPl0, the source electrode of P type metal-oxide-semiconductor MP6 and the grid of N-type metal-oxide-semiconductor MN8; The voltage of this tie point is rsensebl.
The source electrode of described P type metal-oxide-semiconductor MP10 connects voltage source V
DD, reference bias voltage Vrefpbias imports the grid of this P type metal-oxide-semiconductor MP10, and this P type metal-oxide-semiconductor MP10 is as the second electric current source generating circuit, for the right half part circuit provides current source.
Described P type metal-oxide-semiconductor MP6 is second clamper tube, its objective is voltage rsensebl clamper between 0.8V～1.2V, to avoid drain stress effect.The drain electrode of clamper tube MP6 links to each other with drain and gate as the N-type metal-oxide-semiconductor MN6 of load pipe, and grid links to each other with the drain electrode of described N-type metal-oxide-semiconductor MN8.
In second biasing circuit, described N-type metal-oxide-semiconductor MN8 is a feedback pipe, as second load, and its source ground, drain electrode also links to each other with the drain electrode of P type metal-oxide-semiconductor MP8, for generation of the required bias voltage Vrfb of described clamper tube MN5.The grid of described P type metal-oxide-semiconductor MP8 connects bias voltage Vrefbias, and source electrode connects voltage source V
DD, be used to described feedback pipe MN8 that bias voltage is provided.
The source ground of described load pipe MN6, described electric current I ref is by described column decoding pipe Mcol2, and clamper tube MP6, finally be applied to the diode form and be connected on the load pipe MN6 in the circuit, thereby grid and drain electrode at this load pipe MN6 produce voltage sainref, as another input of described comparer.
Finally, described comparer comparative voltage sain and voltage sainref produce or 0 or 1 output signal SAout, thereby have finished the data read to memory cell.
Be not limited to adopt the physical circuit in the above-mentioned example during practical application.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of claim of the present invention.
Claims (12)
1. read the sense amplifier comparator circuit for one kind, comprising: comparer; Memory cell circuits, clamping circuit, first, second clamping circuit, first, second current conversion potential circuit;
It is characterized in that, also comprise:
The first electric current source generating circuit, output terminal connect described first clamping circuit and memory cell circuits;
The second electric current source generating circuit, output terminal connect described second clamping circuit and reference cell scheme;
The described first current conversion potential circuit be connected and first clamping circuit between, the described second current conversion potential circuit be connected and second clamping circuit between;
An input end of described comparer connects the tie point between the described first current conversion potential circuit and described first clamping circuit, and another input end connects the tie point of the described second current conversion potential circuit and described second clamping circuit.
2. the sense amplifier comparator circuit of reading as claimed in claim 1 is characterized in that, described first clamping circuit comprises:
First clamper tube, be used to described first clamper tube that first biasing circuit of bias voltage is provided;
Described first clamper tube is a P type metal-oxide-semiconductor, and the grid of this P type metal-oxide-semiconductor connects described first biasing circuit, and source electrode connects the output terminal of the described first electric current source generating circuit, and drain electrode connects the described first current conversion potential circuit.
3. the sense amplifier comparator circuit of reading as claimed in claim 2 is characterized in that, described first biasing circuit comprises:
A P type metal-oxide-semiconductor and a N-type metal-oxide-semiconductor, this P type metal-oxide-semiconductor is connected the grid of described first clamper tube with the common leak source of N-type metal-oxide-semiconductor;
The source electrode of described P type metal-oxide-semiconductor connects high level, and grid connects first bias voltage;
The source ground of described N-type metal-oxide-semiconductor, grid connect the source electrode of described first clamper tube.
4. the sense amplifier comparator circuit of reading as claimed in claim 2 is characterized in that:
The described first current conversion potential circuit is first load that is connected between described first clamper tube drain electrode and the ground.
5. the sense amplifier comparator circuit of reading as claimed in claim 4 is characterized in that:
Described first load comprises the N-type metal-oxide-semiconductor of a diode type of attachment; The source ground of the N-type metal-oxide-semiconductor in this first load, drain and gate links to each other with the drain electrode of described first clamper tube.
6. the sense amplifier comparator circuit of reading as claimed in claim 1 is characterized in that, described second clamping circuit comprises:
Second clamper tube, be used to described second clamper tube that second biasing circuit of bias voltage is provided;
Described second clamper tube is a P type metal-oxide-semiconductor, and the grid of this P type metal-oxide-semiconductor connects described second biasing circuit, and source electrode connects the output terminal of the described second electric current source generating circuit, and drain electrode connects the described second current conversion potential circuit.
7. the sense amplifier comparator circuit of reading as claimed in claim 6 is characterized in that, described second biasing circuit comprises:
A P type metal-oxide-semiconductor and a N-type metal-oxide-semiconductor, this P type metal-oxide-semiconductor is connected the grid of described second clamper tube with the common leak source of N-type metal-oxide-semiconductor;
The source electrode of described P type metal-oxide-semiconductor connects high level, and grid connects second bias voltage;
The source ground of described N-type metal-oxide-semiconductor, grid connect the source electrode of described second clamper tube.
8. the sense amplifier comparator circuit of reading as claimed in claim 6 is characterized in that:
The described second current conversion potential circuit is second load that is connected between described second clamper tube drain electrode and the ground.
9. the sense amplifier comparator circuit of reading as claimed in claim 8 is characterized in that:
Described second load comprises the N-type metal-oxide-semiconductor of a diode type of attachment; The source ground of the N-type metal-oxide-semiconductor in this second load, drain and gate links to each other with the drain electrode of described second clamper tube.
10. as each described sense amplifier comparator circuit of reading in the claim 1 to 9, it is characterized in that:
Described first clamping circuit is used for voltage clamper with the output terminal of the described first electric current source generating circuit between 0.8V～1.2V; Described second clamping circuit is used for voltage clamper with the output terminal of the described second electric current source generating circuit between 0.8V～1.2V.
11. as each described sense amplifier comparator circuit of reading in the claim 1 to 9, it is characterized in that described memory cell circuits comprises:
Column decode circuitry, array decoding circuit, be connected the electric capacity between array decoding circuit and the ground;
Memory cell is a floating gate type metal-oxide-semiconductor memory spare, and the control grid connects described column decode circuitry, source ground, and drain electrode connects described first clamping circuit, the first electric current source generating circuit and described electric capacity by described array decoding circuit;
Described reference cell scheme comprises:
Reference unit is a floating gate type metal-oxide-semiconductor memory spare, source ground, and the control grid connects the row reference voltage;
The column decoding pipe is a N-type metal-oxide-semiconductor, and source electrode links to each other with the drain electrode of described reference unit, and grid connects the row reference voltage, and drain electrode connects described second clamping circuit and the second electric current source generating circuit.
12. as each described sense amplifier comparator circuit of reading in the claim 1 to 9, it is characterized in that described first, second electric current source generating circuit respectively comprises:
A P type metal-oxide-semiconductor, grid connects the 3rd bias voltage, and source electrode connects voltage source, and drain electrode is as output terminal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210007613.9A CN103208300B (en) | 2012-01-11 | 2012-01-11 | A kind of reading sense amplifier comparison circuit |
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| CN201210007613.9A CN103208300B (en) | 2012-01-11 | 2012-01-11 | A kind of reading sense amplifier comparison circuit |
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| CN103208300A true CN103208300A (en) | 2013-07-17 |
| CN103208300B CN103208300B (en) | 2016-06-08 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110415739A (en) * | 2019-07-17 | 2019-11-05 | 上海华虹宏力半导体制造有限公司 | Charge transfer type sense amplifier and be applied to generating circuit from reference voltage therein |
| CN111462802A (en) * | 2019-01-22 | 2020-07-28 | 上海汉容微电子有限公司 | Reading circuit of NOR flash memory |
| CN115996044A (en) * | 2023-03-22 | 2023-04-21 | 江苏润石科技有限公司 | Fast comparator |
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| US20060152970A1 (en) * | 2005-01-12 | 2006-07-13 | International Business Machines Corporation | Method and apparatus for current sense amplifier calibration in mram devices |
| US20100008147A1 (en) * | 2004-06-29 | 2010-01-14 | Samsung Electronics Co., Ltd. | Sensing circuit for flash memory device operating at low power supply voltage |
| CN102117644A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院微电子研究所 | Readout circuit of storage |
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| US20100008147A1 (en) * | 2004-06-29 | 2010-01-14 | Samsung Electronics Co., Ltd. | Sensing circuit for flash memory device operating at low power supply voltage |
| US20060152970A1 (en) * | 2005-01-12 | 2006-07-13 | International Business Machines Corporation | Method and apparatus for current sense amplifier calibration in mram devices |
| CN102117644A (en) * | 2009-12-30 | 2011-07-06 | 中国科学院微电子研究所 | Readout circuit of storage |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111462802A (en) * | 2019-01-22 | 2020-07-28 | 上海汉容微电子有限公司 | Reading circuit of NOR flash memory |
| CN111462802B (en) * | 2019-01-22 | 2022-05-13 | 上海汉容微电子有限公司 | Reading circuit of NOR flash memory |
| CN110415739A (en) * | 2019-07-17 | 2019-11-05 | 上海华虹宏力半导体制造有限公司 | Charge transfer type sense amplifier and be applied to generating circuit from reference voltage therein |
| CN110415739B (en) * | 2019-07-17 | 2021-06-08 | 上海华虹宏力半导体制造有限公司 | Charge transfer type sensitive amplifier and reference voltage generating circuit applied to same |
| CN115996044A (en) * | 2023-03-22 | 2023-04-21 | 江苏润石科技有限公司 | Fast comparator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103208300B (en) | 2016-06-08 |
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