CN110415739A - Charge transfer type sense amplifier and be applied to generating circuit from reference voltage therein - Google Patents
Charge transfer type sense amplifier and be applied to generating circuit from reference voltage therein Download PDFInfo
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- CN110415739A CN110415739A CN201910644459.8A CN201910644459A CN110415739A CN 110415739 A CN110415739 A CN 110415739A CN 201910644459 A CN201910644459 A CN 201910644459A CN 110415739 A CN110415739 A CN 110415739A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/08—Control thereof
Abstract
The present invention relates to charge transfer type sense amplifiers, it is related to semiconductor integrated circuit design, by designing a generating circuit from reference voltage in charge transfer type sense amplifier, the received reference voltage VREFN of inverting input terminal to adjust the comparator in charge transfer type sense amplifier, making reference voltage VREFN no longer is fixed voltage, and declined in comparison phase reference voltage with certain slope, and it is close with the voltage descending slope of the voltage of E worst situation lower node VD and P worst situation lower node VD, and reference voltage VREFN is greater than the voltage of E worst situation lower node VD and is less than the voltage of P worst situation lower node VD, correct data can be read in the case where no strictly limitation by reading timing in this way, it will not be because of timing reasons And reference voltage VREFN voltage and reduce reading window, while being also improved the effect of reading rate.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit more particularly to a kind of charge transfer type sense amplifier and it is applied to
Generating circuit from reference voltage therein.
Background technique
Charge transfer type sense amplifier is the common circuit of semiconductor integrated circuit, referring to Fig. 1, Fig. 1 is existing skill
The circuit diagram of the charge transfer type sense amplifier of art, as shown in Figure 1, existing charge transfer type sense amplifier packet
Include: comparator 120, the inverting input terminal of comparator 120 receive reference voltage VREF, the normal phase input end connection of comparator 120
Column data line node VD, receives the voltage VD of column data line node VD, and the output end of comparator 120 is sensitive as charge transfer type
The output end of amplifier forms output signal DOUT by the comparison of VD and VREF；The grid of NMOS tube n0, NMOS tube n0 connect
Clamping voltag VCLAMP is received, and is kept it turned on, the source electrode of NMOS tube n0 is connected to bit line node BL, passes through bit line node BL
Memory cell 110 is connected, and memory cell 110 is grounded, the drain electrode of NMOS tube n0 connects column data line node VD；PMOS tube
The source electrode of p0, PMOS tube p0 connect supply voltage VDD, and the drain electrode of PMOS tube p0 connects the drain electrode of NMOS tube n0 and all connects together
The grid of column data line node VD, PMOS tube p0 receive control signal PBIAS, and PBIAS is a bias voltage.
Charge transfer type sense amplifier generally includes two stages of pre-charging stage and comparison phase.It is precharged first
Stage, VD voltage can be charged to supply voltage VDD, and then charge transfer type sense amplifier is carried out to memory cell 110
In comparison phase when reading: if memory cell 110 is r/w cell (Program cell, P cell), then memory list
Member 110 is not turned on, and theoretically the electric current of memory cell 110 is zero, and bit-line voltage is constant, and node BL voltage is constant, node VD
Voltage remains VDD, and the voltage of node VD is greater than reference voltage VREF, and the output signal DOUT of formation is 1；If memory list
Member is erasing unit (Erase cell, E cell), and memory cell 110 is connected, and memory cell 110 has electric current, bit line electricity
Pressure can decline, i.e. the VD voltage that node BL voltage can decline so as to cause the decline of VD voltage, after decline is less than reference voltage VREF,
The output signal DOUT of formation is 0, so completes to read data 1 and reads data 0.
Specifically, referring to Fig. 2, Fig. 2 be charge transfer type sense amplifier shown in FIG. 1 operation principle schematic diagram,
As shown in Fig. 2, include clk signal, and the triggering charge transfer type sense amplifier of the high level through clk signal is started to work, and
VD point voltage waveform including reading memory cell 110.It has read two clock cycle as shown in Figure 2, first clock cycle reads
Data 1 (P cell does not have electric current), second clock cycle read data 0 (E cell has electric current), and including reference voltage VREF wave
Shape, reference voltage VREF is a constant voltage values in the prior art, and each clock cycle includes the charging stage (when such as first
The charging stage d1 and the charging stage d3 in second clock period in clock period) and comparison phase (such as comparison of the first clock cycle
The rate of exchange stage d4 of stage d2 and second clock period), in charging stage d1 and d3, VD voltage is charged to supply voltage
VDD, in comparison phase, within first clock cycle, if memory cell 110 is r/w cell (Program cell, P
Cell), then memory cell 110 is not turned on, and theoretically the electric current of memory cell 110 is zero, and bit-line voltage is constant, node BL
Voltage is constant, and node VD voltage remains VDD, and the voltage of node VD is greater than reference voltage VREF, the output signal DOUT of formation
It is 1, that is, reads 1, however in actual operation, the electric current on memory cell is not theoretical 0A, and is commonly stored on device unit
Electric current be 0A to one between I1A value, the pressure drop when the electric current on memory cell is I1A thereon is greater than memory list
Pressure drop namely the decline of node VD voltage when electric current in member is 0A or more low current it is very fast, lead to partial region node VD
Voltage be less than reference voltage VREF, and 1 cannot be read correctly, relatively other P cell electricity in all P cell (not having electric current)
Flowing maximum label is worst, as shown in Fig. 2, and by electric current it is small be denoted as P good, memories such as all to reading
The data of unit must then complete reading movement before the t1 moment in such as Fig. 2.Within second clock cycle, if storage
Device unit 110 is erasing unit (Erase cell, E cell), and memory cell 110 is connected, theoretically memory cell 110
There is a current value such as I2A, bit-line voltage can decline, i.e. node BL voltage can decline so as to cause the decline of VD voltage, after decline
VD voltage be less than reference voltage VREF, the output signal DOUT of formation is 0, that is, reads 0, however in actual operation, memory
Electric current on unit is not theoretical I2A, and the electric current being commonly stored on device unit is I3A to a value between I2A, when depositing
The electric current that pressure drop when electric current on storage unit is I3A thereon is less than on memory cell is I2A or slightly bigger electric current
When pressure drop namely the decline of node VD voltage it is relatively slow, cause the voltage of partial region node VD to be greater than reference voltage VREF, and
It cannot be read correctly 0, relatively other the smallest labels of E cell electric current are worst, such as Fig. 2 in all E cell (having electric current)
It is shown, and then must be in such as Fig. 2 such as to the data for reading all memory cells by the big E good that is denoted as of electric current
The t2 moment after complete reading movement.
It reads function and needs to guarantee that E worst and P worst can be read correctly, therefore as shown in Fig. 2, in a cycle
P good and P worst are read correctly, need to read before p worst drops to VREF, that is, need t1 it
Preceding completion reading movement.E worst and E good are read correctly in second period, need to drop in E worst low
It is read again after VREF, that is, needs to complete reading movement after t 2, usual t2 is less than t1, namely must be in t2 between t1
Reading movement is completed, no person just will appear read error, so reduce the window (margin) for reading E/P, and consider voltage temperature
And the influence of process deviation, it is also higher to the requirement for reading timing.
Summary of the invention
The purpose of the present invention is to provide a kind of charge transfer type sense amplifiers, so that reading timing can be not stringent
Correct data is read in the case where limitation, will not reduce reading window because of timing reasons and reference voltage VREFN voltage.
Charge transfer type sense amplifier provided by the invention, comprising: the inverting input terminal of comparator, comparator receives ginseng
Voltage VREFN is examined, the normal phase input end of comparator connects column data line node VD, receives the voltage VD of column data line node VD,
Output end of the output end of comparator as charge transfer type sense amplifier forms output by the comparison of VD and VREFN
Signal DOUT；The grid of NMOS tube n0, NMOS tube n0 receive clamping voltag VCLAMP, and keep it turned on, NMOS tube n0's
Source electrode is connected to bit line node BL, and by bit line node BL connection memory cell, and memory cell is grounded；PMOS tube p0,
The source electrode of PMOS tube p0 connects supply voltage VDD, and the drain electrode of PMOS tube p0 connects the drain electrode of NMOS tube n0 and all connection arranges together
The grid of data line node VD, PMOS tube p0 receive control signal PBIAS；And generating circuit from reference voltage, for generating ginseng
Examine voltage VREFN, generating circuit from reference voltage includes PMOS tube p2, PMOS tube p1, NMOS tube n2 and NMOS tube n1, wherein PMOS
The source electrode of pipe p2 connects supply voltage VDD, the source electrode of the drain electrode connection PMOS tube p1 of PMOS tube p2, the drain electrode connection of PMOS tube p1
The drain electrode of NMOS tube n2, the drain electrode of the source electrode connection NMOS tube n1 of NMOS tube n2, the source electrode ground connection of NMOS tube n1, PMOS tube p2's
Grid receives voltage control signal SAENS, the drain electrode of the grid connection NMOS tube n2 of NMOS tube n2, the grid connection of NMOS tube n1
First voltage adjusts circuit, and the grid for receiving control voltage signal NBIAS, PMOS tube p1 that first voltage adjusts circuit output connects
It connects second voltage and adjusts circuit, receive the control voltage signal PBIAS that second voltage adjusts circuit output, wherein PMOS tube p1
The conode output reference voltage VREFN of drain electrode and the drain electrode of NMOS tube n2.
Further, first voltage adjusts circuit and is also connected with the first current source, and the first current source is used for first voltage
It adjusts circuit and one bias voltage is provided.
Further, second voltage adjusts circuit and is also connected with the second current source, and the second current source is used for second voltage
It adjusts circuit and one bias voltage is provided.
Further, first voltage adjusts circuit and adjusts the grid-control voltage signal NBIAS for being output to NMOS tube n1,
And then the electric current In1 for flowing through NMOS tube n1 is adjusted, second voltage adjusts circuit and adjusts the grid control electricity for being output to PMOS tube p1
Signal PBIAS is pressed, and then adjusts the electric current Ip1 for flowing through PMOS tube p1, and In1 is made to be greater than Ip1, makes reference voltage VREFN in electricity
With the decline of certain slope in the section after charging stage in the lotus transfevent sense amplifier course of work.
Further, In1 is slightly larger than Ip1.
Further, the slope of reference voltage VREFN signal decline can have multiple.
Further, in the clock cycle for reading data 0, memory cell is E cell, memory cell conducting, by institute
Having relatively other the smallest labels of E cell electric current in E cell is worst, and first voltage adjusts circuit adjusting and is output to
The grid-control voltage signal NBIAS of NMOS tube n1, and then the electric current In1 for flowing through NMOS tube n1 is adjusted, second voltage adjusts electricity
Road adjusts the grid-control voltage signal PBIAS for being output to PMOS tube p1, and then adjusts the electric current Ip1 for flowing through PMOS tube p1, makes
Reference voltage VREFN is declined in the section after the charging stage with certain slope, and reference voltage VREFN is greater than E worst
The voltage of situation lower node VD.
Further, the slope of reference voltage VREFN decline declines oblique with the voltage of E worst situation lower node VD
Rate is close.
Further, in the clock cycle for reading data 1, memory cell is P cell, and memory cell is not turned on, will
Relatively other maximum labels of P cell electric current are worst in all P cell, and first voltage adjusts circuit and adjusts output
To the grid-control voltage signal NBIAS of NMOS tube n1, and then the electric current In1 for flowing through NMOS tube n1 is adjusted, second voltage is adjusted
Circuit adjusts the grid-control voltage signal PBIAS for being output to PMOS tube p1, and then adjusts the electric current Ip1 for flowing through PMOS tube p1,
Make reference voltage VREFN in the section after the charging stage with the decline of certain slope, and reference voltage VREFN is less than P
The voltage of worst situation lower node VD.
Further, the slope of reference voltage VREFN decline declines oblique with the voltage of P worst situation lower node VD
Rate is close.
Further, in the clock cycle for reading data 0, memory cell is E cell, memory cell conducting, by institute
Having relatively other the smallest labels of E cell electric current in E cell is worst, in the clock cycle for reading data 1, memory list
Member is P cell, and memory cell is not turned on, and is by the maximum label of P cell electric currents relatively other in all P cell
Worst, first voltage adjusts circuit and adjusts the grid-control voltage signal NBIAS for being output to NMOS tube n1, and then adjusts and flow through
The electric current In1 of NMOS tube n1, second voltage adjust circuit and adjust the grid-control voltage signal PBIAS for being output to PMOS tube p1,
And then the electric current Ip1 for flowing through PMOS tube p1 is adjusted, make reference voltage VREFN in the charge transfer type sense amplifier course of work
Charging stage after section in the decline of certain slope, and reference voltage VREFN is greater than E worst situation lower node VD
Voltage and the voltage for being less than P worst situation lower node VD.
Further, by adjusting the electric current Ip1 of PMOS tube p1 is flowed through and the electricity of NMOS tube n1 is flowed through in comparison phase
The ratio I p1/In1 of In1 is flowed, the descending slope of reference voltage VREFN is adjusted.
Further, Ip1/In1 is bigger, then the descending slope of reference voltage VREFN is smaller, and Ip1/In1 is smaller, then joins
The descending slope for examining voltage VREFN is bigger.
Further, in the clock cycle for reading data 0, memory cell is E cell, memory cell conducting, by institute
Having relatively other the smallest labels of E cell electric current in E cell is worst, in the clock cycle for reading data 1, memory list
Member is P cell, and memory cell is not turned on, and is by the maximum label of P cell electric currents relatively other in all P cell
Worst adjusts Ip1/In1, makes the descending slope of reference voltage VREFN and the voltage and P of E worst situation lower node VD
The voltage descending slope of worst situation lower node VD is close, and reference voltage VREFN is made to be greater than E worst situation lower node
The voltage of VD and the voltage for being less than P worst situation lower node VD.
Further, the charge transfer type sense amplifier is integrated in semi-conductive substrate.
Further, the charge transfer type sense amplifier application CMOS technology is integrated in semi-conductive substrate.
The present invention also provides a kind of generating circuit from reference voltage of charge transfer type sense amplifier, for generating output to
The reference voltage VREFN of the inverting input terminal of comparator in charge transfer type sense amplifier, comprising: PMOS tube p2, PMOS
Pipe p1, NMOS tube n2 and NMOS tube n1, wherein the source electrode of PMOS tube p2 connects supply voltage VDD, the drain electrode connection of PMOS tube p2
The source electrode of PMOS tube p1, the drain electrode of the drain electrode connection NMOS tube n2 of PMOS tube p1, the source electrode connection NMOS tube n1's of NMOS tube n2
Drain electrode, the source electrode ground connection of NMOS tube n1, the grid of PMOS tube p2 receive voltage control signal SAENS, and the grid of NMOS tube n2 connects
The drain electrode of NMOS tube n2 is connect, the grid connection first voltage of NMOS tube n1 adjusts circuit, receives first voltage and adjust circuit output
Control voltage signal NBIAS, PMOS tube p1 grid connection second voltage adjust circuit, receive second voltage adjust circuit it is defeated
Control voltage signal PBIAS out, wherein the conode output reference voltage of the drain electrode of the drain electrode of PMOS tube p1 and NMOS tube n2
VREFN。
Further, first voltage adjusts circuit and adjusts the grid-control voltage signal NBIAS for being output to NMOS tube n1,
And then the electric current In1 for flowing through NMOS tube n1 is adjusted, second voltage adjusts circuit and adjusts the grid control electricity for being output to PMOS tube p1
Signal PBIAS is pressed, and then adjusts the electric current Ip1 for flowing through PMOS tube p1, and In1 is made to be greater than Ip1, makes reference voltage VREFN in electricity
With the decline of certain slope in the section after charging stage in the lotus transfevent sense amplifier course of work.
Further, reference voltage VREFN is greater than the voltage of E worst situation lower node VD and is less than P worst feelings
The voltage of condition lower node VD, wherein charge transfer type sense amplifier includes the memory for connecting the positive input of comparator
Unit, in the clock cycle for reading data 0, memory cell is E cell, and memory cell conducting will be opposite in all E cell
Other the smallest labels of E cell electric current are worst, and in the clock cycle for reading data 1, memory cell is P cell, storage
Device unit is not turned on, and is marked P cell electric currents relatively other in all P cell are maximum as worst.
Further, the voltage and Pworst of the descending slope of reference voltage VREFN and E worst situation lower node VD
The voltage descending slope of situation lower node VD is close.
Charge transfer type sense amplifier provided by the invention, by designing a ginseng in charge transfer type sense amplifier
Voltage generation circuit is examined, the received reference voltage of the inverting input terminal to adjust the comparator in charge transfer type sense amplifier
VREFN, making reference voltage VREFN no longer is fixed voltage, and is declined in comparison phase reference voltage with certain slope, and with
The voltage of E worst situation lower node VD and the voltage descending slope of P worst situation lower node VD are close, and reference voltage
Voltage of the VREFN greater than E worst situation lower node VD and the voltage for being less than P worst situation lower node VD, in this way reading timing
Correct data can be read in the case where no strictly limitation, it will not be because of timing reasons and reference voltage VREFN electricity
It presses and reduces reading window (margin), while being also improved the effect of reading rate.
Detailed description of the invention
Fig. 1 is the circuit diagram of the charge transfer type sense amplifier of the prior art.
Fig. 2 is the operation principle schematic diagram of charge transfer type sense amplifier shown in FIG. 1.
Fig. 3 is the schematic diagram of the charge transfer type sense amplifier of one embodiment of the invention.
Fig. 4 is the operation principle schematic diagram of the charge transfer type sense amplifier of one embodiment of the invention shown in Fig. 3.
Label used in attached drawing is explained as follows:
210, memory cell；220, comparator；230, generating circuit from reference voltage；231, first voltage adjusts circuit；
232, second voltage adjusts circuit；233, the first current source；234, the second current source.
Specific embodiment
Below in conjunction with attached drawing, clear, complete description is carried out to the technical solution in the present invention, it is clear that described
Embodiment is a part of the embodiments of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is general
Logical technical staff's all other embodiment obtained under the premise of not making creative work belongs to what the present invention protected
Range.
In an embodiment of the present invention, a kind of charge transfer type sense amplifier is provided.Specifically, referring to Fig. 3, Fig. 3
For the schematic diagram of the charge transfer type sense amplifier of one embodiment of the invention.As shown in figure 3, charge transfer type sense amplifier
It include: comparator 220, the inverting input terminal of comparator 220 receives reference voltage VREFN, and the normal phase input end of comparator 220 connects
Column data line node VD is met, receives the voltage VD of column data line node VD, the output end of comparator 220 is as charge transfer type spirit
The output end of quick amplifier forms output signal DOUT by the comparison of VD and VREFN；NMOS tube n0, the grid of NMOS tube n0
Pole receives clamping voltag VCLAMP, and keeps it turned on, and the source electrode of NMOS tube n0 is connected to bit line node BL, passes through bit line section
Point BL connection memory cell 210, and memory cell 210 is grounded；The source electrode of PMOS tube p0, PMOS tube p0 connect supply voltage
The drain electrode of the drain electrode connection NMOS tube n0 of VDD, PMOS tube p0 and together all connection column data line node VD, the grid of PMOS tube p0
Receive control signal PBIAS；Generating circuit from reference voltage 230 is further included, for generating reference voltage VREFN, reference voltage is produced
Raw circuit 230 includes PMOS tube p2, PMOS tube p1, NMOS tube n2 and NMOS tube n1, and wherein the source electrode of PMOS tube p2 connects power supply
The source electrode of the drain electrode connection PMOS tube p1 of voltage VDD, PMOS tube p2, the drain electrode of the drain electrode connection NMOS tube n2 of PMOS tube p1,
The drain electrode of the source electrode connection NMOS tube n1 of NMOS tube n2, the source electrode ground connection of NMOS tube n1, the grid of PMOS tube p2 receive voltage control
The grid connection first voltage of the drain electrode of the grid connection NMOS tube n2 of signal SAENS processed, NMOS tube n2, NMOS tube n1 adjusts electricity
Road 231 receives the second electricity of grid connection that first voltage adjusts control voltage signal NBIAS, PMOS tube p1 that circuit 231 exports
Voltage regulator circuit 232 receives second voltage and adjusts the control voltage signal PBIAS that circuit 232 exports, the wherein leakage of PMOS tube p1
The conode output reference voltage VREFN of the drain electrode of pole and NMOS tube n2.
In an embodiment of the present invention, referring again to Fig. 3, first voltage adjusts circuit 231 and is also connected with the first current source
233, the first current source 233, which is used to adjust circuit 231 to first voltage, provides a bias voltage.Likewise, second voltage is adjusted
Circuit 232 is also connected with the second current source 234, and the second current source 234, which is used to adjust circuit 232 to second voltage, provides a biased electrical
Pressure.
In an embodiment of the present invention, first voltage adjusts circuit 231 and adjusts the grid control electricity for being output to NMOS tube n1
Signal NBIAS is pressed, and then adjusts the electric current In1 for flowing through NMOS tube n1, second voltage adjusts the adjusting of circuit 232 and is output to PMOS tube
The grid-control voltage signal PBIAS of p1, and then the electric current Ip1 for flowing through PMOS tube p1 is adjusted, and In1 is made to be greater than Ip1, make to refer to
Voltage VREFN is in the section after the charging stage in the charge transfer type sense amplifier course of work under certain slope
Drop.More specifically, in an embodiment of the present invention, In1 is slightly larger than Ip1.In an embodiment of the present invention, reference voltage VREFN
Signal decline slope can have it is multiple, as long as its overall trend be decline.Namely charge transfer type provided by the invention
The received reference voltage VREFN of the inverting input terminal of the comparator 220 of sense amplifier is not as in the prior art one is constant
Value.Fig. 4 is specifically seen, Fig. 4 is that the work of the charge transfer type sense amplifier of one embodiment of the invention shown in Fig. 3 is former
Schematic diagram is managed, as shown in figure 4, including clk signal, and the triggering charge transfer type sense amplifier of the high level through clk signal is opened
Beginning work, and the voltage waveform including column data line node VD point.It has read two clock cycle as shown in Figure 4, first clock
Period reads data 0 (E cell has electric current), and second clock cycle reads data 1 (P cell does not have electric current), and including reference voltage
VREFN waveform, reference voltage VREFN is not a constant voltage values in the present invention, each clock cycle include the charging stage (such as
The charging stage d1 and the charging stage d3 in second clock period of first clock cycle) and comparison phase (such as the first clock cycle
Comparison phase d2 and the rate of exchange stage d4 in second clock period), in charging stage d1 and d3, VD voltage is charged to power supply
Voltage VDD, in comparison phase, within first clock cycle, if memory cell 110 is erasing unit (Erase
Cell, E cell), memory cell 110 is connected, and it is the same as described in Figure 2, in actual operation, by all E cell
The VD voltage of relatively other the smallest E cell of E cell electric current is labeled as E worst in (having electric current), as shown in figure 4, and will
The VD voltage of the big E cell of electric current is denoted as E good, and first voltage adjusts circuit 231 and adjusts the grid for being output to NMOS tube n1
Pole controls voltage signal NBIAS, and then adjusts the electric current In1 for flowing through NMOS tube n1, and second voltage adjusts circuit 232 and adjusts output
To the grid-control voltage signal PBIAS of PMOS tube p1, and then the electric current Ip1 for flowing through PMOS tube p1 is adjusted, makes reference voltage
VREFN in the section after the charging stage with certain slope decline, and reference voltage VREFN be greater than E worst in the case of save
The voltage of point VD, and it can be read correctly 0, more preferably, the slope and E worst situation lower node VD of reference voltage VREFN decline
Voltage decline slope it is close.Within second clock cycle, if memory cell 210 is r/w cell (Program
Cell, P cell), then memory cell 210 is not turned on, and it is the same as described in Figure 2, in actual operation, by all P
The VD voltage mark of relatively other maximum P cell of P cell electric current is labeled as P worst in cell (without electric current), such as Fig. 4 institute
Show, and the VD voltage of the small P cell of electric current is labeled as P good, and first voltage adjusts the adjusting of circuit 231 and is output to NMOS
The grid-control voltage signal NBIAS of pipe n1, and then the electric current In1 for flowing through NMOS tube n1 is adjusted, second voltage adjusts circuit 232
The grid-control voltage signal PBIAS for being output to PMOS tube p1 is adjusted, and then adjusts the electric current Ip1 for flowing through PMOS tube p1, makes to join
Voltage VREFN is examined with the decline of certain slope in the section after the charging stage, and reference voltage VREFN is less than Pworst situation
The voltage of lower node VD, and 1 can be read correctly.More preferably, the slope and Pworst situation lower node of reference voltage VREFN decline
The slope of the voltage decline of VD is close.
Further, first voltage adjusts circuit 231 and adjusts the grid-control voltage signal for being output to NMOS tube n1
NBIAS, and then the electric current In1 for flowing through NMOS tube n1 is adjusted, second voltage adjusts circuit 232 and adjusts the grid for being output to PMOS tube p1
Pole controls voltage signal PBIAS, and then adjusts the electric current Ip1 for flowing through PMOS tube p1, makes reference voltage VREFN in charge transfer type
With the decline of certain slope in the section after charging stage in the sense amplifier course of work, and reference voltage VREFN is greater than E
The voltage of worst situation lower node VD and the voltage for being less than P worst situation lower node VD, can read all memory cells
210 data, without the case where can not reading.
Specifically, by adjusting the electric current Ip1 of PMOS tube p1 is flowed through and flowing through the electric current In1 of NMOS tube n1 in comparison phase
Ratio I p1/In1, adjust reference voltage VREFN descending slope.Specifically, Ip1/In1 is bigger, then reference voltage VREFN
Descending slope it is smaller, Ip1/In1 is smaller, then the descending slope of reference voltage VREFN is bigger.In the present invention, Ip1/ is adjusted
In1 makes the descending slope of reference voltage VREFN and the voltage of E worst situation lower node VD and Pworst situation lower node VD
Voltage descending slope it is close, and make voltage of the reference voltage VREFN greater than E worst situation lower node VD and be less than P
The voltage of worst situation lower node VD.
In an embodiment of the present invention, first voltage adjusts circuit 231 and second voltage adjusts circuit 232 and can appoint for industry
Voltage regulator circuit known to what or any circuit that may be implemented to adjust the function of voltage, the present invention do not do specific limit to it
It is fixed.
As noted previously, as reference voltage VREFN is no longer fixed voltage, in comparison phase reference voltage with certain oblique
Rate decline, and it is close with the voltage descending slope of the voltage of E worst situation lower node VD and P worst situation lower node VD,
And reference voltage VREFN is greater than the voltage of E worst situation lower node VD and is less than the voltage of P worst situation lower node VD,
Correct data can be read in the case where no strictly limitation by reading timing in this way, will not be because of timing reasons and with reference to electricity
It presses VREFN voltage and reduces reading window (margin), while being also improved the effect of reading rate.
In an embodiment of the present invention, the charge transfer type sense amplifier is integrated in semi-conductive substrate.More
Body, in an embodiment of the present invention, the charge transfer type sense amplifier application CMOS technology is integrated in semiconductor lining
On bottom.
In an alternative embodiment of the invention, the reference voltage for also providing a kind of charge transfer type sense amplifier generates electricity
Road.Specifically can be referring again to Fig. 3, generating circuit from reference voltage 230 is for generating output in charge transfer type sense amplifier
Comparator inverting input terminal reference voltage VREFN, generating circuit from reference voltage 230 include PMOS tube p2, PMOS tube p1,
NMOS tube n2 and NMOS tube n1, wherein the source electrode of PMOS tube p2 connects supply voltage VDD, and the drain electrode of PMOS tube p2 connects PMOS tube
The source electrode of p1, the drain electrode of the drain electrode connection NMOS tube n2 of PMOS tube p1, the drain electrode of the source electrode connection NMOS tube n1 of NMOS tube n2,
The source electrode of NMOS tube n1 is grounded, and the grid of PMOS tube p2 receives voltage control signal SAENS, and the grid of NMOS tube n2 connects NMOS
The grid connection first voltage of the drain electrode of pipe n2, NMOS tube n1 adjusts circuit 231, receives first voltage and adjusts the output of circuit 231
Control voltage signal NBIAS, PMOS tube p1 grid connection second voltage adjust circuit 232, receive second voltage adjust electricity
The control voltage signal PBIAS that road 232 exports, wherein the conode of the drain electrode of PMOS tube p1 and the drain electrode of NMOS tube n2, which exports, joins
Examine voltage VREFN.
In an embodiment of the present invention, first voltage adjusts circuit 231 and adjusts the grid control electricity for being output to NMOS tube n1
Signal NBIAS is pressed, and then adjusts the electric current In1 for flowing through NMOS tube n1, second voltage adjusts the adjusting of circuit 232 and is output to PMOS tube
The grid-control voltage signal PBIAS of p1, and then the electric current Ip1 for flowing through PMOS tube p1 is adjusted, and In1 is made to be greater than Ip1, make to refer to
Voltage VREFN is in the section after the charging stage in the charge transfer type sense amplifier course of work under certain slope
Drop.Further, reference voltage VREFN greater than E worst situation lower node VD voltage and be less than P worst in the case of save
The voltage of point VD, wherein charge transfer type sense amplifier includes the memory cell for connecting the positive input of comparator
210, in the clock cycle for reading data 0, memory cell is E cell, and memory cell conducting will be opposite in all E cell
Other the smallest labels of E cell electric current are worst, and in the clock cycle for reading data 1, memory cell is P cell, storage
Device unit is not turned on, and is marked P cell electric currents relatively other in all P cell are maximum as worst.And further
, the electricity of the descending slope of reference voltage VREFN and the voltage of Eworst situation lower node VD and P worst situation lower node VD
It is close to depress drop angle rate.
In conclusion by designing a generating circuit from reference voltage in charge transfer type sense amplifier, to adjust electricity
The received reference voltage VREFN of the inverting input terminal of comparator in lotus transfevent sense amplifier, makes reference voltage VREFN not
It is fixed voltage again, and is declined in comparison phase reference voltage with certain slope, and the electricity with E worst situation lower node VD
The voltage descending slope of pressure and P worst situation lower node VD are close, and reference voltage VREFN be greater than E worst in the case of save
The voltage of point VD and the voltage for being less than P worst situation lower node VD, reading timing in this way can be in the feelings not limited strictly
Correct data is read under condition, reading window (margin) will not be reduced because of timing reasons and reference voltage VREFN voltage, together
When be also improved the effect of reading rate.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (20)
1. a kind of charge transfer type sense amplifier characterized by comprising
Comparator, the inverting input terminal of comparator receive reference voltage VREFN, and the normal phase input end of comparator connects column data line
Node VD receives the voltage VD of column data line node VD, and the output end of comparator is as the defeated of charge transfer type sense amplifier
Outlet forms output signal DOUT by the comparison of VD and VREFN；
The grid of NMOS tube n0, NMOS tube n0 receive clamping voltag VCLAMP, and keep it turned on, and the source electrode of NMOS tube n0 connects
It is connected to bit line node BL, by bit line node BL connection memory cell, and memory cell is grounded；
The source electrode of PMOS tube p0, PMOS tube p0 connects supply voltage VDD, the drain electrode of the drain electrode connection NMOS tube n0 of PMOS tube p0 and
Column data line node VD is all connected together, and the grid of PMOS tube p0 receives control signal PBIAS；And
Generating circuit from reference voltage, for generating reference voltage VREFN, generating circuit from reference voltage includes PMOS tube p2, PMOS
Pipe p1, NMOS tube n2 and NMOS tube n1, wherein the source electrode of PMOS tube p2 connects supply voltage VDD, the drain electrode connection of PMOS tube p2
The source electrode of PMOS tube p1, the drain electrode of the drain electrode connection NMOS tube n2 of PMOS tube p1, the source electrode connection NMOS tube n1's of NMOS tube n2
Drain electrode, the source electrode ground connection of NMOS tube n1, the grid of PMOS tube p2 receive voltage control signal SAENS, and the grid of NMOS tube n2 connects
The drain electrode of NMOS tube n2 is connect, the grid connection first voltage of NMOS tube n1 adjusts circuit, receives first voltage and adjust circuit output
Control voltage signal NBIAS, PMOS tube p1 grid connection second voltage adjust circuit, receive second voltage adjust circuit it is defeated
Control voltage signal PBIAS out, wherein the conode output reference voltage of the drain electrode of the drain electrode of PMOS tube p1 and NMOS tube n2
VREFN。
2. charge transfer type sense amplifier according to claim 1, which is characterized in that first voltage adjusts circuit and also connects
The first current source is connect, the first current source, which is used to adjust circuit to first voltage, provides a bias voltage.
3. charge transfer type sense amplifier according to claim 1, which is characterized in that second voltage adjusts circuit and also connects
The second current source is connect, the second current source, which is used to adjust circuit to second voltage, provides a bias voltage.
4. charge transfer type sense amplifier according to claim 1, which is characterized in that first voltage adjusts circuit and adjusts
It is output to the grid-control voltage signal NBIAS of NMOS tube n1, and then adjusts the electric current In1 for flowing through NMOS tube n1, second voltage
It adjusts circuit and adjusts the grid-control voltage signal PBIAS for being output to PMOS tube p1, and then adjust the electric current for flowing through PMOS tube p1
Ip1, and In1 is made to be greater than Ip1, make charging stage of the reference voltage VREFN in the charge transfer type sense amplifier course of work
With the decline of certain slope in section later.
5. charge transfer type sense amplifier according to claim 4, which is characterized in that In1 is slightly larger than Ip1.
6. charge transfer type sense amplifier according to claim 4, which is characterized in that under reference voltage VREFN signal
The slope of drop can have multiple.
7. charge transfer type sense amplifier according to claim 4, which is characterized in that read data 0 clock cycle,
Memory cell is E cell, memory cell conducting, by the smallest labels of E cell electric current relatively other in all E cell
For E worst, and first voltage adjusts circuit and adjusts the grid-control voltage signal NBIAS for being output to NMOS tube n1, and then adjusts
The electric current In1 of the NMOS tube that throttled n1, second voltage adjust circuit and adjust the grid-control voltage signal for being output to PMOS tube p1
PBIAS, and then the electric current Ip1 for flowing through PMOS tube p1 is adjusted, make reference voltage VREFN in the section after the charging stage with one
Determine slope decline, and reference voltage VREFN is greater than the voltage of E worst situation lower node VD.
8. charge transfer type sense amplifier according to claim 7, which is characterized in that reference voltage VREFN decline
The slope that the voltage of slope and E worst situation lower node VD decline is close.
9. charge transfer type sense amplifier according to claim 4, which is characterized in that read data 1 clock cycle,
Memory cell is P cell, and memory cell is not turned on, by the maximum marks of P cell electric current relatively other in all P cell
It is denoted as P worst, and first voltage adjusts circuit and adjusts the grid-control voltage signal NBIAS for being output to NMOS tube n1, in turn
The electric current In1 for flowing through NMOS tube n1 is adjusted, second voltage adjusts circuit and adjusts the grid-control voltage letter for being output to PMOS tube p1
Number PBIAS, and then adjust the electric current Ip1 for flowing through PMOS tube p1, make reference voltage VREFN in the section after the charging stage with
Certain slope decline, and reference voltage VREFN is less than the voltage of P worst situation lower node VD.
10. charge transfer type sense amplifier according to claim 9, which is characterized in that reference voltage VREFN decline
The slope that the voltage of slope and P worst situation lower node VD decline is close.
11. charge transfer type sense amplifier according to claim 4, which is characterized in that in the clock week for reading data 0
Phase, memory cell are E cell, memory cell conducting, by the smallest marks of E cell electric current relatively other in all E cell
It is denoted as E worst, in the clock cycle for reading data 1, memory cell is P cell, and memory cell is not turned on, by all P
Relatively other maximum labels of P cell electric current are worst in cell, and first voltage adjusts circuit adjusting and is output to NMOS tube
The grid-control voltage signal NBIAS of n1, and then the electric current In1 for flowing through NMOS tube n1 is adjusted, second voltage adjusts circuit and adjusts
It is output to the grid-control voltage signal PBIAS of PMOS tube p1, and then adjusts the electric current Ip1 for flowing through PMOS tube p1, is made with reference to electricity
VREFN is pressed to decline in the section after the charging stage in the charge transfer type sense amplifier course of work with certain slope,
And reference voltage VREFN is greater than the voltage of E worst situation lower node VD and is less than the voltage of P worst situation lower node VD.
12. charge transfer type sense amplifier according to claim 4, which is characterized in that comparison phase by adjusting
It flows through the electric current Ip1 of PMOS tube p1 and flows through the ratio I p1/In1 of the electric current In1 of NMOS tube n1, adjustment reference voltage VREFN's
Descending slope.
13. charge transfer type sense amplifier according to claim 12, which is characterized in that Ip1/In1 is bigger, then refers to
The descending slope of voltage VREFN is smaller, and Ip1/In1 is smaller, then the descending slope of reference voltage VREFN is bigger.
14. charge transfer type sense amplifier according to claim 12, which is characterized in that in the clock week for reading data 0
Phase, memory cell are E cell, memory cell conducting, by the smallest marks of E cell electric current relatively other in all E cell
It is denoted as E worst, in the clock cycle for reading data 1, memory cell is P cell, and memory cell is not turned on, by all P
Relatively other maximum labels of P cell electric current are worst in cell, adjust Ip1/In1, make the decline of reference voltage VREFN
The voltage descending slope of the voltage and P worst situation lower node VD of slope and E worst situation lower node VD is close, and makes
Voltage of the reference voltage VREFN greater than E worst situation lower node VD and the voltage for being less than P worst situation lower node VD.
15. charge transfer type sense amplifier according to claim 1, which is characterized in that the charge transfer type is sensitive
Amplifier is integrated in semi-conductive substrate.
16. charge transfer type sense amplifier according to claim 1, which is characterized in that the charge transfer type is sensitive
Amplifier application CMOS technology is integrated in semi-conductive substrate.
17. a kind of generating circuit from reference voltage of charge transfer type sense amplifier, for generating output to charge transfer type spirit
The reference voltage VREFN of the inverting input terminal of comparator in quick amplifier characterized by comprising PMOS tube p2, PMOS tube
P1, NMOS tube n2 and NMOS tube n1, wherein the source electrode of PMOS tube p2 connects supply voltage VDD, the drain electrode connection of PMOS tube p2
The source electrode of PMOS tube p1, the drain electrode of the drain electrode connection NMOS tube n2 of PMOS tube p1, the source electrode connection NMOS tube n1's of NMOS tube n2
Drain electrode, the source electrode ground connection of NMOS tube n1, the grid of PMOS tube p2 receive voltage control signal SAENS, and the grid of NMOS tube n2 connects
The drain electrode of NMOS tube n2 is connect, the grid connection first voltage of NMOS tube n1 adjusts circuit, receives first voltage and adjust circuit output
Control voltage signal NBIAS, PMOS tube p1 grid connection second voltage adjust circuit, receive second voltage adjust circuit it is defeated
Control voltage signal PBIAS out, wherein the conode output reference voltage of the drain electrode of the drain electrode of PMOS tube p1 and NMOS tube n2
VREFN。
18. generating circuit from reference voltage according to claim 17, which is characterized in that it is defeated that first voltage adjusts circuit adjusting
The grid-control voltage signal NBIAS of NMOS tube n1 is arrived out, and then adjusts the electric current In1 for flowing through NMOS tube n1, second voltage tune
Economize on electricity road adjusts the grid-control voltage signal PBIAS for being output to PMOS tube p1, and then adjusts the electric current for flowing through PMOS tube p1
Ip1, and In1 is made to be greater than Ip1, make charging stage of the reference voltage VREFN in the charge transfer type sense amplifier course of work
With the decline of certain slope in section later.
19. generating circuit from reference voltage according to claim 18, which is characterized in that reference voltage VREFN is greater than E
The voltage of worst situation lower node VD and the voltage for being less than P worst situation lower node VD, wherein charge transfer type is sensitive to be put
Big device includes the memory cell for connecting the positive input of comparator, in the clock cycle for reading data 0, memory cell E
Cell, memory cell conducting are marked E cell electric currents relatively other in all E cell are the smallest as worst, are being read
The clock cycle of data 1, memory cell are P cell, and memory cell is not turned on, by P relatively other in all P cell
The maximum label of cell electric current is worst.
20. generating circuit from reference voltage according to claim 19, which is characterized in that the lower drop angle of reference voltage VREFN
The voltage descending slope of the voltage and P worst situation lower node VD of rate and E worst situation lower node VD is close.
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| CN201910644459.8A CN110415739B (en) | 2019-07-17 | 2019-07-17 | Charge transfer type sensitive amplifier and reference voltage generating circuit applied to same |
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| CN110415739B (en) | 2021-06-08 |
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