CN103825567A - Operational amplifier circuit - Google Patents

Abstract

An operational amplifier circuit includes an output stage circuit. The output stage circuit includes an output transistor pair, a capacitance unit, and a switching unit. The drain of the first output transistor of the output transistor pair is coupled to the drain of the second output transistor of the output transistor pair via the output terminal of the output stage circuit. The switch unit is coupled between the gates of the first and second output transistors and coupled to the first end of the capacitor unit. The second terminal of the capacitor unit is coupled to the output terminal of the output stage circuit. The switch unit determines to conduct a signal transmission path between the grid of the first output transistor and the first end of the capacitor unit or to conduct a signal transmission path between the grid of the second output transistor and the first end of the capacitor unit according to the control signal.

Description

Operational Amplifier Circuit

technical field

The present invention relates to a load driving circuit, and in particular to an operational amplifier circuit.

Background technique

Operational amplifiers play a very important role in integrated circuit design, and are widely used in high-fidelity stereo equipment, microcomputers and other electronic equipment. One of the functions of the operational amplifier is to enhance the driving capability of the output signal to drive the load or the next stage circuit.

FIG. 1 is a schematic diagram of a known digitally controlled analog voltage driving circuit. Please refer to FIG. 1 , the driving circuit 100 includes a digital to analog converter 110 (digital to analog converter, DAC) and an operational amplifier 120 . The digital-to-analog converter 110 is used to receive a digital signal SD, convert the received digital signal SD into an analog signal SA, and then output the analog signal SA to the operational amplifier 120 . In this example, the operational amplifier 120 is in a negative feedback configuration with unity gain. When the operational amplifier 120 receives different input voltages, its output will produce different voltage changes. The speed of this change is called the slew rate (slew rate), and its value depends on the input stage current of the operational amplifier 120 and the size of the compensation capacitor. .

Specifically, in the application of digitally controlled analog voltage driving circuit, the output stage circuit of the operational amplifier 120 usually includes a plurality of compensation capacitors to enhance the stability of the operational amplifier 120 . Taking the 8-bit digital signal SD as an example, according to the most significant bits (MSB) of the digital signal SD, the output range of the digital-to-analog converter 110 can be roughly divided into two parts. FIG. 2 is a schematic diagram illustrating a comparison of digital signals corresponding to output ranges of the digital-to-analog converter 110 . Please refer to FIG. 2 , in the range where the most significant bit of the digital signal SD is 1 (MSB=1), the corresponding voltage range is roughly the high potential output V2 to V3. In the range where the most significant bit of the digital signal SD is 0 (MSB=0), the corresponding voltage range is roughly the low potential output V1 to V2. Therefore, in order to cope with this digital control method, two capacitors are generally designed inside the output stage circuit of the operational amplifier 120 to compensate for its stability. One of the capacitors is responsible for compensating the high potential output of the DAC 110 , and the other capacitor is responsible for compensating the low potential output of the DAC 110 .

In this design, the compensation capacitor usually occupies too much area in the chip. However, reducing the compensation capacitor in order to increase the slew rate will cause the operational amplifier to oscillate. Therefore, how to design an appropriate capacitance compensation structure in the output stage circuit of the operational amplifier is one of the important issues.

Contents of the invention

The invention provides an operational amplifier circuit, which uses a control signal to switch the compensation capacitance of its output stage circuit to different output transistors.

The invention provides an operational amplifier circuit, which includes an input stage circuit, a bias voltage circuit and an output stage circuit. The input stage circuit has an input terminal for receiving an input signal. The bias circuit is coupled to the input stage circuit for providing bias current to the input stage circuit. The output stage circuit is coupled to the bias circuit. The output stage circuit has an output. The output stage circuit includes an output transistor pair, a capacitor unit and a switch unit. The output transistor pair includes a first output transistor and a second output transistor. The first source/drain of the first output transistor is coupled to the first source/drain of the second output transistor via the output terminal. The capacitor unit has a first end and a second end. The second end of the capacitor unit is coupled to the output end of the output stage circuit. The switch unit is coupled between the gates of the first and second output transistors, and coupled to the first end of the capacitor unit. The switch unit decides to turn on the signal transmission path between the gate of the first output transistor and the first terminal of the capacitor unit, or to turn on the signal transmission path between the gate of the second output transistor and the first terminal of the capacitor unit according to the control signal. signal transmission path.

In an embodiment of the present invention, the above-mentioned capacitor unit includes a first capacitor. The first capacitor has a first terminal and a second terminal. The first terminal of the first capacitor is coupled to the first terminal of the capacitance unit, and the second terminal of the first capacitor is coupled to the second terminal of the capacitance unit.

In an embodiment of the present invention, the above-mentioned switch unit includes a first switch and a second switch. The first switch has a first terminal, a second terminal and a control terminal. The first terminal of the first switch is coupled to the gate of the first output transistor, the second terminal of the first switch is coupled to the first terminal of the first capacitor, and the control terminal of the first switch is controlled by an inverted control signal . The second switch has a first terminal, a second terminal and a control terminal. The second terminal of the second switch is coupled to the gate of the second output transistor, the first terminal of the second switch is coupled to the first terminal of the first capacitor, and the control terminal of the second switch is controlled by the control signal.

In an embodiment of the present invention, when the first switch turns on the signal transmission path between the gate of the first output transistor and the first terminal of the first capacitor, the second switch turns off the gate of the second output transistor and the signal transmission path between the first end of the first capacitor. When the second switch turns on the signal transmission path between the gate of the second output transistor and the first end of the first capacitor, the first switch turns off the connection between the gate of the first output transistor and the first end of the first capacitor. signal transmission path between them.

In an embodiment of the present invention, the above-mentioned capacitor unit includes a plurality of second capacitors. Each second capacitor has a first end and a second end. The first terminal of each second capacitor is coupled to the first terminal of the capacitor unit, and the second terminal of each second capacitor is coupled to the second terminal of the capacitor unit.

In an embodiment of the present invention, the above-mentioned switch unit includes a plurality of third switches and a plurality of fourth switches. Each third switch has a first terminal, a second terminal and a control terminal. The first terminal of each third switch is coupled to the gate of the first output transistor, the second terminal of each third switch is coupled to the first terminal of a different second capacitor, and the control terminal of each third switch is controlled by Inverted control signal. Each fourth switch has a first terminal, a second terminal and a control terminal. The second terminal of each fourth switch is coupled to the gate of the second output transistor, the first terminal of each fourth switch is coupled to the first terminal of a different second capacitor, and the control terminal of each fourth switch is controlled by control signal.

In an embodiment of the present invention, when each third switch turns on the signal transmission path between the gate of the first output transistor and the first end of each second capacitor, each fourth switch turns off the second output transistor The signal transmission path between the gate of the second capacitor and the first end of each second capacitor. When each fourth switch turns on the signal transmission path between the gate of the second output transistor and the first end of each second capacitor, each third switch disconnects the gate of the first output transistor and the first end of each second capacitor. A signal transfer path between the first ends.

In an embodiment of the present invention, when one of the third switches turns on the signal transmission path between the gate of the first output transistor and the first terminal of one of the second capacitors, the other third switches are turned off A signal transmission path between the gate of the first output transistor and the first terminal of the other second capacitor.

In an embodiment of the present invention, when the first part of the third switch turns on the signal transmission path between the gate of the first output transistor and the first end of the first part of the second capacitor, A second portion of the third switch The third switch disconnects the signal transfer path between the gate of the first output transistor and the second portion of the second capacitor at the first end of the second capacitor.

In an embodiment of the present invention, when one of the fourth switches turns on the signal transmission path between the gate of the second output transistor and the first terminal of one of the second capacitors, the other fourth switches are turned off A signal transmission path between the gate of the second output transistor and the first terminal of the other second capacitor.

In an embodiment of the present invention, when the first part of the fourth switch turns on the signal transmission path between the gate of the second output transistor and the first end of the first part of the second capacitor, The second part of the fourth switch disconnects the signal transfer path between the gate of the second output transistor and the second part of the second capacitor at the first terminal of the second capacitor.

In an embodiment of the present invention, the above-mentioned capacitor unit further has a third terminal and a fourth terminal. The third terminal of the capacitor unit is coupled to the gate of the first output transistor, and the fourth terminal of the capacitor unit is coupled to the gate of the second output transistor.

In an embodiment of the present invention, the above-mentioned capacitor unit includes a third capacitor and a fourth capacitor. The third capacitor has a first terminal and a second terminal. A first terminal of the third capacitor is coupled to the gate of the first output transistor, and a second terminal of the third capacitor is coupled to the output terminal of the output stage circuit. The fourth capacitor has a first terminal and a second terminal. The second terminal of the fourth capacitor is coupled to the gate of the second output transistor, and the first terminal of the fourth capacitor is coupled to the output terminal of the output stage circuit.

In an embodiment of the present invention, the output end of the above-mentioned output stage circuit is coupled to the input end of the input stage circuit to form a feedback circuit configuration.

In an embodiment of the present invention, the second source/drain of the above-mentioned first output transistor is coupled to the first system voltage, and the second source/drain of the second output transistor is coupled to the second system voltage.

In an embodiment of the present invention, the above-mentioned control signal is the most significant bit of the digital signal corresponding to the input signal.

Based on the above, in an exemplary embodiment of the present invention, the output stage circuit includes a capacitor unit and a switch unit. The operational amplifier circuit uses the control signal to switch the switching unit so that the capacitor unit can compensate the operational amplifier circuit according to different voltage ranges.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a known digitally controlled analog voltage driving circuit.

FIG. 2 is a schematic diagram illustrating a comparison of digital signals corresponding to output ranges of the digital-to-analog converter 110 .

FIG. 3 is a schematic diagram of an operational amplifier circuit according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of an operational amplifier circuit according to another embodiment of the present invention.

FIG. 5 is a schematic diagram of an operational amplifier circuit according to another embodiment of the present invention.

[Description of main component labels]

100: Digital control analog voltage drive circuit 110: Digital to analog converter

120: Operational amplifier 300, 400, 500: Operational amplifier circuit

310, 410, 510: input stage circuit 320, 420, 520: bias circuit

330, 430, 530: output stage circuit 332, 432, 532: capacitor unit

334, 434, 534: switch unit A, B, C, D: terminals of the capacitor unit

MN1, MN2, MN3: N-type field effect transistors MP1, MP2, MP3: P-type field effect transistors

AVO: output signal AVO, AVP: differential input signal

INV: the inverting input terminal of the input stage circuit IN: the non-inverting input terminal of the input stage circuit

SD: digital signal SA: analog signal

IP5, IP6, I7, I8: bias current VDD: first system voltage

VSS: second system voltage Va, Vb: bias point

OUT: the output terminal of the output stage circuit CM1: the first capacitor

CM2: second capacitor CM3: third capacitor

CM4: Fourth capacitor S: Control signal

SB: Inversion control signal SW1: First switch

SW2: Second switch SW1_1, SW1_2: Third switch

SW2_1, SW2_2: Fourth switch

Detailed ways

FIG. 3 is a schematic diagram of an operational amplifier circuit according to an embodiment of the present invention. Please refer to FIG. 3 , the operational amplifier circuit 300 of this embodiment includes an input stage circuit 310 , a bias circuit 320 and an output stage circuit 330 . The input stage circuit 310 has an inverting input terminal INV and a non-inverting input terminal IN for receiving differential input signals AVO and AVP respectively. Specifically, in this embodiment, the input stage circuit 310 includes N-type field effect transistors MN1 , MN2 , MN3 , and P-type field effect transistors MP1 , MP2 , MP3 . N-type field effect transistors MN1 , MN2 and P-type field effect transistors MP1 , MP2 each form a differential input pair. In this embodiment, the inverting input terminal INV of the operational amplifier circuit 300 is coupled to the output terminal OUT of the output stage circuit 330 , for example. Therefore, in addition to receiving the differential input signal AVP, the aforementioned two differential input pairs also receive the output signal AVO output from the output stage circuit 330 to form a feedback circuit configuration with a single gain, but the invention is not limited thereto. In other embodiments, the inverting input end of the input stage circuit 310 may also receive a differential input signal AVN (not shown) corresponding to the differential input signal AVP.

In this embodiment, the bias circuit 320 is coupled to the input stage circuit 320 for providing bias currents IP5 and IP6 to the input stage circuit 310 . In practice, the bias currents IP5 and IP6 are implemented by, for example, a transistor circuit configured with a current mirror. Therefore, the N-type field effect transistor MN3 and the P-type field effect transistor MP3 in the input stage circuit 310 are used to cooperate with the bias currents IP5, IP6 to bias the differential input pair as a current source.

In this embodiment, the output stage circuit 330 includes a pair of complementary output transistors MP9 and MN9 , a capacitor unit 332 and a switch unit 334 . The output transistor pair MP9, MN9 includes a first output transistor MP9 and a second output transistor MN9. In this example, they are respectively implemented by P-type field effect transistors and N-type field effect transistors. The drain of the first output transistor MP9 is coupled to the drain of the second output transistor MN9 via the output terminal OUT. The source of the first output transistor MP9 is coupled to the first system voltage VDD, and the source of the second output transistor MN9 is coupled to the second system voltage VSS.

When the output stage circuit 330 needs to provide a large current to the driven load or the next stage circuit, the operational amplifier circuit 300 will use the bias voltage point Va in the bias voltage circuit 320 to make the source and gate of the first output transistor MP9 There is a larger voltage difference between the poles, which in turn provides a larger current to the driven load or the next stage of the circuit. When the output stage circuit 330 needs to withdraw a large current from the driven load or the next stage circuit, the operational amplifier circuit 300 will use the bias voltage point Vb in the bias voltage circuit 320 to make the source of the second output transistor MN9 There is a large voltage difference between the electrode and the grid, and a large current is drawn from the driven load or the next-level circuit.

In this embodiment, the capacitor unit 332 is used to compensate the operational amplifier circuit 330 to improve its stability. The capacitor unit 332 has a first terminal A and a second terminal B. The first terminal A of the capacitor unit 332 is coupled to the switch unit 334 . The second terminal B of the capacitor unit 332 is coupled to the output terminal OUT of the output stage circuit 330 . Specifically, the capacitor unit 332 of this embodiment includes a first capacitor CM1. The first capacitor CM1 has a first terminal and a second terminal. A first terminal of the first capacitor CM1 is coupled to the first terminal A of the capacitor unit 332 , and a second terminal of the first capacitor CM1 is coupled to the second terminal B of the capacitor unit 332 .

In this embodiment, the switch unit 334 is coupled between the gates of the first output transistor MP9 and the second output transistor MN9 , and is coupled to the first terminal A of the capacitor unit 332 . The switch unit 334 determines to turn on the signal transmission path between the gate of the first output transistor MP9 and the first terminal A of the capacitor unit 332 according to the control signal S, or to turn on the gate of the second output transistor MN9 to the capacitor unit 332 The signal transmission path between the first end A. Specifically, the switch unit 334 of this embodiment includes a first switch SW1 and a second switch SW2. The first switch SW1 has a first terminal, a second terminal and a control terminal. The first terminal of the first switch SW1 is coupled to the gate of the first output transistor MP9, the second terminal of the first switch SW1 is coupled to the first terminal A of the first capacitor CM1, and the control terminal of the first switch SW1 is controlled Inverted control signal SB. The second switch SW2 has a first terminal, a second terminal and a control terminal. The second terminal of the second switch SW2 is coupled to the gate of the second output transistor MN9, the first terminal of the second switch SW2 is coupled to the first terminal A of the first capacitor CM1, and the control terminal of the second switch SW2 is controlled on the control signal S.

In this embodiment, when the first switch SW1 turns on the signal transmission path between the gate of the first output transistor MP9 and the first terminal A of the first capacitor CM1, the second switch SW2 turns off the second output transistor MN9 The signal transmission path between the gate of the first capacitor CM1 and the first terminal A of the first capacitor CM1. Conversely, when the second switch SW2 turns on the signal transmission path between the gate of the second output transistor MN9 and the first terminal A of the first capacitor CM1, the first switch SW1 turns off the gate of the first output transistor MP9. The signal transmission path between the terminal A of the first capacitor CM1 and the first capacitor CM1.

When the operational amplifier circuit 300 of this embodiment is applied to digitally control the analog voltage driving circuit 100, the control signal S is, for example, the most significant bit of the digital signal SD. When the most significant bit of the digital signal SD is 1 (MSB=1), the control signal S=1, the inverting control signal SB=0, both turn on the gate of the first output transistor MP9 and the first capacitor unit 332 The signal transmission path between the terminals A is disconnected, and the signal transmission path between the gate of the second output transistor MN9 and the first terminal A of the first capacitor CM1 is disconnected. In other words, when the operational amplifier circuit 330 operates in the voltage range of the high potential output V2 to V3, the switch unit 334 switches to the signal transmission path between the gate of the first output transistor MP9 and the first terminal A of the capacitor unit 332, The operational amplifier circuit 330 is compensated by the first capacitor CM1 to improve its stability.

On the other hand, when the most significant bit of the digital signal SD is 0 (MSB=0), the control signal S=0 and the inverted control signal SB=1, both of them turn on the gate of the second output transistor MN9 and the first The first terminal A of the capacitor CM1 connects the signal transmission path between the first output transistor, and disconnects the signal transmission path between the gate of MP9 and the first terminal A of the capacitor unit 332 . In other words, when the operational amplifier circuit 330 operates in the voltage range of the low potential output V1 to V2, the switch unit 334 switches between the gate of the second output transistor MN9 and the first output transistor A of the first capacitor CM1. The signal transmission path of the operational amplifier circuit 330 is compensated by the first capacitor CM1 to improve its stability.

Therefore, in the application of the digitally controlled analog voltage driving circuit, for the compensation of the stability of the operational amplifier circuit 330 , only a single capacitor needs to be designed inside the output stage circuit 330 of this embodiment to compensate its stability. Through switching of the switch unit 334, the single capacitor can compensate the operational amplifier circuit 330 in different potential output ranges. Therefore, in the design architecture of this embodiment, the compensation capacitor will not occupy an excessively large area in the chip. In addition, if the slew rate needs to be increased, it can be achieved by adjusting the capacitance value of the compensation capacitor.

It should be noted that the control signal in this embodiment is not limited to the most significant bit of an 8-bit digital signal. The implementation form of the control signal can be any bit of a digital signal with any number of digits, or other control signals set by the designer according to actual needs. In addition, the scope of application of the operational amplifier circuit of this embodiment is not limited to digitally controlled analog voltage drive circuits.

FIG. 4 is a schematic diagram of an operational amplifier circuit according to another embodiment of the present invention. 3 and 4, the operational amplifier circuit 400 of the present embodiment is similar to the operational amplifier circuit 300 of FIG.

The capacitor unit 432 of this embodiment includes a plurality of second capacitors. In this example, for the sake of brief description, FIG. 4 only shows two second capacitors CM2_1 and CM2_2 for illustration, and the number thereof is not intended to limit the present invention. Each second capacitor has a first end and a second end. First terminals of the second capacitors CM2_1 and CM2_2 are coupled to the first terminal A of the capacitor unit 432 , and second terminals of the second capacitors CM2_1 and CM2_2 are coupled to the second terminal B of the capacitor unit 432 .

In this embodiment, the switch unit 434 includes a plurality of third switches and a plurality of fourth switches. In this example, for the sake of brief description, FIG. 4 only shows two third switches SW1_1 , SW1_2 and two fourth switches SW2_1 , SW2_2 for illustration, and the number of individual switches is not intended to limit the present invention. In this embodiment, each third switch has a first terminal, a second terminal and a control terminal. Taking the third switch SW1_1 as an example, the first terminal of the third switch SW1_1 is coupled to the gate of the first output transistor MP9, and the second terminal of the third switch SW1_1 is coupled to the first terminal A of the second capacitor CM2_1. The control terminals of the three switches SW1_1 are controlled by the inverted control signal SB. The coupling relationship between the third switch SW1_2 and other circuit elements can be deduced from FIG. 4 , and will not be repeated here. It is worth mentioning that the second terminals of the third switches SW1_1 , SW1_2 are coupled to the first terminals A of different second capacitors CM2_1 , CM2_2 .

In this embodiment, each fourth switch has a first terminal, a second terminal and a control terminal. Taking the fourth switch SW2_1 as an example, the first terminal of the fourth switch SW2_1 is coupled to the first terminal A of the second capacitor CM2_1, and the second terminal of the fourth switch SW2_1 is coupled to the gate of the second output transistor MN9. The control terminals of the four switches SW2_1 are controlled by the control signal S. The coupling relationship between the fourth switch SW2_2 and other circuit elements can be deduced from FIG. 4 , and will not be repeated here. It is worth mentioning that the first terminals of the fourth switches SW2_1 , SW2_2 are coupled to the first terminals A of different second capacitors CM2_1 , CM2_2 .

From another point of view, if the second capacitor CM2_1, the third switch SW1_1 and the fourth switch SW2_1 are regarded as a compensation module, then this compensation module can perform the compensation function of the capacitor unit 332 and the switch unit 334 as shown in FIG. 3 . Therefore, from this point of view, the capacitor unit 432 and the switch unit 434 in this embodiment can be regarded as a parallel connection of the above-mentioned compensation modules.

In this embodiment, when each third switch turns on the signal transmission path between the gate of the first output transistor MP9 and the first terminal A of each second capacitor, each fourth switch turns off the second output transistor MN9 The signal transmission path between the gate of the second capacitor and the first terminal A of each second capacitor. Conversely, when each fourth switch turns on the signal transmission path between the gate of the second output transistor MN9 and the first terminal A of each second capacitor, each third switch turns off the gate of the first output transistor MP9. and the signal transmission path between the first terminal A of each second capacitor.

In the implementation of multiple second capacitors, when one of the third switches turns on the signal transmission path between the gate of the first output transistor MP9 and the first terminal A of one of the second capacitors, the other The third switch disconnects the signal transmission path between the gate of the first output transistor MP9 and the first terminal A of the other second capacitor. For example, in this embodiment, when the third switch SW1_1 turns on the signal transmission path between the gate of the first output transistor MP9 and the first terminal A of the second capacitor CM2_1, the third switch SW1_2 turns off the first terminal A of the second capacitor CM2_1. A signal transmission path between the gate of the output transistor MP9 and the first terminal A of the second capacitor CM2_2 .

Similarly, in the implementation of multiple second capacitors, when one of the fourth switches turns on the signal transmission path between the gate of the second output transistor MN9 and the first terminal of one of the second capacitors , the other fourth switch disconnects the signal transmission path between the gate of the second output transistor MN9 and the first terminal of the other second capacitor. For example, in this embodiment, when the fourth switch SW2_1 turns on the signal transmission path between the gate of the second output transistor MN9 and the first terminal A of the second capacitor CM2_1, the fourth switch SW2_2 turns off the second A signal transmission path between the gate of the second output transistor MN9 and the first terminal A of the second capacitor CM2_2 .

In other words, in this embodiment, only one of the plurality of third switches is turned on at a time, and only one of the plurality of fourth switches is turned on at a time, but the present invention is not limited thereto. In another embodiment, some of the multiple third switches may be turned on at the same time, and another part may be turned off at the same time. Moreover, it is also possible that some of the multiple fourth switches are turned on at the same time, and the other part is turned off at the same time.

For example, in the implementation of more than three second capacitors, when the first part of the plurality of third switches, for example, a specific number of the third switches, turns on the gate of the first output transistor MP9 When the signal transmission path between the first terminal A of the second capacitor and part of the second capacitor, the third switch of the second part of the third switch, such as the remaining third switch, disconnects the gate of the first output transistor MP9 from the other A part of the signal transmission path between the first terminals A of the second capacitor. Similarly, when the first part of the plurality of fourth switches, for example, a specific number of fourth switches among them, turns on the signal between the gate of the second output transistor MN9 and the first terminal A of part of the second capacitor During the transmission path, the fourth switch in the second part of the fourth switch, such as the remaining fourth switches, disconnects the signal transmission between the gate of the second output transistor MN9 and the first terminal A of another part of the second capacitor path.

FIG. 5 is a schematic diagram of an operational amplifier circuit according to another embodiment of the present invention. 3 and 5, the operational amplifier circuit 500 of this embodiment is similar to the operational amplifier circuit 300 of FIG.

The capacitor unit 532 of this embodiment also has a third terminal C and a fourth terminal D. The third terminal C of the capacitor unit 532 is coupled to the gate of the first output transistor MP9, and the fourth terminal D of the capacitor unit 532 is coupled to the gate of the second output transistor MN9. Specifically, in this embodiment, the capacitor unit 532 further includes a third capacitor CM3 and a fourth capacitor CM4. The third capacitor CM3 has a first terminal and a second terminal. A first terminal of the third capacitor CM3 is coupled to the gate of the first output transistor MP9 , and a second terminal of the third capacitor CM3 is coupled to the output terminal OUT of the output stage circuit 530 . The fourth capacitor CM4 has a first terminal and a second terminal. A second terminal of the fourth capacitor CM4 is coupled to the gate of the second output transistor MN9 , and a first terminal of the fourth capacitor CM4 is coupled to the output terminal OUT of the output stage circuit 530 .

From the point of view of circuit operation, when the first switch SW1 is turned on and the second switch SW2 is turned off, the first capacitor CM1 and the third capacitor CM3 form a parallel configuration, which is equivalent to a compensation capacitor, so that the operational amplifier circuit 500 Make compensation. Conversely, when the second switch SW2 is turned on and the first switch SW1 is turned off, the first capacitor CM1 and the fourth capacitor CM4 form a parallel configuration, which is equivalent to another compensation capacitor, and can also compensate the operational amplifier circuit 500 .

To sum up, in an exemplary embodiment of the present invention, the output stage circuit includes a capacitor unit and a switch unit. The operational amplifier circuit uses the control signal to switch the switching unit so that the capacitor unit can compensate the operational amplifier circuit according to different voltage ranges. This design structure not only saves the chip area, but also improves the driving capability of the operational amplifier circuit.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims (16)

1. An operational amplifier circuit comprising: The input stage circuit has an input terminal for receiving an input signal; a bias circuit coupled to the input stage circuit for providing a bias current to the input stage circuit; and An output stage circuit, coupled to the bias circuit, has an output terminal, and the output stage circuit includes: an output transistor pair, including a first output transistor and a second output transistor, the first source/drain of the first output transistor is coupled to the first source/drain of the second output transistor through the output terminal; a capacitor unit having a first end and a second end, the second end of the capacitor unit being coupled to the output end of the output stage circuit; and a switch unit, coupled between the gates of the first and second output transistors, and coupled to the first end of the capacitor unit, Wherein the switch unit decides to turn on the signal transmission path between the gate of the first output transistor and the first end of the capacitor unit according to the control signal, or to turn on the gate of the second output transistor and the first end of the capacitor unit. A signal transmission path between the first ends of the capacitor units. 2. The operational amplifier circuit of claim 1, wherein the capacitive unit comprises: The first capacitor has a first end and a second end, the first end of the first capacitor is coupled to the first end of the capacitance unit, and the second end of the first capacitor is coupled to the capacitance unit the second end of . 3. The operational amplifier circuit according to claim 2, wherein said switching unit comprises: The first switch has a first terminal, a second terminal and a control terminal, the first terminal of the first switch is coupled to the gate of the first output transistor, and the second terminal of the first switch is coupled to the first terminal of the first capacitor, the control terminal of the first switch is controlled by the control signal with an inverted phase; and The second switch has a first terminal, a second terminal and a control terminal, the second terminal of the second switch is coupled to the gate of the second output transistor, the first terminal of the second switch is coupled to The first terminal of the first capacitor and the control terminal of the second switch are controlled by the control signal. 4. The operational amplifier circuit according to claim 3 , wherein when the first switch conducts a signal transfer path between the gate of the first output transistor and the first end of the first capacitor, the The second switch disconnects the signal transmission path between the gate of the second output transistor and the first terminal of the first capacitor, and when the second switch turns on the gate of the second output transistor and the signal transmission path between the first end of the first capacitor, the first switch disconnects the signal transmission path between the gate of the first output transistor and the first end of the first capacitor . 5. The operational amplifier circuit of claim 1 , wherein the capacitive unit comprises: A plurality of second capacitors, each of the second capacitors has a first end and a second end, the first end of each of the second capacitors is coupled to the first end of the capacitor unit, and each of the second capacitors The second terminal is coupled to the second terminal of the capacitor unit. 6. The operational amplifier circuit according to claim 5, wherein said switching unit comprises: A plurality of third switches, each of the third switches has a first terminal, a second terminal and a control terminal, the first terminal of each of the third switches is coupled to the gate of the first output transistor, and each of the third switches The second terminals of the third switches are coupled to different first terminals of the second capacitors, and the control terminals of the respective third switches are controlled by the control signals in opposite phases; and A plurality of fourth switches, each of the fourth switches has a first terminal, a second terminal and a control terminal, the second terminal of each of the fourth switches is coupled to the gate of the second output transistor, and each of the fourth switches The first ends of the fourth switches are coupled to the first ends of different second capacitors, and the control ends of the fourth switches are controlled by the control signal. 7. The operational amplifier circuit according to claim 6, wherein when the third switches conduct the signal transmission path between the gate of the first output transistor and the first ends of the second capacitors , the fourth switches disconnect the signal transmission paths between the gates of the second output transistors and the first terminals of the second capacitors, and when the fourth switches turn on the second When there is a signal transmission path between the gate of the output transistor and the first end of each second capacitor, each of the third switches disconnects the gate of the first output transistor from the first end of each second capacitor. Signal transmission path between one end. 8. The operational amplifier circuit according to claim 6 , wherein when one of the third switches turns on the gate of the first output transistor and one of the second capacitors When the signal transmission path between the first terminals of the capacitor is closed, the other third switch disconnects the signal transmission path between the gate of the first output transistor and the first terminal of the other second capacitor. 9. The operational amplifier circuit according to claim 6 , wherein when the first part of the third switch turns on the gate of the first output transistor and the first part of the second capacitor The second part of the third switch disconnects the gate of the first output transistor from the first part of the second capacitor to the second part of the second capacitor when the signal transfer path between the first terminal The signal transmission path between the terminals. 10. The operational amplifier circuit according to claim 6, wherein when one of the fourth switches turns on the gate of the second output transistor and one of the second capacitors The other fourth switch disconnects the signal transmission path between the gate of the second output transistor and the first terminals of the other second capacitors. 11. The operational amplifier circuit of claim 6, wherein when the first portion of the fourth switch the fourth switch turns on the gate of the second output transistor and the first portion of the second capacitor The second part of the fourth switch disconnects the gate of the second output transistor from the first part of the second capacitor to the second part of the second capacitor when the signal transfer path between the first terminal The signal transmission path between the terminals. 12. The operational amplifier circuit according to claim 1, wherein the capacitance unit further has a third end and a fourth end, the third end of the capacitance unit is coupled to the gate of the first output transistor, the The fourth end of the capacitor unit is coupled to the gate of the second output transistor. 13. The operational amplifier circuit of claim 12, wherein the capacitive unit comprises: The third capacitor has a first terminal and a second terminal, the first terminal of the third capacitor is coupled to the gate of the first output transistor, and the second terminal of the third capacitor is coupled to the output output terminal of the stage circuit; and The fourth capacitor has a first terminal and a second terminal, the second terminal of the fourth capacitor is coupled to the gate of the second output transistor, and the first terminal of the fourth capacitor is coupled to the output output terminal of the stage circuit. 14. The operational amplifier circuit of claim 1, wherein an output terminal of the output stage circuit is coupled to an input terminal of the input stage circuit forming a feedback circuit configuration. 15. The operational amplifier circuit according to claim 1 , wherein the second source/drain of the first output transistor is coupled to a first system voltage, and the second source/drain of the second output transistor is coupled to to the second system voltage. 16. The operational amplifier circuit of claim 1, wherein the control signal is the most significant bit of a digital signal corresponding to the input signal.

Images