CN210351102U - Microphone programmable gain amplifier integrated circuit - Google Patents
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Abstract
The utility model discloses a microphone programmable gain amplifier integrated circuit, which relates to the field of voice integrated circuits, and comprises an operational amplifier, two groups of first capacitors, a second capacitor, a third capacitor and a switch capacitor array, wherein the differential input end of the operational amplifier is connected with a small-capacity first capacitor for decoupling in series, and two second capacitors are respectively bridged between the differential input end and the differential output end of the operational amplifier; the switch capacitor array comprises a plurality of groups of first switches and fourth capacitors which are connected in series, the fourth capacitors are controlled by the gating of the first switches and are connected with the second capacitors or the first capacitors in parallel, and programmable gain is formed; the third capacitor is connected in series with a second switch, the second switch is switched and connected with the clock frequency, the third capacitor is gated by the second switch in the first half period of the clock frequency, and two ends of the third capacitor are respectively connected with the input common-mode voltage and the output common-mode voltage; the third capacitor is connected in parallel with the second capacitor during a second half-cycle of the clock frequency.
Description
Technical Field
The utility model relates to a pronunciation integrated circuit field especially relates to a microphone gain amplifier integrated circuit able to programme.
Background
In mobile communication electronic devices, circuit scale and chip area are important considerations in design. In a mobile phone system, reducing the effective area of each chip on a mainboard not only means reducing the required cost, but also means that more chips can be added in a printed circuit board with the same area, thereby enriching the system function. In a traditional mobile phone mainboard, a passive surface-mounted device represented by a resistor, a capacitor and an inductor occupies a large system area in a direct welding mode. In recent years, engineers can package these passive devices and chips In one package thanks to sip (system In a package) system In package technology. However, in the path from the microphone to the analog front-end amplifier, large decoupling capacitances are often required, and these capacitances with large capacitance values are too large in area to realize a SIP package. A typical microphone-to-programmable amplifier requires the use of an off-chip decoupling capacitor to remove the dc component from the microphone, and the capacitance of the decoupling capacitor is generally in the range of hundreds of nanofarads to a few microfarads, and cannot be integrated on-chip.
SUMMERY OF THE UTILITY MODEL
In view of the above-mentioned drawbacks of the prior art, it is an object of the present invention to provide a microphone programmable gain amplifier integrated circuit capable of integrating a decoupling capacitor into a chip, so as to improve the integration of the microphone programmable gain amplifier circuit.
In order to achieve the above purpose, the utility model provides a following technical scheme:
a microphone programmable gain amplifier integrated circuit comprises an operational amplifier, two groups of first capacitors C1 and second capacitors C2AA third capacitor C2BAnd a switched capacitor array, and a capacitor array,
the operational amplifier comprises a differential input end and a differential output end, the differential input end of the operational amplifier is electrically connected with the differential signal input end of the microphone programmable gain amplifier circuit through a first capacitor C1, and the differential output end of the operational amplifier is the differential signal output end of the microphone programmable gain amplifier circuit;
two of the second capacitors C2AThe voltage-stabilizing circuit is respectively bridged between the positive pole of the differential input end and the positive pole of the differential output end of the operational amplifier, and between the negative pole of the differential input end and the negative pole of the differential output end of the operational amplifier;
the switched capacitor array comprises a plurality of groups of first switches SW connected in seriesnAnd a fourth capacitance CXnSaid fourth capacitance CXnBy a first switch SWnGating control and second capacitor C2AOr the first capacitor C1 is connected in parallel;
the third capacitor C2BIn series with a second switch at a clock frequency fclkMaking a switched connection at a clock frequency fclkOf said third capacitor C2BThe second switch is used for gating, and two ends of the second switch are respectively connected with the input common-mode voltage and the output common-mode voltage; at clock frequency fclkSecond half period of (C), the third capacitance C2BAnd a second capacitor C2AParallel connection;
the capacitance value of the first capacitor is 20-100 pF.
Further, the amplifier gain of the programmable gain amplifier is determined by a capacitance ratio, where the capacitance ratio is:
wherein C1 is the capacitance of the first capacitor C1, C2AIs a second capacitor C2AThe capacitance value of (a) is set,
a fourth capacitor C for all gates in the switched capacitor arrayXiSum of capacitance values of, K xi1 represents CXiIs gated; k xi0 represents CXiIs not gated.
Further, the programmable gain amplifier is embodied as a high-pass filter, the cut-off frequency f of which isHPComprises the following steps:
wherein f isHPIs the cut-off frequency of the high-pass filter, fclkClock frequency for switching of the second switch, C2BIs the capacitance value of the third capacitor, C2AIs the capacitance value of the second capacitor.
Further, the cutoff frequency satisfies 20Hz or less.
Further, the operational amplifier is a two-stage miller compensated class AB transconductance amplifier.
Furthermore, the two-stage miller compensation class AB transconductance amplifier comprises a bias circuit, a first-stage input amplification circuit and a second-stage output amplification circuit;
the bias circuit provides a first bias voltage and a second bias voltage;
the input amplification circuit comprises a zeroth PMOS (P-channel metal oxide semiconductor) tube, a PMOS (P-channel metal oxide semiconductor) differential input geminate transistor, a first load transistor pair and a second load transistor pair, the grid electrode of the PMOS differential input geminate transistor is the differential input end of the AB class transconductance amplifier, and the first load transistor pair is biased at a second bias voltage Vbias; the second pair of load transistors is biased at a common mode feedback voltage;
the PMOS differential input pair transistors comprise a first PMOS transistor and a second PMOS transistor;
the first load transistor pair comprises a first NMOS transistor NM1aAnd a second NMOS tube NM2a；
The second load transistor pair comprises an eleventh NMOS transistor NM1bAnd a twelfth NMOS tube NM2b；
The first output end of the input amplifying circuit, the source electrode of the first PMOS tube and the first NMOS tube NM1aAnd a second NMOS tube NM2aThe drain connection of (1);
the second output end of the input amplifying circuit, the source electrode of the second PMOS tube and the eleventh NMOS tube NM1bAnd a twelfth NMOS tube NM2bThe drain connection of (1);
the drain of the zeroth PMOS is connected to a first level of a power supply, the source of the zeroth PMOS is connected with the drain of the first PMOS tube and the drain of the second PMOS tube, and the grid of the zeroth PMOS tube is biased at a first bias voltage;
the first NMOS transistor NM1a and the second NMOS transistor NM2aAnd an eleventh NMOS tube NM1bAnd a twelfth NMOS tube NM2bIs connected to a second level of the power supply;
the output amplifying circuit of the second stage comprises a first output amplifying circuit and a second output amplifying circuit;
the first output amplifying circuit comprises a third PMOS tube, a fifth MOS tube, a third NMOS tube and a fifth NMOS tube;
the first output end of the input amplifying circuit is connected with the grid electrode of the third NMOS tube;
the second output end of the input amplifying circuit is connected with the grid electrode of the fifth NMOS tube;
the drain of the third NMOS transistor NM3 is connected with the source of the third PMOS transistor, the gate of the third PMOS transistor and the gate of the fifth PMOS transistor;
the drain electrodes of the third PMOS tube and the fifth PMOS tube are connected to a first level of a power supply;
the source electrodes of the third NMOS transistor and the fifth NMOS transistor are connected to a second level of the power supply;
the drain electrode of the fifth NMOS tube and the source electrode of the fifth PMOS tube are connected to the first differential output end of the first output amplifying circuit;
a miller compensation circuit is connected between the grid and the drain of the fifth NMOS transistor NM5 in a bridging way;
the second output amplifying circuit comprises a fourth PMOS tube, a sixth MOS tube, a fourth NMOS tube and a sixth NMOS tube;
the first output end of the input amplifying circuit is connected with the grid electrode of the fourth NMOS tube;
the second output end of the input amplifying circuit is connected with the grid electrode of the sixth NMOS tube;
the drain of the sixth NMOS tube is connected with the source of the fourth PMOS tube, the grid of the fourth PMOS tube and the grid of the sixth PMOS tube;
the drain electrodes of the fourth PMOS tube and the sixth PMOS tube are connected to a first level;
the source electrodes of the fourth NMOS transistor and the sixth NMOS transistor are connected to a second level;
the drain electrode of the sixth NMOS tube and the source electrode of the sixth PMOS tube are connected to the second differential output end of the first output amplifying circuit;
and a Miller compensation circuit is connected between the grid electrode and the drain electrode of the sixth NMOS tube in a bridging mode.
Further, the miller compensation circuit comprises a resistor and a capacitor connected in series.
Furthermore, the programmable gain amplifier also comprises a band-gap reference source and a low-dropout linear regulator;
the band-gap reference source provides reference voltage for the low-dropout linear regulator and also provides current bias and common-mode feedback voltage for the two-stage Miller-compensated class AB transconductance amplifier;
the low dropout linear regulator is powered by an off-chip power supply and provides power supply voltage for the transconductance amplifier.
Further, the voltage of the off-chip power supply is 1.4V, and the power supply voltage of the transconductance amplifier is 1.0V.
Further, the current bias output by the bandgap reference source is 2 μ A.
Further, the common mode feedback voltage is 0.5V.
The utility model discloses a following technological effect:
the utility model discloses a switched capacitor array adopts the high pass filter design, can adopt less decoupling capacitor to the realization is integrated the fully integrated microphone gain amplifier circuit able to programme in the piece with decoupling capacitor, does benefit to and realizes system level packaging.
The embodiment of the utility model provides an amplifier is AB class transconductance amplifier of two-stage miller compensation, through the push-pull output amplification structure of difference amplification and AB class to realize the great output swing under the low voltage power supply, and reduce the low frequency 1/f noise.
Drawings
Fig. 1 is a circuit block diagram of a programmable gain amplifier according to an embodiment of the present invention;
fig. 2 is a schematic circuit diagram of a low voltage two-stage miller compensated class AB transconductance amplifier of an embodiment of the present invention;
fig. 3 is a schematic diagram of a bandgap reference source circuit according to an embodiment of the present invention;
FIG. 4 is a graph of a gain frequency simulation of a programmable gain amplifier;
FIG. 5 is a transconductance amplifier gain phase curve;
FIG. 6 is a plot of a spectral simulation of the output signal of a transconductance amplifier;
fig. 7 is a graph of the noise of a transconductance amplifier.
Detailed Description
To further illustrate the embodiments, the present invention provides the accompanying drawings. The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the embodiments. With these references, one of ordinary skill in the art will appreciate other possible embodiments and advantages of the present invention. Elements in the figures are not drawn to scale and like reference numerals are generally used to indicate like elements.
The present invention will now be further described with reference to the accompanying drawings and detailed description.
A typical microphone signal analog processing chip includes a programmable gain amplifier, an anti-aliasing filter, a switched capacitor Sigma Delta modulator, and a digital filter. As a first stage of microphone signal processing, the programmable gain amplifier is typically required to provide 0-20dB of gain adjustability, with more gain being available for subsequent digital signal processing circuitry. In order to meet the application requirement of high-quality microphone output, the output signal of the programmable gain amplifier should have a Dynamic Range (DR) and Total Harmonic Distortion (THD) performance of more than 60 dB.
The utility model discloses an embodiment of a programmable gain amplifier circuit, its circuit diagram is shown in fig. 1 and fig. 2.
The product canThe programming gain amplifier comprises a transconductance operational amplifier OTA, a capacitor C1 and a capacitor C2ACapacitor C2BSwitched capacitor array CX1～CXNThe band gap reference source Bandgap and the low dropout regulator LDO. As shown in fig. 1, by a switch SW1，SW2，…，SWNControlled capacitance CX1，CX2，…，CXNAnd a capacitor C2AAnd the gain of 1.5dB is adjustable by gating through parallel connection. The capacitor C1 is a decoupling capacitor, and the amplifier gain is determined by the capacitance ratio of
Wherein C1 is the capacitance of the first capacitor, C2AIs the capacitance value of the second capacitor and,
a fourth capacitor C for all gates in the switched capacitor arrayXiSum of capacitance values of, K xi1 represents CXiIs gated; k xi0 represents CXiIs not gated.
By switching off a different number of fourth capacitors C in the capacitor arrayXiThe programmable amplifier gain with the step length of 1.5dB is realized from 0dB to 20dB by adjusting the sum of the capacitance values output by the capacitor array.
In this embodiment, at 0dB, CX1，CX2，…，CXNFull conduction and capacitance C2AParallel connection; off CX1The gain of 1.5dB is realized; turn off C simultaneouslyX1，CX23dB gain is realized; turn off C simultaneouslyX1、CX2、CX3A gain of 4.5dB is realized; until C is turned off at the same timeX1，CX2，…，CXNA gain of 20dB is achieved. Table 1 gives a specific example of the capacitance of the gain of the programmable amplifier, C1 ═ 30pF, C2ABy turning off the capacitors one by one to achieve incremental gain 3pF, C can be conveniently calculated from table 1X1＝4.79pF，CX23.96pF, etc.
Table 1:
capacitor C2BOn the one hand, to balance the input and output common mode voltages, stabilizing both at half the supply voltage. On the other hand the capacitance C2BAnd a capacitor C2ATogether forming a high-pass filter characteristic, cut-off to frequency fHPComprises the following steps:
in order to realize system-in-package, the on-chip capacitors are all selected to have smaller capacitance values, wherein the capacitance value of the capacitor C1 is selected to be 20-100 pF. In this embodiment, the capacitance of the capacitor C1 is set to 30pF at 0dB gain. Since the lowest frequency range of sound received by the human ear is above 20Hz, the clock frequencies clk and C can be selected2BIs configured in a plurality of combinations, here taking the clock frequency fclk＝140kHz，C2B20pF, making the high pass cut-off frequency about 15Hz, leaving a certain band margin, as shown in fig. 4. The Bandgap reference source Bandgap provides 1.4V power supply from outside of the chip, and provides 0.4V reference voltage V for the low dropout regulator LDOrefMeanwhile, two paths of current bias I of 2 mu A are also provided for the transconductance amplifier2u1And I2u2And a common mode feedback voltage Vcmfb _ in of 0.5V; the LDO provides 1.4V power supply from outside chip and inputs the reference voltage V of Bandgap reference source BandgaprefAnd a stable power supply voltage VDDA of 1.0V is provided for the buffer and the transconductance amplifier.
The utility model discloses a switched capacitor array through adopting high pass filter design, has accomplished a section and will decouple the integrated whole integrated microphone programmable gain amplifier circuit in the piece of electric capacity integration, does benefit to and realizes system level packaging.
In order to meet the application requirement of high-quality microphone output, the output signal of the programmable gain amplifier should have a Dynamic Range (DR) and Total Harmonic Distortion (THD) performance of more than 60 dB. In order to drive the Sigma Delta modulator at the subsequent stage and realize a larger output swing, the operational amplifier OTA of the present embodiment is designed as a low-voltage class AB transconductance amplifier with two-stage amplification and miller compensation, and the circuit thereof is shown in fig. 2.
The two-stage Miller compensation AB class transconductance amplifier comprises a PMOS transistor pair differential input amplification circuit of a first stage, a Miller compensation AB class differential amplification circuit of a second stage and a biasing circuit;
wherein the differential PMOS transistor pair differential amplification circuit of the first stage consists of a PMOS transistor pair PM1/PM2Two sets of load transistor pairs NM1a、NM2aAnd NM1b、NM2bAnd a constant current bias transistor PM 0. Load transistor pair NM1a、NM2aIs biased at a fixed bias voltage Vbias provided by a bias circuit; and the load transistor pair NM1b、NM2bDriven by a common mode feedback voltage Vcmfb, which is connected to the common mode feedback voltage Vcmfb _ in of fig. 1. The method has the greatest advantages that the output load capacitance of the first-stage amplifying circuit is effectively reduced, the phase margin of the transconductance amplifier is favorably improved, and the frequency characteristic is stabilized.
The Miller compensation AB type differential amplification circuit of the second stage comprises PM3/NM3、PM5/NM5And PM4/NM4、PM6/NM6And the formed AB output stage outputs differential signals Voutp and Voutn. R1/C1 and R2/C2 are connected across the input and output of the second stage to form RC Miller compensation. PM (particulate matter)3/NM3、PM5/NM5And PM4/NM4、PM6/NM6The formed AB class output stage optimizes output quiescent current and simultaneously realizes output voltage with larger swing.
The bias circuit comprises a PMOS transistor pair PM8/PM9And NMOS tube NM7、NM8、NM9The bias voltage Vbias and the bias voltage of the constant current bias transistor PM0 are provided.
To optimize the noise performance of the transconductance amplifier, the PMOS transistor pair PM is selected1And PM2As an input stage of the transconductance amplifier, differential signals Vin, Vip are input. According to the noise theory, the equivalent input noise of the transconductance amplifier is:
wherein W1、L1And gm1The channel width, the channel length and the transconductance of the PMOS transistor are respectively; w2、L2And gm2Respectively NMOS transistor channel width, channel length, and transconductance. Mu.spIs the PMOS transistor mobility. CoXIs the oxide layer capacitance per unit area. KFNAnd KFPThe flicker noise figure of the PMOS and NMOS transistors, respectively. The left and right term parts of the plus sign in the formula represent thermal noise and flicker noise, respectively. The thermal noise term shows that the transconductance of the input transistor is increased, and the thermal noise can be effectively reduced. Meanwhile, the width and length of the input transistor are large, which also means W in the flicker noise term1L1The product is large, which is also beneficial to reducing the low frequency 1/f noise.
FIG. 5 is a transconductance amplifier gain phase curve; FIG. 6 is a plot of a spectral simulation of the output signal of a transconductance amplifier; FIG. 7 is a noise plot for a transconductance amplifier; simulation data of the transconductance amplifier finally designed are shown in fig. 5, 6 and 7, wherein the direct current gain is 86dB, and the phase margin is 61 degrees. As shown in FIG. 7, the equivalent input noise at 101Hz is only 708nV/sort Hz, and the noise performance is good.
The bandgap reference source circuit is shown in fig. 3 and includes a bias circuit, a start-up circuit and a bandgap reference source main circuit.
The bias circuit outputs a path of bias voltage Vb to bias the voltage of the transconductance amplifier OTA; in the middle band gap reference source main circuit, a triode PNP1, a PNP2, a resistor R1/R2/R3, a transconductance amplifier OTA and a PMOS transistor PM1/PM2 form zero temperature coefficient voltage output together, and a current source transistor PM3/PM4/PM5/PM6 is biased. Wherein PM3/R4 constitutes zero temperature coefficient voltage output circuit, outputs reference voltage Vref. The PM4/R5 forms a zero temperature coefficient voltage output circuit, which outputs a reference voltage Vcmfb _ in. The PM5/PM6 is used as a current source transistor and outputs two current sources I2u1 and I2u 2; the working principle of the right starting circuit is as follows: when the power supply voltage is zero, the grid electrode of the PMOS tube PM9 is at zero level, and the PM9 is conducted; when the power supply voltage gradually rises, a path from the power supply to the input end of the transconductance amplifier is formed, and the transconductance amplifier has input common-mode direct-current voltage and starts to work. While the path charges the MOS capacitor formed by the NMOS transistor NM 1; when the power supply voltage continues to rise, the PMOS transistor PM8 is switched on, a current path of the PM8 through the resistor R5 is formed, the gate voltage of the PM9 gradually rises, and when the absolute value of the overdrive voltage of the PM9 is larger than the absolute value of the drain-source voltage, the PM9 is switched off. And meanwhile, the MOS capacitor is charged, the voltage on the MOS capacitor maintains the input common-mode voltage of the transconductance amplifier, and the band-gap reference source enters a normal working state.
The bandgap reference source circuit can also adopt other existing bandgap reference source circuits to realize temperature-independent voltage reference and current reference.
Fig. 3 and fig. 2 are independent circuit diagrams, and the element numbers and the network numbers in the diagrams are independent and are only used for explaining the working principle of the respective circuit diagrams. VDDA1 in fig. 3 corresponds to 1.4V in fig. 1.
The LDO circuit of the embodiment adopts a traditional two-stage error amplifier circuit structure, and meanwhile, the frequency characteristic of a Miller compensation capacitor stabilizing circuit is added. The LDO output transistor is designed to be 600 mu m/300nm in large size, and the current driving capability of the output stage is enhanced.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. Microphone programmable gain amplifier integrated circuitThe road, its characterized in that: comprises an operational amplifier, two groups of first capacitors C1 and second capacitors C2AA third capacitor C2BAnd a switched capacitor array, and a capacitor array,
the operational amplifier comprises a differential input end and a differential output end, and the first capacitor C1 is connected between the differential input end of the operational amplifier and the differential signal input end of the microphone programmable gain amplifier circuit; the differential output end of the operational amplifier is the differential signal output end of the microphone programmable gain amplifier circuit;
two of the second capacitors C2AThe voltage-stabilizing circuit is respectively bridged between the positive pole of the differential input end and the positive pole of the differential output end of the operational amplifier, and between the negative pole of the differential input end and the negative pole of the differential output end of the operational amplifier;
the switched capacitor array comprises a plurality of groups of first switches SW connected in seriesnAnd a fourth capacitance CXnSaid fourth capacitance CXnBy a first switch SWnGating control and second capacitor C2AOr the first capacitor C1 is connected in parallel;
the third capacitor C2BIn series with a second switch at a clock frequency fclkMaking a switched connection at a clock frequency fclkOf said third capacitor C2BThe second switch is used for gating, and two ends of the second switch are respectively connected with the input common-mode voltage and the output common-mode voltage; at clock frequency fclkSecond half period of (C), the third capacitance C2BAnd a second capacitor C2AAnd (4) connecting in parallel.
2. The microphone programmable gain amplifier integrated circuit of claim 1, wherein: the amplifier gain of the programmable gain amplifier is determined by a capacitance ratio, wherein the capacitance ratio is as follows:
wherein,
a fourth capacitor C for all gates in the switched capacitor arrayXiSum of capacitance values of, Kxi1 denotes a fourth capacitance CXiIs gated; kxi0 denotes a fourth capacitance CXiIs not gated.
3. The microphone programmable gain amplifier integrated circuit of claim 1, wherein: the capacitance value of the first capacitor is 20-100 pF.
4. The microphone programmable gain amplifier integrated circuit of claim 1, wherein: the programmable gain amplifier behaves as a high-pass filter with its cut-off frequency fHPComprises the following steps:
wherein f isHPThe cut-off frequency of the high-pass filter.
5. The microphone programmable gain amplifier integrated circuit of claim 4, wherein: the cut-off frequency is less than or equal to 20 Hz.
6. The microphone programmable gain amplifier integrated circuit of claim 1, wherein: the operational amplifier is a two-stage Miller compensated class AB transconductance amplifier.
7. The microphone programmable gain amplifier integrated circuit of claim 6, wherein: the two-stage Miller compensated class AB transconductance amplifier comprises a biasing circuit, a first-stage input amplifying circuit and a second-stage output amplifying circuit;
the bias circuit provides a first bias voltage and a second bias voltage;
the input amplification circuit comprises a zeroth PMOS (P-channel metal oxide semiconductor) tube, a PMOS (P-channel metal oxide semiconductor) differential input geminate transistor, a first load transistor pair and a second load transistor pair, the grid electrode of the PMOS differential input geminate transistor is the differential input end of the AB class transconductance amplifier, and the first load transistor pair is biased at a second bias voltage Vbias; the second pair of load transistors is biased at a common mode feedback voltage;
the PMOS differential input pair transistors comprise a first PMOS transistor and a second PMOS transistor;
the first load transistor pair comprises a first NMOS transistor NM1aAnd a second NMOS tube NM2a；
The second load transistor pair comprises an eleventh NMOS transistor NM1bAnd a twelfth NMOS tube NM2b；
The first output end of the input amplifying circuit, the source electrode of the first PMOS tube and the first NMOS tube NM1aAnd a second NMOS tube NM2aThe drain connection of (1);
the second output end of the input amplifying circuit, the source electrode of the second PMOS tube and the eleventh NMOS tube NM1bAnd a twelfth NMOS tube NM2bThe drain connection of (1);
the drain of the zeroth PMOS is connected to a first level, the source of the zeroth PMOS is connected with the drain of the first PMOS tube and the drain of the second PMOS tube, and the gate of the zeroth PMOS tube is biased at a first bias voltage;
the first NMOS tube NM1aAnd a second NMOS tube NM2aAnd an eleventh NMOS tube NM1bAnd a twelfth NMOS tube NM2bIs connected to a second level;
the output amplifying circuit of the second stage comprises a first output amplifying circuit and a second output amplifying circuit;
the first output amplifying circuit comprises a third PMOS tube, a fifth MOS tube, a third NMOS tube and a fifth NMOS tube;
the first output end of the input amplifying circuit is connected with the grid electrode of the third NMOS tube;
the second output end of the input amplifying circuit is connected with the grid electrode of the fifth NMOS tube;
the drain electrode of the third NMOS tube is connected with the source electrode of the third PMOS tube, the grid electrode of the third PMOS tube and the grid electrode of the fifth PMOS tube;
the drain electrodes of the third PMOS tube and the fifth PMOS tube are connected to a first level;
the source electrodes of the third NMOS transistor and the fifth NMOS transistor are connected to a second level;
the drain electrode of the fifth NMOS tube and the source electrode of the fifth PMOS tube are connected to the first differential output end of the first output amplifying circuit;
a Miller compensation circuit is bridged between the grid electrode and the drain electrode of the fifth NMOS tube;
the second output amplifying circuit comprises a fourth PMOS tube, a sixth MOS tube, a fourth NMOS tube and a sixth NMOS tube;
the first output end of the input amplifying circuit is connected with the grid electrode of the fourth NMOS tube;
the second output end of the input amplifying circuit is connected with the grid electrode of the sixth NMOS tube;
the drain of the sixth NMOS tube is connected with the source of the fourth PMOS tube, the grid of the fourth PMOS tube and the grid of the sixth PMOS tube;
the drain electrodes of the fourth PMOS tube and the sixth PMOS tube are connected to a first level;
the source electrodes of the fourth NMOS transistor and the sixth NMOS transistor are connected to a second level;
the drain electrode of the sixth NMOS tube and the source electrode of the sixth PMOS tube are connected to the second differential output end of the first output amplifying circuit;
and a Miller compensation circuit is connected between the grid electrode and the drain electrode of the sixth NMOS tube in a bridging mode.
8. The microphone programmable gain amplifier integrated circuit of claim 7, wherein: the device also comprises a band-gap reference source and a low-dropout linear regulator;
the band-gap reference source provides reference voltage for the low-dropout linear regulator and provides current bias and common-mode feedback voltage for the two-stage Miller-compensated class AB transconductance amplifier;
the low dropout linear regulator is powered by an off-chip power supply and provides power supply voltage for the transconductance amplifier.
9. The microphone programmable gain amplifier integrated circuit of claim 8, wherein: the voltage of the off-chip power supply is 1.4V, and the power supply voltage of the transconductance amplifier is 1.0V.
10. The microphone programmable gain amplifier integrated circuit of claim 8, wherein: the common mode feedback voltage is 0.5V.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110601670A (en) * | 2019-10-11 | 2019-12-20 | 厦门理工学院 | Microphone programmable gain amplifier integrated circuit |
| CN115412041A (en) * | 2022-10-31 | 2022-11-29 | 成都市安比科技有限公司 | Low-noise fully-differential amplifier comprising common-mode feedback circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110601670A (en) * | 2019-10-11 | 2019-12-20 | 厦门理工学院 | Microphone programmable gain amplifier integrated circuit |
| CN115412041A (en) * | 2022-10-31 | 2022-11-29 | 成都市安比科技有限公司 | Low-noise fully-differential amplifier comprising common-mode feedback circuit |
| CN115412041B (en) * | 2022-10-31 | 2023-02-28 | 成都市安比科技有限公司 | Low-noise fully-differential amplifier comprising common-mode feedback circuit |
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