KR101915979B1

KR101915979B1 - Balanced output rail-to-rail second generation current conveyor

Info

Publication number: KR101915979B1
Application number: KR1020160174637A
Authority: KR
Inventors: 한상현
Original assignee: 주식회사 리딩유아이
Priority date: 2016-12-20
Filing date: 2016-12-20
Publication date: 2018-11-07
Also published as: WO2018117524A3; WO2018117524A2; KR20180071702A

Abstract

A balanced output rail-to-rail second generation current conveyor is initiated. Balanced Output Rail-to-Rail Second Generation Current Conveyors include core blocks and driving blocks. The core block implements rail-to-rail input and output through the upper differential input stage and the lower differential input stage that are commonly connected to the Y- and X-ports, and the current applied by the bias voltage is applied to the Y- And outputs the first driving voltage P_DRV and the second driving voltage N_DRV. The driving block outputs a normal output current through the ZP port in response to the first driving voltage P_DRV and the second driving voltage N_DRV and outputs an inverted output current having a phase opposite to the normal output current to the ZN- Lt; / RTI >

Description

Balanced Output Rail-to-Rail Second Generation Current Conveyor {BALANCED OUTPUT RAIL-TO-RAIL SECOND GENERATION CURRENT CONVEYOR}

The present invention relates to a current conveyor, and more particularly to a balanced output rail-to-rail second generation current conveyor.

Generally, a second generation current conveyor (CCII) is known as a basic component of current-mode signal processing. The second-generation current conveyor is configured such that the X-port that follows the Y-port voltage functions as a voltage follower and the Z terminal that conducts the current that flows into and out of the X terminal functions as a current follower have.

Therefore, as a basic constituent circuit of the current-mode signal processing, researches on the second-generation current conveyor itself and its application circuit have been actively conducted. The Y-port (or voltage input terminal) to which the voltage of the ideal second-generation current conveyor is input has infinite input impedance, the X-port (or current input terminal) to which the current is input has a zero input impedance, The output Z terminal (or current output terminal) has an infinite output impedance.

On the other hand, the class AB driver is used to power large capacitors such as small resistors and / or power amplifiers such as audio amplifiers. These class AB drivers require rail-to-rail output swing, low no-load power, large driver capability, high-speed operation and low distortion.

Korean Patent No. 10-1053254 (2011. 07. 26.) (Current conveyor circuit) Korean Registered Patent No. 10-1152601 (2012. 05. 29.) (Unidirectional Current Detection Circuit Using Second Generation Current Conveyor)

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a balanced output rail-to-rail 2 having a rail-to-rail input / output function, a class AB amplification function, Generation current conveyor.

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In order to realize the object of the present invention described above, a balanced output rail-to-rail second generation current conveyor according to an embodiment includes a core block and a driving block. The core block implements a rail-to-rail input / output through an upper differential input stage and a lower differential input stage commonly connected to the Y-port and the X-port, and controls the current applied by the bias voltage to the voltage of the Y- - port and outputs the first driving voltage P_DRV and the second driving voltage N_DRV. A first bias voltage VBP0 and a second bias voltage VBP1 are applied to the upper differential input terminal and a fourth bias voltage VBN0 and a fifth bias voltage VBN1 are applied to the lower differential input terminal. The driving block outputs a normal output current through the ZP-port in response to the first driving voltage (P_DRV) and the second driving voltage (N_DRV), and outputs an inverted output current having a phase opposite to the normal output current Through the ZN-port. The core block includes: an upper current mirror stage connected to an output terminal of the lower differential input stage and outputting the first driving voltage (P_DRV) by mirroring a current output through the lower differential input stage; A lower current mirror stage connected to an output terminal of the upper differential input stage and outputting the second driving voltage N_DRV by mirroring a current output through the upper differential input stage; And two CMOS transmission gates, and a switching stage disposed between the upper current mirror stage and the lower current mirror stage and performing a class AB driver function. Here, inverted clock terminals of each of the CMOS transmission gates are connected in common to receive a third bias voltage VBP2, and a clock terminal of each of the CMOS transmission gates receives a sixth bias voltage VBN2. The first to sixth bias voltages VBP0, VBP1, VBP2, VBN0, VBN1 and VBN2 are generated by a wide-swing cascode bias circuit.
In one embodiment, the upper differential input stage may compare a voltage of the Y-port with a voltage of the X-port to allow a current applied by a bias voltage to flow through a transistor to which a low voltage is input, The voltage of the Y-port may be compared with the voltage of the X-port to allow a current applied by the bias voltage to flow through the transistor to which the high voltage is input.

In one embodiment, the upper differential input stage comprises two PMOSs connected in series; And two PMOSs serially connected to the two PMOSs and connected in parallel to each other, wherein the first bias voltage VBPO and the second bias voltage VBP1 are applied to the gates of two PMOSs connected in series with each other And the voltage of the Y-port and the voltage of the X-port may be applied to the gates of the two PMOSs connected in parallel with each other.

In one embodiment, the lower differential input stage comprises two NMOSs connected in series; And two NMOSs serially connected to the two NMOSs and connected in parallel to each other, wherein the fourth bias voltage VBN0 and the fifth bias voltage VBN1 are applied to the gates of two NMOSs connected in series, And the voltage of the Y-port and the voltage of the X-port may be applied to the gates of the two NMOSs connected in parallel to each other.

In one embodiment, the upper current mirror stage and the lower current mirror stage may convert a voltage difference between a signal applied through the Y-port and a signal applied through the X-port into a current.

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In one embodiment, the switching stage may adjust the bias current of the upper current mirror stage and the bias current of the lower current mirror stage.

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In one embodiment, the switching stage may control the voltage level of the output terminal of the upper current mirror stage and the voltage level of the output terminal of the lower current mirror stage.

In one embodiment, the switching stage may have a rail-to-rail output structure in which the width of the output voltage covers the supply voltage.

In one embodiment, the upper current mirror stage may comprise a plurality of PMOSs, and the lower current mirror stage may comprise a plurality of NMOSs.

In one embodiment, the core block includes: a first capacitor having one end connected to the upper current mirror stage and the other end connected to the X-port to stabilize the frequency; And a second capacitor having one end connected to the lower current mirror stage and the other end connected to the X-port to stabilize the frequency.

In an exemplary embodiment, the upper differential input stage may include a plurality of PMOSs, and the lower differential input stage may include a plurality of NMOSs.

In one embodiment, the driving block includes: a first driver for controlling a voltage applied to the X-port in response to the first driving voltage (P_DRV) and the second driving voltage (N_DRV); A second driver for controlling a normal output current output through the ZP-port in response to the first driving voltage (P_DRV) and the second driving voltage (N_DRV); A third driver for outputting a third driving voltage P_DRV1 in response to the second driving voltage N_DRV and outputting a fourth driving voltage N_DRV1 in response to the first driving voltage P_DRV; A fourth driver for receiving the third driving voltage (P_DRV1) and the fourth driving voltage (N_DRV1); And a fifth driver that is mirrored by the fourth driver and outputs an inverted output current through the ZN-port.

In one embodiment, the PMOSs included in the first driver, the second driver, the third driver, the fourth driver, and the fifth driver have the same gate area, and the first driver, the second driver And the NMOSs included in the third driver, the fourth driver, and the fifth driver may have the same gate area.

In one embodiment, the steady output current and the inverted output current may be inverses of each other.

In one embodiment, the core block may further include a bias circuit stage that generates the bias voltage.

In one embodiment, to implement a voltage-to-current converter, an X-resistor RX is placed between the common-mode terminal to which the common-mode voltage is applied and the X-port, and the Y- And a normal output current defined by a relationship between the input voltage and the X-resistor (RX) is output through the ZP-port and is defined by a relationship between the input voltage and the X-resistor (RX) An inverted output current may be output through the ZN-port.

In one embodiment, to implement a voltage amplifier, the Y-port is connected to the terminal to which the input voltage is applied, the common mode voltage is connected to the X-port via the X-resistor RX, Port connected to the ZP-port via a resistor RZP and connected to the ZN-port via a ZN-resistor RZN, and the input voltage, the X-resistor RX and the ZP- ), And a negative voltage defined by a relationship between the input voltage, the X-resistor (RX) and the ZN-resistor (RZN) Can be output via the ZN-port.

In one embodiment, to implement a current-to-voltage converter, a ZP-resistor (RZP) is placed between the ZP-port and the Y-port, and a ZN-resistor Port is connected to a terminal to which an input voltage is applied, an input current is applied to the X-port, and the input current and the ZP-resistance (RZP) A polarity voltage is output through the ZP-port, and a negative voltage defined by the relationship between the input current and the ZN-resistor RZN can be output through the ZN-port.

In one embodiment, to implement a current amplifier, a Y-resistor RY is disposed between a terminal to which an input current is applied and a common mode terminal to which a common mode voltage is applied, and between the common mode terminal and the X- Port is connected to a terminal to which an input current is applied and is defined by a relationship between the input current, the X-resistance RX and the Y-resistance RY. And the inverted output current defined by the relationship between the input current, the X-resistor (RX) and the Y-resistor (RY) is output through the ZN-port Can be output.

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These balanced output rail-to-rail second-generation current conveyors enable rail-to-rail input and output capability, class AB amplification, and two current output functions that are opposite to each other.

1 is a diagram showing a bias circuit block.
2 is a circuit diagram of a bias circuit block.
3 is a graph for explaining normal bias voltages generated in the bias circuit block.
4 is a graph for explaining the reverse bias voltages generated in the bias circuit block.
5 is a symbol representing a core block.
6 is a symbol representing the first output driver among the drivers of the second generation current conveyor.
7 is a circuit diagram of the first output driver.
8 is a symbol representing the second output driver among the drivers of the current conveyor.
9 is a circuit diagram of the second output driver among the drivers of the current conveyor.
10 is a symbol representing a driving block among the drivers of the current conveyor.
11 is a circuit diagram of the driving block.
12 is a symbol representing a balanced output rail-to-rail second generation current conveyor (hereinafter referred to as BORRCC II).
13 is a configuration diagram for explaining a common mode voltage supply.
14 is a diagram for explaining an implementation of a fully balanced differential rail-to-rail second generation current conveyor (hereinafter referred to as FBDRRCC II).
15 is a circuit diagram for explaining a balanced output rail-to-rail second generation current conveyor according to an embodiment of the present invention.
16 is a graph for explaining the rail-to-rail input.
17 is a graph for explaining drain-current versus drain-to-source voltage characteristics corresponding to current mirrors.
18 is a graph for explaining the input / output waveform of the second output current-to-rail current conveyor of FIG. 15;
19 is a graph for explaining current characteristics of the MP10 and MN10 provided in the first driver.
20 is an equivalent circuit diagram for explaining features of the second generation current conveyor.
21 is a configuration diagram of a voltage-current converter using BORRCCII according to the present invention.
22 is a graph for explaining the operation of the voltage-current converter shown in Fig.
23 is a configuration diagram of a voltage amplifier using BORRCC II according to the present invention.
24 is a graph for explaining the operation of the voltage amplifier shown in FIG.
25 is a configuration diagram of a current-voltage converter using BORRCCII according to the present invention.
26 is a graph for explaining the operation of the current-voltage converter shown in Fig.
27 is a configuration diagram of a current amplifier using BORRCC II according to the present invention.
FIG. 28 is a graph for explaining the operation of the current amplifier shown in FIG. 27; FIG.
FIG. 29 is a configuration diagram of FBDRRCC II using BORRCC II according to two inventions. FIG.
30 shows the symbols of FBDRRCCII.
31 is a configuration diagram of a fully differential voltage-current converter using FBDRRCC II according to the present invention.
FIG. 32 is a graph for explaining the operation of the fully differential voltage-current converter shown in FIG. 31; FIG.
33 is a configuration diagram of a fully differential voltage amplifier using FBDRRCC II according to the present invention.
34 is a graph for explaining the operation of the fully differential voltage amplifier shown in Fig.
FIG. 35 is a configuration diagram of a fully differential current-voltage converter using FBDRRCC II according to the present invention.
FIG. 36 is a graph for explaining the operation of the fully differential current-voltage converter shown in FIG.
37 is a configuration diagram of a fully differential current amplifier using FBDRRCC II according to the present invention.
FIG. 38 is a graph for explaining the operation of the fully differential current amplifier shown in FIG. 37; FIG.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in more detail with reference to the accompanying drawings. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Like reference numerals are used for like elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged to illustrate the present invention in order to clarify the present invention.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. The singular expressions include plural expressions unless the context clearly dictates otherwise.

In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Also, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

First, the names and symbols of the circuits mentioned in this specification will be described.

1 is a diagram showing a bias circuit block. 2 is a circuit diagram of a bias circuit block. 3 is a graph for explaining normal bias voltages generated in the bias circuit block. 4 is a graph for explaining the reverse bias voltages generated in the bias circuit block.

1 to 4, the bias circuit block BIAS includes a plurality of PMOSs and a plurality of NMOSs. The bias circuit block BIAS receives a reference current IREF from the outside, A first normal bias voltage VBP0, a second normal bias voltage VBP1 and a third normal bias voltage VBP2 and supplies a first inverted bias voltage VBN0 and a second inverted bias voltage VBN2 supplied as a bias voltage to the NMOS, VBN1 and the third reverse bias voltage VBN2.

In this embodiment, VDD, which is a relatively high power supply voltage, is applied to the PMOSs, and VSS, which is a relatively low power supply voltage, is applied to the NMOSs. In the PMOS, a terminal connected to a relatively high voltage is referred to as a source, a terminal to which a control voltage is applied is referred to as a gate, and the remaining terminal is referred to as a drain. Also, a terminal connected to a relatively low voltage in the NMOS is referred to as a source, a terminal to which a control voltage is applied is referred to as a gate, and the remaining terminal is referred to as a drain.

The source of MN0 is connected to VSS, the gate and drain are connected in common and connected to the source of MN1. The source of MN1 is connected to the drain of MN0, and the gate and the drain are connected in common to a terminal to which reference current IREF is applied. The source of MN2 is connected to VSS, the gate is connected to the gate of MN0, and the drain is connected to the source of MN3. The source of MN3 is connected to the drain of MN2, the gate is connected to the gate of MN1, and the drain is connected to the drain of MP2. The source of MN4 is connected to VSS, the gate is connected to the gate of each of MN0 and MN2, and the drain is connected to the source of MN5. The source of MN5 is connected to the drain of MN4, the gate is connected to the gate of each of MN1 and MN3, and the drain is connected to the drain of MP3. In this embodiment, MN0, MN1, MN2, MN3, MN4 and MN5 define a first current mirror connected in a cascode manner. MN0 and MN1 define the input of the first current mirror MN2 and MN3 define a first output of the first current mirror MN4 and MN5 define a second output of the first current mirror .

The source of MP0 is connected to VDD, the gate is connected to the drain of MP1, and the drain is connected to the source of MP1. The source of MP1 is connected to the drain of MP0, the gate is connected to the gate of MP3, and the drain is connected to the source of MP2. The source of MP2 is connected to the drain of MP1 and the gate of MP0, and the gate and the drain are commonly connected to the drain of MN3. The source of MP3 is connected to VDD, the gate is connected to the gate of MP1, and the drain is connected to the drain of MN5. The source of MP4 is connected to VDD, the gate is connected to the gate of MP0, and the drain is connected to the source of MP5. The source of MP5 is connected to the drain of MP4, the gate is connected to the gate of MP3, and the drain is connected to the drain of MN8. The source of MP6 is connected to VDD, the gate is connected to the gate of each of MP0 and MP4, and the drain is connected to the source of MP7. The source of MP7 is connected to the drain of MP6, the gate is connected to the gate of each of MP3 and MP5, and the drain is connected to the drain of MN9. In this embodiment, MP0, MP1, MP4, MP5, MP6 and MP7 define a second current mirror connected in a cascode manner. MP0 and MP1 define an input of the second current mirror, MP4 and MP5 define a first output of the second current mirror, and MP6 and MP7 define a second output of the second current mirror . The bias circuit block including the first and second current mirrors defines a wide-swing cascode bias circuit.

Here, a first normal bias voltage VBP0 is generated through the gates of MP0, MP4 and MP6, a second normal bias voltage VBP1 is generated through the gates of MP1, MP3, MP5 and MP7, A third normal bias voltage VBP2 is generated through the gate.

The source of MN6 is connected to VSS, the gate is connected to the drain of MN7, and the drain is connected to the source of MN7. The source of MN7 is connected to the drain of MN6, the gate is connected to the gate of MN9, and the drain is connected to the source of MN8 and the gate of MN6. The drain and gate of MN8 are connected in common to the drain of MP5, and the source is connected to the drain of MN7. The source of MN9 is connected to VSS, the gate is connected to the gate of MN7, and the drain is connected to the drain of MP7.

Here, a first reverse bias voltage VBN0 is generated through the gate of MN6, a second reverse bias voltage VBN1 is generated through the gates of MN7 and MN9, and a third reverse bias voltage VBN2 ) Is generated.

The normal bias voltage VBP applied to the bias voltage of the PMOS, that is, the first normal bias voltage VBP0, the second normal bias voltage VBP1, and the third normal bias voltage VBP2 are precisely set in the actual circuit design , And can be roughly generated by Equation 1 as follows.

[Equation 1]

VBP0 = VDD - (Vthp * 1)

VBP1 = VDD - (Vthp * 2)

VBP2 = VDD - (Vthp * 3)

Here, it is assumed that Vthp is about 0.5V to 0.8V as a threshold voltage of the PMOS.

The first normal bias voltage VBP0, the second normal bias voltage VBP1 and the third normal bias voltage VBP2 generated in the bias circuit block BIAS are as shown in FIG.

On the other hand, the reverse bias voltage VBN applied to the bias voltage of the NMOS, that is, the first reverse bias voltage VBN0, the second reverse bias voltage VBN1, and the third reverse bias voltage VBN2, But it can be roughly generated by the following Equation (2).

[Equation 2]

VBN0 = VSS (0V) + (Vthn * 1)

VBN1 = VSS (0V) + (Vthn * 2)

VBN2 = VSS (0V) + (Vthn * 3)

Here, it is assumed that Vthn is about 0.4V to 0.7V as a threshold voltage of the NMOS.

The first inverted bias voltage VBN0, the second inverted bias voltage VBN1 and the third inverted bias voltage VBN2 generated in the bias circuit block BIAS are as shown in FIG.

As shown in Fig. 3, the magnitude of the voltage in the order of the first normal bias voltage VBP0, the second normal bias voltage VBP1, and the third normal bias voltage VBP2 becomes smaller, Likewise, the magnitude of the voltage increases in the order of the first reverse bias voltage VBN0, the second reverse bias voltage VBN1, and the third reverse bias voltage VBN2.

In this embodiment, the reference current IREF is about several uA to several tens uA, and the channel width and the channel length for generating the gate area of all the PMOSs are the same, and the channel width And the channel length are the same. Generally, when the channel lengths of the PMOS and the NMOS are made the same, the channel width of the PMOS is selected to be about three times or more than the channel width of the NMOS. The channel length of MP3 is about 4 to 6 times longer than the remaining PMOS gate area. The channel length of MN9 is about 4 to 6 times longer than the remaining NMOS gate area.

5 is a symbol representing a core block.

As shown in FIG. 5, the core block CORE has a function of outputting a gate voltage of a rail-to-rail input stage and an AB class driver.

The core block (CORE) may be designed as an operational transconductance amplifier (OTA) or an operational amplifier (Op-Amp). Both amplification circuits are circuits that amplify and output the difference of the input, and have a large voltage gain (for example, several thousands to tens of thousands) and a high input resistance.

In the case of OTA, when the capacitive load is driven, the output voltage becomes close to an ideal voltage controlled current source, so a high output resistance is a desirable characteristic.

On the other hand, in order to drive a resistive load, the output resistance of the Op-Amp must be low to avoid a loading effect. This output resistance is designed to be very low and operate as a voltage controlled voltage source.

6 is a symbol representing the first output driver D0 among the drivers of the second generation current conveyor. 7 is a circuit diagram of the first output driver D0.

Referring to Figs. 6 and 7, the first output driver D0 has a normal output voltage buffer for voltage feedback.

The first output driver D0 is composed of a series-connected MP10 and MN10. MP10 has a source to which VDD is applied, a gate to which the first driving voltage (P_DRV) is applied, a drain of MN10, and a drain connected to the X-port. MN10 has a source to which VSS is applied, a gate to which the second driving voltage N_DRV is applied, and a drain connected to the drain of MP10 and a X-port.

8 is a symbol representing the second output driver D1 among the drivers of the current conveyor. 9 is a circuit diagram of the second output driver D1.

Referring to Figs. 8 and 9, the second output driver D1 has a normal output voltage buffer for voltage feedback and a ZP-port.

The second output driver D1 constitutes the MP10 and MN10 connected in series and the MP11 and MN11 connected in series.

MP10 has a source to which VDD is applied, a gate to which the first driving voltage P_DRV is applied, a source of MN10, and a drain connected to the X-port. MN10 has a source to which VSS is applied, a gate to which the second driving voltage N_DRV is applied, and a drain connected to the drain of MP10 and a X-port.

MP11 has a source to which VDD is applied, a gate commonly connected to the gate of MP10 to which a first driving voltage P_DRV is applied, a source of MN11, and a drain connected to the ZP-port. MN11 has a source to which VSS is applied, a gate commonly connected to the gate of MN10 and to which the second driving voltage N_DRV is applied, and a drain connected to the drain and ZP-port of MP11.

10 is a symbol representing the driving block D2 among the drivers of the current conveyor. 11 is a circuit diagram of the driving block D2.

Referring to Figs. 10 and 11, the driving block D2 has a normal output voltage buffer for voltage feedback, a ZP-port, and a ZN-port.

The driving block D2 is composed of MP10, MN10, MP11, MN11, MP12, MN12, MP13, MN13, MP14 and MN14.

MP12 has a source to which VDD is applied, a gate commonly connected to the gate of MP10 to which a first driving voltage P_DRV is applied, and a drain connected to the source of MN13. MN12 has a source to which VSS is applied, a gate commonly connected to the gate of MN10 to which a second driving voltage N_DRV is applied, and a source connected to the drain of MP13.

MP13 has a source to which VDD is applied, a gate connected to a source of MN12 in common and a drain. MN13 has a source to which VSS is applied, a source connected in common to the drain of MP12, and a gate.

MP14 has a source to which VDD is applied, a gate connected to the gate of MP13, and a drain connected to the ZN-port. MN14 has a source to which VSS is applied, a gate connected to the gate of MN13, and a drain connected to the ZN-port.

12 is a symbol representing a balanced output rail-to-rail current conveyor (hereinafter referred to as BORRCC II).

As shown in FIG. 12, a balanced output rail-to-rail second generation current conveyor (BORRCCII) is implemented by connecting the core block CORE and the driving block D2 in series.

13 is a configuration diagram for explaining a common mode voltage supply.

As shown in FIG. 13, the common mode voltage generator (VCM Generator) includes a functional block of a combination of a core block (CORE) and a first output driver (D0).

The reference voltage Vref is generated at a ratio of the first resistor R1 and the second resistor R2 connected in series between VDD and GND and applied to the Y-port of the core block CORE. When the reference voltage Vref is applied to the Y-port of the core block CORE, an ideal common mode voltage (VCM) having a very low output impedance is generated through the X-port outputting the same voltage do.

FIG. 14 is a diagram for explaining an implementation of a fully balanced differential rail-to-rail current conveyor (hereinafter referred to as FBDRRCC II).

Referring to FIG. 14, two BORRCC IIs are arranged on the upper and lower sides to define a fully balanced differential rail-to-rail second generation current conveyor (hereinafter referred to as FBDRRCC II).

The Y-port of BORRCC II arranged on the upper side defines the YP port of FBDRRCC II, the X-port of BORRCC II arranged on the upper side defines the XP-port of FBDRRCC II, and the Y port of BORRCC II arranged on the lower side defines FBDRRCC II Port, and the X-port of BORRCC II located on the lower side defines the XN-port of FBDRRCC II.

The ZP-port of BORRCC II located on the upper side and the ZN-port of BORRCC II disposed on the lower side are connected to each other to define the ZP-port of FBDRRCC II. The ZN-port of BORRCC II located on the upper side and the ZP-port of BORRCC II disposed on the lower side are connected to each other to define the ZN-port of FBDRRCC II.

The ZP-port and ZN-port of the FBDRRCC II output only the differential components of the voltage or current of the input ports of the upper BORRCC II and the lower BORRCC II, respectively.

15 is a circuit diagram for explaining a balanced output rail-to-rail second generation current conveyor according to an embodiment of the present invention.

Referring to FIG. 15, a balanced output rail-to-rail current conveyor according to an embodiment of the present invention includes a core block and a driving block D2 do.

The core block CORE includes an upper differential input terminal 110, a lower differential input terminal 120, an upper current mirror stage 130, a lower current mirror stage 140, a switching stage 150, a first capacitor C1, 2 capacitor C2 and receives VBP0, VBP1 and VBP2 as the bias voltages of the PMOS devices from the bias circuit block (shown in Figs. 1 and 2), VBN0, VBN1 and VBN2 as bias voltages of the NMOS devices . The illustration of the bias circuit block in the balanced output rail-to-rail second generation current conveyor shown in Fig. 15 has been omitted.

The core block CORE implements a rail-to-rail input / output through an upper differential input stage 110 and a lower differential input stage 120 that are commonly connected to the Y-port and the X-port, And outputs the first driving voltage P_DRV and the second driving voltage N_DRV to the driving block D2 by mirroring the current applied by the bias voltage based on the voltage of the driving voltage V_DRV.

The upper differential input stage 110 is composed of MP2 and MP3 connected in parallel with MP0 and MP1 connected in series. MP0 has a source to which VDD is applied, a gate to which VBP0 is applied, and a drain connected to the source of MP1. MP1 has a source connected to the drain of MP0, a gate to which VBP1 is applied, a source of MP2 and a drain connected to the source of MP3. MP2 has a source coupled to the drain of MP1, a gate coupled to the Y-port, and a drain coupled to the lower current mirror stage 140. MP3 has a source coupled to the drain of MP1, a gate coupled to the X-port, and a drain coupled to the lower current mirror stage 140. MP2 and MP3 are responsible for input, and compare the voltage of the Y-port with the voltage of the X-port to flow the tail current (Ip) applied by the bias voltage to the gate to which the lower voltage is input do. Here, the range of the operable input signal voltage (common mode voltage) is about 2.5V to 0V when VDD is assumed to be about 3.3V.

The lower differential input stage 120 consists of MN0 and MN1 connected in series and MN2 and MN3 connected in parallel. MN0 has a drain connected to the source of MN1, a gate to which VBN0 is applied, and a source to which VSS is applied. MN1 has a source connected to the source of MN2 and a drain connected to the source of MN3, a gate to which VBN1 is applied, and a source connected to the drain of MN0. MN2 has a drain coupled to the upper current mirror stage 130, a gate coupled to the Y-port, and a source coupled to the drain of MN1. MN3 has a drain connected to the upper current mirror stage 130, a gate connected to the X-port, and a source connected to the drain of MN1. MN2 and MN3 take charge of the input, and compare the voltage of the Y-port with the voltage of the X-port to flow the current (In) applied by the bias voltage toward the input gate. Here, the range of the operable input signal voltage (common mode voltage) is about 0.7V to 3.3V when VDD is assumed to be about 3.3V.

Since the upper differential input stage 110 and the lower differential input stage 120 are disposed as an input stage of the current conveyor, a rail-to-rail input can be realized. That is, the current (Ip, In) can be supplied so that the range of the input voltage (Common Mode Voltage) covers the entire range of the power supply voltage (VDD) when the power source is 3.3V. The range of the input voltage is shown in FIG.

16 is a graph for explaining the rail-to-rail input.

As shown in FIG. 16, the rail-to-rail input covers a range of the input signal from 0 V to VDD, so that a wider range of inputs is obtained when the conventional circuit receives the upper input or the lower input It has the advantage of operating on voltage.

Referring back to FIG. 15, the upper current mirror stage 130 consists of MP4, MP5, MP6, and MP7 to define a current mirror. MP4 has a source to which VDD is applied, a drain of MP5, a gate connected to the gate of MP6, and a drain connected to the source of MP5. Further, the drain of MP4 is connected to the source of MN3 of the lower differential input terminal 120. [ MP5 has a source connected to the drain of MP4, a gate connected to the gate of MP7, and a drain connected to the gate of MP4. Further, the source of MP5 is connected to the source of MN3 of the lower differential input stage 120. [ MP6 has a source to which VDD is applied, a drain of MP5, a gate connected to the gate of MP4, and a drain connected to the source of MP7. Further, the drain of MP6 is connected to the source of MN2 of the lower differential input terminal 120. [ MP7 has a source connected to the drain of MP6, a gate connected to the gate of MP5, a driving block D2 and a drain connected to the switching stage 150. Here, MP5 and MP7 are biased with VBP1 voltage, and the bias voltage between MP4 and MP6 has a circuit characteristic in which a drain voltage of MP5 is applied.

If the gate area of MP4 is equal to the gate area of MP6, and the gate area of MP5 is equal to the gate area of MP7, the current flowing through MP6 and MP7 is the same as the current flowing through MP4 and MP5. At this time, the saturation voltage of MP5 is higher than the threshold voltage (Vth) of MP4, thereby supplying current to the drain of MP7. Therefore, the range of the operable voltage is wider than the current mirror of the general structure.

At this time, if the current is applied to the drains of MP4 and MP6 at different values due to the difference of the input voltages of the lower differential input terminal 120, the final output current I (MP7) flowing through the MP7 becomes the bias current It is determined by the current of ± @ IN. Here, @ denotes a ratio of a current (In) to a difference value of the input voltage obtained from the upper differential input terminal 110 and the lower differential input terminal 120, which are the input stages of the current conveyor.

The lower current mirror stage 140 consists of MN4, MN5, MN6 and MN7 to define a current mirror. MN4 has a drain connected to the source of MN5, a gate connected to the gate of MN6, and a source to which VSS is applied. Further, the drain of MN4 is connected to the source of the MP3 of the upper differential input stage 110. [ MN5 has a drain connected to the switching stage 150, a gate connected to the gate of MN7, and a source connected to the drain of MN4. Further, the source of MN5 is connected to the source of MP2 of the upper differential input stage 110. [ MN6 has a drain connected to the source of MN7, a gate connected to the gate of MN4, and a source to which VSS is applied. MN7 has a drain connected to the switching node 150, a gate connected to the gate of MN5, and a source connected to the drain of MN6. Further, the drain of MN7 is connected to the source of MP2 of the upper differential input stage 110. [ Here, MN5 and MN7 are biased with a VBN1 voltage, and bias voltages of MN4 and MN6 have a circuit characteristic in which a source voltage of MN5 is applied.

If the gate area of MN4 is equal to the gate area of MN6 and the gate area of MN5 is equal to the gate area of MN7, the current flowing through MN6 and MN7 is the same as the current flowing through MN4 and MN5. At this time, the saturation voltage of MN5 becomes higher than the threshold voltage (Vth) of MN4, thereby supplying current to the source of MN7. Therefore, the range of the operable voltage is wider than the current mirror of the general structure.

At this time, if the current is applied to the sources of MN4 and MN6 at different values due to the difference of the input voltages of the upper differential input terminal 110, the final output current I (MN7) flowing through MN7 becomes equal to the bias current It is determined by the current of ± @ IP. Here, @ denotes the ratio of the current Ip to the difference value of the input voltage obtained from the upper differential input terminal 110 and the lower differential input terminal 120, which are the input stages of the current conveyor.

In this embodiment, the upper current mirror stage 130 and the lower current mirror stage 140 employ a High-compliance current mirror.

17 is a graph for explaining drain-current versus drain-to-source voltage characteristics corresponding to current mirrors.

Referring to FIG. 17, the high-compliance current mirror has a wide Vds (drain-source voltage) in comparison with conventional triple cascode, regulated cathode, Wilson cathode method, . Thus, a wide voltage swing with a current source is possible.

In addition, the variation of Id (drain current) with respect to Vds is smaller than that of a simple scheme which is a conventional structure of the high-compliance current mirror.

15, one end of the first capacitor C1 is connected to a node between MP6 and MP7 of the upper current mirror stage 130, and one end of the second capacitor C2 is connected to a node between the MP6 and the MP7 of the lower current mirror stage 130 And is connected to a node between MN6 and MN7. The other end of the first capacitor C1 and the other end of the second capacitor C2 are connected in common to the X-port.

The first capacitor C1 and the second capacitor C2 are frequency stabilized capacitors inserted to provide a phase margin in case the core block CORE is operated with OTA AMP.

The switching stage 150 includes a CMOS transmission gate composed of MP8 and MN8 and a CMOS transmission gate composed of MP9 and MN9 and is disposed between the upper current mirror stage 130 and the lower current mirror stage 140 . Due to the voltage difference between the source and the drain of MP8, MN8, MP9 and MN9 biased with VBN2 and VBP2, the switching stage 150 has a driver type with a Class AB amplification structure.

Due to the current mirror structure of the upper current mirror stage 130 and the lower current mirror stage 140, the switching stage 150 has a rail-to-rail output (rail) in which the width of the output voltage is able to cover all of the supply voltage -to-rail output) structure.

18 is a graph for explaining the input / output waveform of the second output current-to-rail current conveyor of FIG. 15; In particular, a schematic waveform for the voltage input signal applied to the Y-port or the voltage output signal outputted through the ZP-port, the first driving voltage P_DRV and the second driving voltage N_DRV is shown.

As shown in FIG. 18, in the section A, the NMOSs MN10, MN11 and MN12 shown in FIG. 15 are driven weakly but kept in a cut-off state by the second driving voltage N_DRV. However, the first driving voltage P_DRV controls the voltage of the ZP-port by driving the PMOSs MP10, MP11 and MP12 shown in FIG.

In the section B, the PMOSs MP10, MP11 and MP12 shown in FIG. 15 are driven weakly but kept in a cut-off state by the first driving voltage P_DRV. However, the second driving voltage N_DRV controls the voltage of the ZP-port by driving the NMOSs MN10, MN11 and MN12 shown in FIG.

The signal driving of the section A or the signal driving of the section B is a typical driving voltage waveform of the class AB driver.

Referring again to FIG. 15, the driving block D2 includes a first driver 210, a second driver 220, a third driver 230, a fourth driver 240, and a fifth driver 250 Port through the ZP-port in response to the first driving voltage P_DRV and the second driving voltage N_DRV, and outputs the inverted output current through the ZN-port.

The first driver 210 is composed of the MP10 and the MN10 connected in series. MP10 has a source to which VDD is applied, a gate connected to the upper current mirror stage 130, and a drain connected to the drain and X-port of MN10. MN10 has a source to which VSS is applied, a gate connected to the lower current mirror stage 140, and a drain connected to the drain of the MP10 and an X-port. The first driver 210 serves to connect the output to the X-port of the input stage according to the structure of the second generation current conveyor.

19 is a graph for explaining current characteristics of the MP10 and MN10 provided in the first driver.

As shown in FIG. 19, the output current I _{MP of the MP} 10 is controlled by the first driving voltage P_DRV, which is the output of the upper current mirror stage 130. In the section where the output current (I _MP ) is larger than +4J, the MP10 operates in the linear mode. In the section smaller than +4J, the MP10 has the nonlinear characteristic. (cut-off), and the current can not be driven any more. Here, J is the quiescent current of the driven MOSFET, which means the standby mode current (i.e., the value of the current flowing before the operation in the standby state). AB driver (Class AB driver) is designed by defining a section with respect to the bias voltage until the gate voltage of the driver MOS exceeds the threshold voltage and reaches the linear operation mode in a period of about 4J.

On the other hand, the output current I _{MN of the MN} 10 is controlled by the second driving voltage N_DRV, which is the output of the lower current mirror stage 140. In the section where the output current I _MN is smaller than -4 J, the _{MN 10} operates in a linear mode. In the section larger than -4 J, the MN 10 has a nonlinear characteristic. In the section longer than + 4 J, cut-off) and the current can not be driven any more.

Therefore, since the current values of MP10 and MN10 are present in the zero current period (ie, the non-signal interval) in which there is no signal, they have the smallest current value in the operating mode. Therefore, this output buffer stage is referred to as AB class AB stage). A driver having such a function is referred to as an AB class driver. In addition, by using the current conveyor with AB class driver, it is possible to reduce the consumption current of the silent screen, adjust the size of the output driver appropriately to suit the application, and realize the low power operation characteristic and drive the large current .

Referring again to FIG. 15, the second driver 220 includes the MP11 and the MN11 connected in series in the same manner as the first driver 210. MP11 has a source to which VDD is applied, a gate connected to the gate of the MP10 of the first driver 210, and a drain connected to the drain of the MN11 and a ZP-port. MN11 has a source to which VSS is applied, a lower current mirror stage 140 and a gate connected to the gate of MN10, and a drain connected to the drain and ZP-port of MP11. Port of the differential input stage of the upper differential input stage 110 and the differential input stage of the lower differential input stage 120. The second driver 220 is connected to the ZP port for output driving do.

The third driver 230 is composed of MP12 and MN12. The gate of MP12 is connected to the gate of MP11, and the gate of MN12 is connected to the gate of MN11. VDD is applied to the source of MP12, and VSS is applied to the source of MN12.

The fourth driver 240 is composed of MP13 and MN13. The drain of the MP13 is connected to the drain of the MN12 of the third driver 230 and the drain of the MN13 is connected to the drain of the MP12 of the third driver 203. [ VDD is applied to the source of MP13, and VSS is applied to the source of MN13.

The fifth driver 250 is composed of MP14 and MN14. The gate of the MP14 is connected to the gate of the MP13, the drain of the MP13, and the drain of the MN12 of the third driver 230. The gate of the MN14 is connected to the gate of the MN13, do. VDD is applied to the MP14 source, and VSS is applied to the source of the MN14. The drain of the MP14 and the drain of the MN14 are commonly connected to the ZN-port.

The third driver 230 and the fourth driver 240 have a reverse current mirror structure for driving the ZN-port of the fifth driver 250.

The same current as the PMOS that was used to drive the ZP-port flows in MP12, and this current is mirrored to MN13 to drive MN14.

In addition, the same current as the NMOS that was used to drive the ZP-port flows in the MN 12, and this current is mirrored in the MP 13 to drive the MP 14.

Through this inversion current mirror, the ZN-port of the fifth driver 250 has an output current or output voltage that is completely in phase with the ZP-port.

All the PMOSs of the first driver 210, the second driver 220, the third driver 230, the fourth driver 240 and the fifth driver 250 have the same gate area And the NMOS is also designed to have the same gate area. In particular, for correct operation of the current mirror, each of the PMOSs and NMOSs can be set to use the same value for both the width and the length of the channel generating the gate area.

A block completed with the configuration from the upper differential input terminal 110 to the fifth driver 250 is defined as a 'balanced output rail-to-rail current converter' (BORRCCII).

The above BORRCC II satisfies the features of the second generation current conveyor (CC).

20 is an equivalent circuit diagram for explaining features of the second generation current conveyor.

20, a second-generation current conveyor CC has a 100% mirrored current (i0) flowing to the X-port low impedance input, the Y-port high impedance input, and the X- Or Z + port) and an inverting current output through the ZN-port (or Z-port).

That is, the second-generation current conveyor follows the voltage from the Y-port to the X-port according to the impedance characteristic, and if positive, the Z-port follows the current in the same direction as the current flow in the X-port. On the other hand, in the case of a negative electrode, the Z-port follows the current in the direction opposite to the current flow direction of the X-port.

In addition, the second-generation current conveyor follows the voltage from the Y-port to the X-port according to the impedance characteristics as shown in Table 1 below.

[Table 1]

Therefore, the current I _{Y of the Y} -port, the voltage V _{X of the X} -port, and the current I _Z of the Z-port can be expressed by the following Equation 3.

[Equation 3]

Hereinafter, various application circuits using BORRCC II according to an embodiment of the present invention will be described.

FIG. 21 is a configuration diagram of a voltage-current converter using BORRCC II according to the present invention, and FIG. 22 is a graph for explaining the operation of the voltage-current converter shown in FIG.

As shown in FIGS. 21 and 22, in order to implement a voltage-to-current converter for converting a voltage into a current, a common mode voltage (VCM) and an X-resistor (RX) are connected in series to the X-port of BORRCC II .

When the input voltage (VIN) is supplied to the Y-port, the same voltage as the supplied input voltage (VIN) is output to the X-port by the second-generation current-current (CC) formula. That is, V (VIN) = V (X).

The voltage difference between the common mode voltage (VCM) and the X-port causes the current (ix) to be generated by the X-resistor (RX). This current (ix) is mirrored by the current of iZPO in the ZP-port and the current of iZNO is mirrored in the ZN-port. Therefore, the input voltage VIN is converted into a current output such as ZPO and ZNO.

That is, the voltage is converted into the current in accordance with the following expression (4).

[Equation 4]

I (ZPO) = VIN * (1 / RX)

I (ZNO) = -VIN * (1 / RX)

The value at which the input voltage VIN is converted into the current has a relation proportional to the reciprocal (1 / RX) of the X-resistor RX. The relationship between the voltage input and the current output is shown in FIG.

FIG. 23 is a configuration diagram of a voltage amplifier using BORRCC II according to the present invention, and FIG. 24 is a graph for explaining the operation of the voltage amplifier shown in FIG.

23 and 24, in order to implement a voltage amplifier for amplifying the voltage, the Y-port of BORRCC II is connected to the terminal to which the input voltage VIN is applied, and the X-port of BORRCC II and the common mode voltage (RX) is arranged between the terminals to which the common mode voltage (VCM) is applied and the ZP-resistor (RZP) is arranged between the terminals to which the common mode voltage (VCM) is applied and the ZP port of the BORRCCII, The ZN-resistor RZN is disposed between the port and the terminal to which the common mode voltage VCM is applied.

The input voltage VIN is supplied to the Y-port which is a voltage input port and the voltage of the voltage-current converter to which the same voltage as the input voltage VIN is supplied is converted into a current, When the ZP-resistor (RZP) and ZN-resistor (RZN), which can set the voltage gain to the ZP-port and ZN- port, are connected between the terminals to which the common mode voltage (VCM) is applied, .

When the ZP-resistor (RZP) is connected between the ZPO terminal and the terminal to which the common mode voltage (VCM) is applied and the ZN-resistor (RZN) is connected between the ZNO terminal and the common mode voltage (VCM) The voltage has a relationship expressed by the following equation (5).

[Equation 5]

V (ZPO) = VIN * (RZP / RX)

V (ZNO) = -VIN * (RZN / RX)

Therefore, the output voltage V (ZPO) through the ZPO terminal and the output voltage V (ZNO) through the ZNO terminal are the X-resistor RX and the ZP-resistor RZP for the input voltage VIN, It can be seen that the voltage gain (or the amplification factor) is set according to the ratio of each of the resistance RX and the resistance ZN-resistor RZN. This feature is illustrated in FIG.

FIG. 25 is a configuration diagram of a current-voltage converter using BORRCC II according to the present invention, and FIG. 26 is a graph for explaining the operation of the current-voltage converter shown in FIG.

25 and 26, the Y-port of BORRCC II is connected to the terminal to which the common mode voltage (VCM) is applied, and the BORRCC II X- Port is connected to the terminal to which the input current IIN is applied and the ZP-resistor RZP is arranged between the ZP port of the BORRCC II and the terminal to which the common mode voltage VCM is applied and the ZN- The ZN-resistor RZN is disposed between the terminals to which the voltage VCM is applied.

When the input current (IIN) is supplied to the X-port of the BORRCC II with the common mode voltage (VCM) connected to the Y-port of BORRCC II, the same current as the input current (I IN) To the ZP-port and the ZN-port. That is, I (ZPO) = I (X) and I (ZNO) = -I (X).

At this time, when the ZP-resistor RZP is connected between the ZPO terminal and the terminal to which the common mode voltage VCM is applied, V (ZPO) has a product of I (ZPO) and RZP. Conversely, when the ZN-resistor RZN is connected between the ZNO terminal and the terminal to which the common mode voltage VCM is applied, V (ZNO) has a product of I (ZNO) and RZN. At this time, I (ZNO) and I (ZPO) have current values of opposite phases having different values but different signs.

Therefore, the input current IIN is converted into an output of a voltage such as an output voltage V (ZPO) through the ZPO terminal and an output voltage V (ZNO) through the ZNO terminal. That is, the voltage is converted into the current in accordance with the following equation (6).

[Equation 6]

V (ZPO) = IIN * RZP

V (ZNO) = - IIN * RZN

Such a characteristic is illustrated in FIG. 26.

FIG. 27 is a configuration diagram of a current amplifier using BORRCC II according to the present invention, and FIG. 28 is a graph for explaining the operation of the current amplifier shown in FIG.

27 and 28, in order to implement a current amplifier for amplifying current, a terminal to which an input current IIN is applied is connected to a Y-port of BORRCC II, and a Y-port and a common mode voltage VCM When the Y-resistor RY is connected between the terminals to which the common mode voltage VCM is applied and the X-resistor RX is connected in series between the X-port of BORRCC II and the common mode voltage VCM, The voltage (V (Y)) of the transistor Q1 is expressed by the following equation: IIN * RY.

This degree of voltage is generated in the X-port, and this voltage V (X) is formed by the X-resistor RX such that a current relationship such as iX = V (X) / RX is formed. This current (iX) is output as iZPO and iZNO with normal and reverse phase, respectively.

At this time, the current (i (X)) of the X-port is defined by a relational expression such as IIN * RY / RX.

Therefore, the current outputs I (ZPO) and I (ZNO) are defined by the following relational expressions.

[Equation 7]

I (ZPO) = IIN * (RY / RX)

I (ZNO) = - IIN * (RY / RX)

This characteristic is illustrated in FIG. 28.

FIG. 29 is a configuration diagram of FBDRRCC II using BORRCC II according to two inventions, and FIG. 30 is a symbol of FBDRRCC II. FIG.

Referring to FIGS. 29 and 30, two BORRCC IIs are arranged to define FBDRRCC II. That is, the ZP-port of the upper BORRCC II and the ZN-port of the lower BORRCC II are connected to each other to define the ZPF-port of the FBDRRCC II. In addition, the ZN-port of the upper BORRCC II and the ZP-port of the lower BORRCC II are interconnected to define the ZNF-port of the FBDRRCC II.

The ZPF-port and ZNF-port of the FBDRRCC II have a function of outputting only the differential component of the voltage or current of the input port of the upper BORRCC II and the lower BORRCC II.

When the terminal to which the common mode voltage (VCM) is applied is connected to the YP-port and the YN- port, and the current input is connected to the XP-port and the XN-port,

[Equation 8]

Izppo = Ixp

Izpno = -Ixp

Iznpo = Ixn

Iznno = -Ixn

Izpo = Izppo + Iznno

Izno = Izpno + Iznpo

Izpo = Ixp - Izn

Izno = - (Izp - Izn)

The final output current through the ZPF-port is XP-XN and the final output current through the ZNF-port is - (XP-XN).

Therefore, it becomes a current conveyor structure that outputs only the difference component of the input current.

FIG. 31 is a block diagram of a fully differential voltage-to-current converter using FBDRRCC II according to the present invention, and FIG. 32 is a diagram illustrating the operation of the fully differential voltage-current converter shown in FIG. .

As shown in FIGS. 31 and 32, a fully differential voltage-current converter is implemented by connecting an X-resistor (RX) between the XP-port and the XN-port of FBDRRCC II.

When the input voltage VINP is supplied to the YP-port and the input voltage VINN is supplied to the YN- port, the difference voltage between the input voltage VINP and the input voltage VINN is calculated by the second generation current CC Port, and the difference voltage between the input voltage (VINN) and the input voltage (VINP) is output to the XN-port by the second-generation current-current (CC) formula. That is, a relation such as V (VINP-VINN) = V (XP) and V (VINN-VINP) = V (XN) can be defined.

The difference between the voltage of the XP-port and the voltage of the XN-port generates the current (XP) or the current (XN) by the X-resistor (RX). This current (XP) mirrors the current as much as iZPO to the ZPF-port, and the current as much as iZNO to the ZNF-port. Therefore, the difference voltage between the input voltage VINP and the input voltage VINN is converted into a current output such as ZPO and ZNO.

FIG. 33 is a block diagram of a fully differential voltage amplifier using FBDRRCC II according to the present invention, and FIG. 34 is a graph for explaining the operation of the fully differential voltage amplifier shown in FIG.

As shown in FIGS. 33 and 34, an X-resistor RX is connected between the XP-port and the XN-port of the FBDRRCC II, and a ZP-port is connected between the ZPF-port and the terminal to which the common mode voltage VCM is applied. Connect the resistor (RZP) and connect the ZN-resistor (RZN) between the ZNF-port and the terminal to which the common mode voltage (VCM) is applied to implement a fully differential voltage amplifier.

FIG. 35 is a configuration diagram of a fully differential current-to-voltage converter using FBDRRCC II according to the present invention, and FIG. 36 is a diagram illustrating the operation of the fully differential current-voltage converter shown in FIG. .

35 and 36, the common mode voltage VCM is applied to each of the YP-port and the YN-port of the FBDRRCC II, and the ZP-port is connected between the terminal to which the common mode voltage VCM is applied and the ZPF- A fully differential current-to-voltage converter is implemented by connecting the resistor RZP and connecting the ZN-resistor RZN between the terminal to which the common mode voltage VCM is applied and the ZNF-port.

FIG. 37 is a configuration diagram of a fully differential current amplifier using FBDRRCC II according to the present invention, and FIG. 38 is a graph for explaining the operation of the fully differential current amplifier shown in FIG.

As shown in FIGS. 37 and 38, a YP-resistor RYP is provided between the terminal for applying the input current IINP to the YP- port of the FBDRRCC II and the terminal for applying the common mode voltage VCM to the XN- Connect the YN-resistor (RYN) between the terminal for applying the input current (IINN) to the YN- port of FBDRRCC II and the terminal for applying the common mode voltage (VCM) to the XN- port, Resistor RXP is connected between the terminal to which the common mode voltage VCM is applied and the terminal to which the common mode voltage VCM is applied to the XN-port of the FBDRRCC II, Implement a fully differential current amplifier.

As described above, according to the present invention, a block of a balanced output rail-to-rail second generation current conveyor (BORRCCII) is constructed, and a full balanced differential rail-to- (FBDRRCCII).

The above-mentioned FBDRRCCII circuit has the following characteristics.

The FBDR RCC II circuit according to this embodiment operates in a single supply.

In addition, the FBDR RCC II circuit according to the present embodiment has a voltage input or a current input.

In addition, the FBDR RCC II circuit according to the present embodiment has a voltage output or a current output.

In addition, the FBDR RCC II circuit according to the present embodiment has a fully differential input and output with respect to voltage or current.

In the FBDR RCC II circuit according to the present embodiment, the common mode voltage (VCM) for the input of differential voltage or differential current is generally 1 / 2VDD (where VDD is the supply voltage) , And can be variously set from 0V to VDD depending on the application.

In addition, the FBDR RCC II circuit according to the present embodiment has a rail-to-rail input / output function for a voltage input and a voltage output.

In addition, the FBDR RCC II circuit according to the present embodiment has a function of amplifying a differential voltage or amplifying a differential current.

In addition, the FBDR RCC II circuit according to this embodiment has a function of converting a differential voltage into a current or a differential current into a voltage.

In the case of outputting a voltage or a current, the FBDR RCC II circuit according to this embodiment has a balanced output having a reverse phase output with a structure in which ZP-port and ZP-port are symmetrical with respect to 1/2 VDD, (balanced output) function.

In addition, the FBDR RCC II circuit according to the present embodiment has an advantage of obtaining a differential voltage and a current output of a phase-reversed phase exactly on the basis of the common mode voltage (VCM) without using a common mode feed back (CMFB) .

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. You will understand.

CORE: Core block 110: Upper differential input stage
120: lower differential input stage 130: upper current mirror stage
140: lower current mirror stage 150: switching stage
D2: Driving block 210: First driver
220: second driver 230: third driver
240: fourth driver 250: fifth driver
C1: first capacitor C2: second capacitor
RX: X-resistor RY: Y-resistor
RZP: ZP-resistor RZN: ZN-resistor
RXP: XP-resistor RXN: XN-resistor
RZP: ZP-resistor RZN: ZN-resistor

Claims

To-rail input / output through an upper differential input stage and a lower differential input stage commonly connected to the Y-port and the X-port, and the current applied by the bias voltage is controlled by the voltage of the Y- A core block for outputting a first driving voltage P_DRV and a second driving voltage N_DRV by mirroring based on a first bias voltage VBP0 and a second bias voltage VBP1 applied to the upper differential input terminal, A fourth bias voltage VBN0 and a fifth bias voltage VBN1 are applied to the lower differential input terminal; And
Port in response to the first driving voltage (P_DRV) and the second driving voltage (N_DRV), and outputs an inverted output current having a phase opposite to the normal output current to the ZN-port And a driving block which outputs the driving block through the driving block,
An upper current mirror stage connected to an output terminal of the lower differential input stage and mirroring a current output through the lower differential input stage to output the first driving voltage P_DRV;
A lower current mirror stage connected to an output terminal of the upper differential input stage and outputting the second driving voltage N_DRV by mirroring a current output through the upper differential input stage; And
Further comprising a switching stage that includes two CMOS transmission gates and is disposed between the upper current mirror stage and the lower current mirror stage to perform a class AB driver function,
The inverted clock terminals of each of the CMOS transmission gates are commonly connected to receive a third bias voltage VBP2 and a clock terminal of each of the CMOS transmission gates receives a sixth bias voltage VBN2,
Wherein the first to sixth bias voltages VBP0, VBP1, VBP2, VBN0, VBN1 and VBN2 are generated by a wide-swing cascode bias circuit. - Rail second generation current conveyor.

[3] The method of claim 1, wherein the upper differential input stage is configured to compare a voltage of the Y-port with a voltage of the X-port to flow a current applied by a bias voltage through a transistor to which a low voltage is input,
Wherein the lower differential input stage is adapted to compare a voltage of the Y-port with a voltage of the X-port to allow a current applied by the bias voltage to flow through a transistor to which a high voltage is inputted, Rail 2nd Generation Current Conveyor.

3. The differential amplifier of claim 2, wherein the upper differential input stage comprises:
Two PMOSs connected in series; And
And two PMOSs serially connected to the two PMOSs and connected in parallel with each other,
The first bias voltage VBP0 and the second bias voltage VBP1 are applied to the gates of the two PMOSs connected in series,
Wherein the voltage of the Y-port and the voltage of the X-port are applied to the gates of the two PMOSs connected in parallel to each other.

3. The apparatus of claim 2, wherein the lower differential input stage comprises:
Two NMOSs connected in series; And
And two NMOSs serially connected to the two NMOSs and connected in parallel to each other,
The fourth bias voltage VBN0 and the fifth bias voltage VBN1 are applied to the gates of the two NMOSs connected in series,
Wherein the voltage of the Y-port and the voltage of the X-port are applied to the gates of the two NMOSs connected in parallel to each other.

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2. The method of claim 1, wherein the upper current mirror stage and the lower current mirror stage convert a voltage difference between a signal applied through the Y-port and a signal applied through the X- Output rail-to-rail second generation current conveyor.

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2. The balanced output rail-to-rail second generation current conveyor of claim 1, wherein the switching stage adjusts the bias current of the upper current mirror stage and the bias current of the lower current mirror stage.

The balanced output rail-to-rail second generation current conveyor according to claim 1, wherein the switching stage controls the voltage level of the output stage of the upper current mirror stage and the voltage level of the output stage of the lower current mirror stage.

2. The balanced output rail-to-rail second generation current conveyor according to claim 1, wherein the switching stage has a rail-to-rail output structure in which the width of the output voltage covers the supply voltage.

2. The balanced output rail-to-rail second generation current conveyor of claim 1, wherein the upper current mirror stage comprises a plurality of PMOSs, and the lower current mirror stage comprises a plurality of NMOSs.

The apparatus of claim 1,
A first capacitor having one end connected to the upper current mirror stage and the other end connected to the X-port to stabilize the frequency; And
Further comprising a second capacitor having one end connected to the lower current mirror stage and the other end connected to the X-port to stabilize the frequency.

The balanced output rail-to-rail second generation current conveyor of claim 1, wherein the upper differential input stage comprises a plurality of PMOSs, and the lower differential input stage comprises a plurality of NMOSs.

2. The vehicle driving force control apparatus according to claim 1,
A first driver for controlling a voltage applied to the X-port in response to the first driving voltage (P_DRV) and the second driving voltage (N_DRV);
A second driver for controlling a normal output current output through the ZP-port in response to the first driving voltage (P_DRV) and the second driving voltage (N_DRV);
A third driver for outputting a third driving voltage P_DRV1 in response to the second driving voltage N_DRV and outputting a fourth driving voltage N_DRV1 in response to the first driving voltage P_DRV;
A fourth driver for receiving the third driving voltage (P_DRV1) and the fourth driving voltage (N_DRV1); And
And a fifth driver mirrored by the fourth driver to output an inverted output current through the ZN-port. &Lt; Desc / Clms Page number 19 >

15. The method of claim 14, wherein the PMOSs of the first driver, the second driver, the third driver, the fourth driver, and the fifth driver have the same gate area,
Wherein the NMOSs included in the first driver, the second driver, the third driver, the fourth driver, and the fifth driver have the same gate area. The balanced output rail-to-rail second generation current conveyor .

The balanced output rail-to-rail second generation current conveyor according to claim 1, wherein the normal output current and the inverted output current are in opposite phases to each other.

2. The balanced output rail-to-rail second generation current conveyor of claim 1, wherein the core block further comprises a bias circuit stage for generating the bias voltage.

2. The voltage-to-current converter according to claim 1,
An X-resistor (RX) is disposed between the common mode terminal to which the common mode voltage is applied and the X-port,
The Y-port is connected to a terminal to which an input voltage is applied,
The normal output current defined by the relationship between the input voltage and the X-resistor (RX) is output through the ZP-port,
Wherein the inverted output current defined by a relationship between the input voltage and the X-resistor (RX) is output through the ZN-port. &Lt; Desc / Clms Page number 20 >

2. The method of claim 1, further comprising:
The Y-port is connected to a terminal to which an input voltage is applied,
The common mode voltage is connected to the X-port via the X-resistor RX, to the ZP-port via the ZP-resistor RZP, and to the ZN- Port,
A positive voltage defined by a relationship between the input voltage, the X-resistor (RX) and the ZP-resistor (RZP) is output through the ZP-
Wherein a negative voltage defined by a relationship between the input voltage, the X-resistor (RX) and the ZN-resistor (RZN) is output through the ZN-port. Current conveyor.

The method of claim 1, wherein to implement the current-voltage converter,
A ZP-resistor (RZP) is disposed between the ZP port and the Y port,
A ZN-resistor (RZN) is disposed between the ZN-port and the Y-port,
The Y-port is connected to a terminal to which an input voltage is applied,
An input current is applied to the X-port,
The positive voltage defined by the relationship between the input current and the ZP-resistor (RZP) is output through the ZP-port,
And a negative voltage defined by a relationship between the input current and the ZN-resistor (RZN) is output through the ZN-port.

2. The method of claim 1, further comprising:
A Y-resistor (RY) is disposed between a terminal to which an input current is applied and a common mode terminal to which a common mode voltage is applied,
An X-resistor RX is disposed between the common mode terminal and the X-port,
The Y-port is connected to a terminal to which an input current is applied,
The normal output current defined by the relationship between the input current, the X-resistor (RX) and the Y-resistor (RY) is output through the ZP-
Wherein an inverted output current defined by a relationship between the input current, the X-resistor (RX) and the Y-resistor (RY) is output through the ZN-port. Current conveyor.

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