WO2024031991A1 - Reference circuit - Google Patents

Reference circuit Download PDF

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Publication number
WO2024031991A1
WO2024031991A1 PCT/CN2023/082753 CN2023082753W WO2024031991A1 WO 2024031991 A1 WO2024031991 A1 WO 2024031991A1 CN 2023082753 W CN2023082753 W CN 2023082753W WO 2024031991 A1 WO2024031991 A1 WO 2024031991A1
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WO
WIPO (PCT)
Prior art keywords
chopper switch
chopper
mos tube
switch
voltage
Prior art date
Application number
PCT/CN2023/082753
Other languages
French (fr)
Chinese (zh)
Inventor
李琛
荆二荣
徐德辉
Original Assignee
上海烨映微电子科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication of WO2024031991A1 publication Critical patent/WO2024031991A1/en

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Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation

Definitions

  • the invention relates to the field of integrated circuit design, and in particular to a reference circuit.
  • the sensor signal is extremely weak (generally at the nV ⁇ uV level), as shown in Figure 1.
  • the mainstream signal processing is implemented by a high-precision pre-amplifier (pre-amplifer) plus an analog-to-digital converter (ADC), but the pre-amplifier and ADCs have to sacrifice area and power consumption to ensure performance.
  • the gain of the preamplifier is high (such as >100 times)
  • the analog input signal is amplified to a larger level, so the accuracy requirements for the back-end ADC are reduced, and thus the reference noise requirements are also reduced.
  • the overall noise performance of the system Mainly determined by the equivalent input noise (RTI) of the preamplifier.
  • the gain of the preamplifier is small (such as ⁇ 50 times).
  • the noise requirements for the back-end ADC increase, and the noise level of the ADC is not only related to its own Quantization noise, device noise, and reference noise levels are related. Reference noise optimization is very important in this case and must be paid attention to when designing the system.
  • the object of the present invention is to provide a reference circuit to solve the problem of poor reference noise performance of the existing reference circuit.
  • a reference circuit which includes:
  • a voltage generation module configured to generate and output a reference voltage according to the positive temperature coefficient voltage and the negative temperature coefficient voltage, and to regulate the positive temperature coefficient voltage and the negative temperature coefficient voltage according to the bias voltage;
  • a chopper modulation module connected to the positive voltage terminal and the negative voltage terminal of the voltage generation module, for performing chopper modulation on the positive temperature coefficient voltage and the negative temperature coefficient voltage according to the chopping frequency;
  • the amplification and demodulation module is connected to the two output terminals of the chopper modulation module, and is used to perform operational amplifier processing on the chopper-modulated positive temperature coefficient voltage and negative temperature coefficient voltage, and then perform chopper demodulation according to the chopping frequency. And generate the bias voltage, and perform chopping modulation on the amplifier noise in the amplification and demodulation module according to the chopping frequency;
  • Notch filter module connected to the output end of the amplification and demodulation module, used to filter the amplifier noise at the chopping frequency point. Perform notch processing.
  • the voltage generation module includes: a first MOS tube, a second MOS tube, a first resistor, a second resistor, a first triode and a second triode; the gate of the first MOS tube
  • the gate of the second MOS transistor is connected to the bias voltage, the source of the first MOS transistor and the source of the second MOS transistor are connected to the power supply voltage, and the drain of the first MOS transistor is connected to the The first end of the first resistor serves as the positive voltage end of the voltage generating module, and the drain of the second MOS transistor is connected to the first end of the second resistor and serves as the output end of the voltage generating module;
  • the second end of the first resistor is connected to the emitter of the first transistor; the second end of the second resistor is connected to the emitter of the second transistor and serves as the negative voltage of the voltage generating module. terminal; the base of the first triode is connected to its collector and grounded; the base of the second triode is connected to its collector and grounded.
  • the chopper modulation module includes: a first chopper switch, a second chopper switch, a third chopper switch and a fourth chopper switch; the first end of the first chopper switch and the The first terminal of the third chopper switch is connected to the positive voltage terminal of the voltage generating module, and the first terminal of the second chopper switch is connected to the first terminal of the fourth chopper switch and connected to the positive voltage terminal of the voltage generating module.
  • the negative voltage end of the voltage generation module, the second end of the first chopper switch is connected to the second end of the second chopper switch and serves as the first output end of the chopper modulation module, and the third The second end of the chopper switch is connected to the second end of the fourth chopper switch and serves as the second output end of the chopper modulation module; wherein the first chopper switch and the fourth chopper switch
  • the switch is controlled by a first clock
  • the second chopping switch and the third chopping switch are controlled by a second clock
  • the first clock and the second clock are a set of inverted clocks.
  • the amplification and demodulation module includes: a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, a fifth chopper switch, a sixth chopper switch, and a third MOS transistor.
  • Seven chopper switches and an eighth chopper switch the gate of the third MOS tube is connected to the gate control voltage, the source is connected to the power supply voltage, and the drain is connected to the source of the fourth MOS tube and the fifth MOS tube.
  • the source; the gate of the fourth MOS tube and the gate of the fifth MOS tube are connected to the two output terminals of the chopper modulation module, and the drain of the fourth MOS tube is connected to the The drains of the six MOS transistors, the first end of the fifth chopper switch and the first end of the sixth chopper switch.
  • the drain of the fifth MOS transistor is connected to the drain of the seventh MOS transistor.
  • the gate of the sixth MOS tube is connected to the gate of the seventh MOS tube, and the sixth MOS
  • the source of the tube and the source of the seventh MOS tube are grounded;
  • the second end of the fifth chopper switch is connected to the second end of the seventh chopper switch and connected to the gate of the sixth MOS tube.
  • the second end of the sixth chopper switch is connected to the second end of the eighth chopper switch and serves as the output end of the amplification demodulation module; wherein, the fifth chopper switch and the eighth chopper switch
  • the chopper switch is controlled by a first clock
  • the sixth chopper switch and the seventh chopper switch are controlled by a second clock
  • the first clock and the second clock are a set of inverted clocks.
  • the amplification and demodulation module includes: a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor tube, seventh MOS tube, eighth MOS tube, ninth MOS tube, tenth MOS tube, eleventh MOS tube, twelfth MOS tube, thirteenth MOS tube, fifth chopper switch, sixth chopper switch switch, the seventh chopper switch, the eighth chopper switch, the ninth chopper switch, the tenth chopper switch, the eleventh chopper switch and the twelfth chopper switch; the gate of the third MOS tube and The gate of the fourth MOS tube is connected to the two output terminals of the chopper modulation module, and the source of the third MOS tube and the source of the fourth MOS tube are connected to the fifth MOS tube.
  • the drain of the third MOS tube is connected to the drain of the twelfth MOS tube, the drain of the fourth MOS tube is connected to the drain of the thirteenth MOS tube;
  • the fifth MOS The gate of the tube is connected to the first gate control voltage, the source is connected to the source of the sixth MOS tube and the source of the seventh MOS tube and is connected to the power supply voltage;
  • the gate of the sixth MOS tube is connected to the The gate of the seventh MOS transistor is connected to the second gate control voltage, and the drain of the sixth MOS transistor is connected to the first end of the fifth chopper switch and the first end of the seventh chopper switch, so
  • the drain of the seventh MOS transistor is connected to the first end of the sixth chopper switch and the first end of the eighth chopper switch; the second end of the fifth chopper switch is connected to the sixth chopper switch.
  • the second end of the wave switch is connected to the source of the eighth MOS transistor, and the second end of the seventh chopper switch is connected to the second end of the eighth chopper switch and connected to the ninth MOS transistor.
  • the source of the tube; the gate of the eighth MOS tube is connected to the gate of the ninth MOS tube and connected to the third gate control voltage, and the drain of the eighth MOS tube is connected to the drain of the tenth MOS tube. pole, the first end of the ninth chopper switch and the first end of the tenth chopper switch, and the drain of the ninth MOS transistor is connected to the drain of the eleventh MOS transistor and the first end of the tenth chopper switch.
  • the fifth chopper switch, the eighth chopper switch, the ninth chopper switch, and the twelfth chopper switch are controlled by the A clock
  • the sixth chopper switch, the seventh chopper switch, the tenth chopper switch, the eleventh chopper switch are controlled by a second clock
  • the first clock and the The second clocks are a set of inverted clocks.
  • the notch filter module includes: a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor and a third capacitor; the first end of the third resistor is connected to the first The first end of the capacitor is connected to the output end of the amplification and demodulation module, and the second end is connected to the first end of the fourth resistor and the first end of the second capacitor; the second end of the first capacitor Connect the first end of the third capacitor and the first end of the fifth resistor; the second end of the fourth resistor is connected to the second end of the third capacitor and serve as the output of the notch filter module terminal; the second terminal of the second capacitor is grounded; the second terminal of the fifth resistor is grounded; wherein, the third resistor, the fourth resistor and the fifth resistor adopt switched capacitors.
  • the control clock of the switch in the switched capacitor circuit and the chopping clock are frequency-divided and phase-shifted by 45°.
  • the reference circuit further includes: an output driving module, connected to the output end of the voltage generation module, for enhancing the load driving capability of the reference voltage.
  • the output driver module includes:
  • a chopper modulation unit connected to the output end of the voltage generation module, used to perform chopper modulation on the reference voltage and feedback voltage according to the chopping frequency;
  • An amplification and demodulation unit is connected to the two output terminals of the chopper modulation unit, and is used to amplify the error of the chopper-modulated reference voltage and feedback voltage, and then perform chopper demodulation according to the chopper frequency and generate an intermediate voltage, And, perform chopping modulation on the amplifier noise in the amplification and demodulation unit according to the chopping frequency;
  • the notch filter unit is connected to the output end of the amplification and demodulation unit, and is used to perform notch processing on the amplifier noise at the chopping frequency point.
  • the output end of the notch filter unit serves as the output end of the output driving module and generates the feedback voltage
  • the output driving module further includes: a driving tube, a first voltage dividing resistor and a second voltage dividing resistor.
  • the gate of the driving tube is connected to the trap.
  • the output end of the wave filter unit, the source is connected to the power supply voltage, the drain is connected to the first end of the first voltage dividing resistor and serves as the output end of the output driving module, and the second end of the first voltage dividing resistor is connected to The first end of the second voltage dividing resistor generates the feedback voltage, and the second end of the second voltage dividing resistor is connected to ground.
  • the chopper modulation unit includes: a thirteenth chopper switch, a fourteenth chopper switch, a fifteenth chopper switch and a sixteenth chopper switch; the third chopper switch of the thirteenth chopper switch One end is connected to the first end of the fifteenth chopper switch and the output end of the voltage generating module, and the first end of the fourteenth chopper switch is connected to the first end of the sixteenth chopper switch.
  • One end is connected to the feedback voltage, and the second end of the thirteenth chopper switch is connected to the second end of the fourteenth chopper switch and serves as the first output end of the chopper modulation unit,
  • the second end of the fifteenth chopper switch is connected to the second end of the sixteenth chopper switch and serves as the second output end of the chopper modulation unit; wherein, the thirteenth chopper switch and the sixteenth chopper switch is controlled by a first clock, the fourteenth chopper switch and the fifteenth chopper switch are controlled by a second clock, the first clock and the second The clocks are a set of inverted clocks. .
  • the amplification and demodulation unit includes: a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a seventeenth chopper switch, a Eighteenth chopper switch, nineteenth chopper switch and twentieth chopper switch; the gate of the fourteenth MOS transistor is connected to the gate control voltage, the source is connected to the power supply voltage, and the drain is connected to the fifteenth MOS transistor.
  • the source of the tube and the source of the sixteenth MOS tube; the gate of the fifteenth MOS tube and the The gates of the sixteenth MOS tube are connected to the two output terminals of the chopper modulation unit, and the drain of the fifteenth MOS tube is connected to the drain of the seventeenth MOS tube and the seventeenth chopper modulation unit.
  • the first end of the switch and the first end of the eighteenth chopper switch, the drain of the sixteenth MOS transistor is connected to the drain of the eighteenth MOS transistor and the drain of the nineteenth chopper switch.
  • the source of the eighteenth MOS transistor is grounded;
  • the second end of the seventeenth chopper switch is connected to the second end of the nineteenth chopper switch and connected to the gate of the seventeenth MOS transistor,
  • the second end of the eighteenth chopper switch is connected to the second end of the twentieth chopper switch and serves as the output end of the amplification and demodulation unit; wherein, the seventeenth chopper switch and the The twentieth chopper switch is controlled by a first clock.
  • the eighteenth chopper switch and the nineteenth chopper switch are controlled by a second clock.
  • the first clock and the second clock are mutually exclusive.
  • the amplification and demodulation unit includes: a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube tube, the twenty-first MOS tube, the twenty-second MOS tube, the twenty-third MOS tube, the twenty-fourth MOS tube, the seventeenth chopper switch, the eighteenth chopper switch, the nineteenth chopper switch , the twentieth chopper switch, the twenty-first chopper switch, the twenty-second chopper switch, the twenty-third chopper switch and the twenty-fourth chopper switch; the gate of the fourteenth MOS tube
  • the gate of the fifteenth MOS transistor is connected to the two output terminals of the chopper modulation unit, and the source of the fourteenth MOS transistor and the source of the fifteenth MOS transistor are connected to the source of the first MOS transistor.
  • the drain of the sixteenth MOS tube, the drain of the fourteenth MOS tube is connected to the drain of the twenty-third MOS tube, and the drain of the fifteenth MOS tube is connected to the twenty-fourth MOS tube.
  • the drain of the sixteenth MOS transistor is connected to the first gate control voltage, and the source is connected to the source of the seventeenth MOS transistor and the source of the eighteenth MOS transistor and connected to the power supply voltage;
  • the gate of the seventeenth MOS transistor is connected to the gate of the eighteenth MOS transistor and connected to the second gate control voltage, and the drain of the seventeenth MOS transistor is connected to the seventh gate of the seventeenth chopper switch.
  • One end is connected to the first end of the nineteenth chopper switch, and the drain of the eighteenth MOS tube is connected to the first end of the eighteenth chopper switch and the twentieth chopper switch.
  • One end; the second end of the seventeenth chopper switch is connected to the second end of the eighteenth chopper switch and connected to the source of the nineteenth MOS tube.
  • the nineteenth chopper switch The second end of the switch is connected to the second end of the twentieth chopper switch and connected to the source of the twentieth MOS tube; the gate of the nineteenth MOS tube is connected to the gate of the twentieth MOS tube.
  • the gate is also connected to the third gate control voltage
  • the drain of the nineteenth MOS transistor is connected to the drain of the twenty-first MOS transistor, the first end of the twenty-first chopper switch and the first end of the chopper switch.
  • the first end of the twenty-second chopper switch, the drain of the twentieth MOS transistor is connected to the drain of the twenty-second MOS transistor, the first end of the twenty-third chopper switch and the The first end of the twenty-fourth chopper switch;
  • the gate of the twenty-first MOS transistor is connected to the gate of the twenty-second MOS transistor and connected to the fourth gate control voltage.
  • the source of the tube is connected to the drain of the twenty-third MOS tube, and the source of the twenty-second MOS tube is connected to the drain of the twenty-fourth MOS tube;
  • the gate is connected to the twenty-fourth MOS tube The gate of the twenty-third MOS transistor and the source of the twenty-fourth MOS transistor are grounded; the second end of the twenty-first chopper switch is connected to the twenty-third chopper switch.
  • the second end of the wave switch is connected to the gate of the twenty-third MOS transistor, and the second end of the twenty-second chopper switch is connected to the second end of the twenty-fourth chopper switch and serves as the The output end of the amplification and demodulation unit; wherein the seventeenth chopper switch, the twentieth chopper switch, the twenty-first chopper switch and the twenty-fourth chopper switch are controlled At the first clock, the eighteenth chopper switch, the nineteenth chopper switch, the twenty-second chopper switch and the twenty-third chopper switch are controlled by the second clock, so The first clock and the second clock are a set of inverted clocks.
  • the notch filter unit includes: a sixth resistor, a seventh resistor, an eighth resistor, a fourth capacitor, a fifth capacitor and a sixth capacitor; the first end of the sixth resistor is connected to the fourth The first end of the capacitor is connected to the output end of the amplification and demodulation unit, and the second end is connected to the first end of the seventh resistor and the first end of the fifth capacitor; the second end of the fourth capacitor The first end of the sixth capacitor is connected to the first end of the eighth resistor; the second end of the seventh resistor is connected to the second end of the sixth capacitor and serves as the output of the notch filter unit terminal; the second terminal of the fifth capacitor is grounded; the second terminal of the eighth resistor is grounded; wherein the sixth resistor, the seventh resistor and the eighth resistor are implemented by a switched capacitor circuit, so The control clock of the switch in the switched capacitor circuit and the chopping clock are frequency-divided and phase-shifted by 45°.
  • the switches in the switched capacitor circuit are implemented using NMOS tubes, wherein the substrate of the NMOS tube includes a DPWDN isolation diode and a DDNPWPSUB isolation diode.
  • the reference circuit of the present invention can effectively suppress the impact of amplifier noise on the reference voltage through the design of the chopper modulation module, amplification demodulation module, notch filter module and output driver module, thereby improving the noise characteristics of the reference voltage. ; Moreover, each module can be implemented using extremely small on-chip circuits, occupying a small area and having good system loop stability.
  • Figure 1 shows a schematic diagram of an existing signal processing system consisting of a preamplifier and an analog-to-digital converter.
  • Figure 2 shows a schematic diagram of the reference circuit of the present invention.
  • Figure 3 shows a schematic diagram of the chopper modulation module of the present invention.
  • Figure 4 shows the equivalent circuit diagram of Figure 3 showing the chopper modulation module when the first clock is valid.
  • FIG. 5 shows an equivalent circuit diagram of the chopper modulation module shown in FIG. 3 when the second clock is active.
  • Figure 6 shows a schematic diagram of an amplification and demodulation module of the present invention.
  • Figure 7 shows the equivalent circuit diagram of Figure 6 showing the amplification and demodulation module when the first clock is valid.
  • Figure 8 shows the equivalent circuit diagram of Figure 6 showing the amplification and demodulation module when the second clock is valid.
  • Figure 9 shows a schematic diagram of another amplification and demodulation module of the present invention.
  • Figure 10 shows the equivalent circuit diagram of Figure 9 showing the amplification and demodulation module when the first clock is valid.
  • FIG. 11 shows an equivalent circuit diagram of the amplification demodulation module when the second clock is valid as shown in FIG. 9 .
  • Figure 12 shows a schematic diagram of the notch filter module of the present invention.
  • Figure 13 shows a schematic diagram of the switched capacitor circuit of the present invention.
  • Figure 14 shows a schematic diagram of an isolation diode provided in the substrate of an NMOS transistor.
  • Figure 15 shows the clock and voltage waveforms associated with the synchronous integration notch filter of the present invention.
  • Figure 16 shows a schematic diagram of the output driving module of the present invention implemented using an output buffer.
  • Figure 17 shows a schematic diagram of the output driving module of the present invention when it is implemented using a low voltage dropout linear regulator.
  • Figure 18 shows a schematic diagram of an error amplifier in an output buffer or low-dropout linear regulator.
  • Figure 19 shows a schematic diagram of an alternative error amplifier in an output buffer or low-dropout linear regulator.
  • Figure 20 shows a schematic diagram of a circuit-level compensation scheme for an output buffer structure.
  • Figure 21 shows a schematic diagram of the chopper modulation unit of the present invention.
  • FIG. 22 shows an equivalent circuit diagram of the chopper modulation unit when the first clock is active as shown in FIG. 21 .
  • FIG. 23 shows an equivalent circuit diagram of the chopper modulation unit when the second clock is active as shown in FIG. 21 .
  • Figure 24 shows a schematic diagram of an amplification demodulation unit of the present invention.
  • FIG. 25 shows an equivalent circuit diagram of the amplification demodulation unit shown in FIG. 24 when the first clock is valid.
  • FIG. 26 shows an equivalent circuit diagram of the amplification demodulation unit when the second clock is valid as shown in FIG. 24 .
  • Figure 27 shows a schematic diagram of another amplification and demodulation unit of the present invention.
  • FIG. 28 shows an equivalent circuit diagram of the amplification demodulation unit when the first clock is valid as shown in FIG. 27 .
  • FIG. 29 shows an equivalent circuit diagram of the amplification demodulation unit shown in FIG. 27 when the second clock is valid.
  • Figure 30 shows a schematic diagram of the notch filter unit of the present invention.
  • Figure 31 shows a schematic diagram of a circuit-level compensation scheme for a low-dropout linear regulator architecture.
  • this embodiment provides a reference circuit 10.
  • the reference circuit 10 includes: a voltage generation module 100, a chopper modulation module 200, an amplification demodulation module 300, and a notch filter module 400. Further, the reference circuit 10 also includes: an output driving module 500 .
  • the voltage generation module 100 is used to generate and output a reference voltage VREF according to the positive temperature coefficient voltage VP and the negative temperature coefficient voltage VN, and to regulate the positive temperature coefficient voltage VP and the negative temperature coefficient voltage VN according to the bias voltage VB', so that both equal.
  • the voltage generation module 100 includes: a first MOS transistor M1, a second MOS transistor M2, a first resistor R1, a second resistor R2, a first transistor Q1 and a second transistor Q2. ;
  • the gate of the first MOS transistor M1 and the gate of the second MOS transistor M2 are connected to the bias voltage VB', the source of the first MOS transistor M1 and the source of the second MOS transistor M2 are connected to the power supply voltage VDD, and the first MOS The drain of the tube M1 is connected to the first terminal of the first resistor R1 and serves as the positive voltage terminal of the voltage generation module 100 to generate the positive temperature coefficient voltage VP.
  • the drain of the second MOS tube M2 is connected to the first terminal of the second resistor R2 and As the output end of the voltage generation module 100, the reference voltage VREF is output; the second end of the first resistor R1 is connected to the emitter of the first transistor Q1; the second end of the second resistor R2 is connected to the emitter of the second transistor Q2.
  • the base of the first transistor Q1 is connected to its collector and grounded, and the base of the second transistor Q2 is connected to its collector and grounded. .
  • the specific circuit of the voltage generation module 100 is not limited to this, and the above circuit structure is only an example; it can be any existing bandgap reference circuit including an operational amplifier, except for the operational amplifier. Circuit structure, this embodiment is suitable for There is no restriction on this.
  • how the voltage generation module 100 generates the reference voltage VREF according to the positive temperature coefficient voltage VP and the negative temperature coefficient voltage VN, and how to regulate the positive temperature coefficient voltage VP and the negative temperature coefficient voltage VN according to the bias voltage VB' to make them equal It is well known to those skilled in the art and will not be described in detail here.
  • the chopper modulation module 200 is connected to the positive voltage terminal and the negative voltage terminal of the voltage generation module 100, and is used to perform chopper modulation on the positive temperature coefficient voltage VP and the negative temperature coefficient voltage VN according to the chopping frequency.
  • the chopper modulation module 200 includes: a first chopper switch K1 , a second chopper switch K2 , a third chopper switch K3 and a fourth chopper switch K4 ; the first chopper switch K1 The first terminal of is connected to the first terminal of the third chopper switch K3 and is connected to the positive voltage terminal of the voltage generation module 100 to access the positive temperature coefficient voltage VP, and the first terminal of the second chopper switch K2 is connected to the fourth chopper switch K3.
  • the first end of the switch K4 is connected to the negative voltage end of the voltage generation module 100 to access the negative temperature coefficient voltage VN, and the second end of the first chopper switch K1 is connected to the second end of the second chopper switch K2 and serves as The first output terminal TP of the chopper modulation module 200 and the second terminal of the third chopper switch K3 are connected to the second terminal of the fourth chopper switch K4 and serve as the second output terminal TN of the chopper modulation module 200; wherein, The first chopper switch K1 and the fourth chopper switch K4 are controlled by the first clock, the second chopper switch K2 and the third chopper switch K3 are controlled by the second clock, and the first clock and the second clock are one with each other. Set of inverted clocks. It should be noted that the first clock is the chopping clock, and its frequency is the chopping frequency.
  • the first chopper switch K1 and the fourth chopper switch K4 are controlled to be closed by the first clock
  • the second chopper switch K2 and the third chopper switch K3 are controlled to be turned off by the second clock, etc.
  • the effective circuit is shown in Figure 4.
  • the first output terminal TP of the chopper modulation module 200 outputs the positive temperature coefficient voltage VP
  • the second output terminal TN outputs the negative temperature coefficient voltage VN; between the first chopper switch K1 and the
  • the four chopper switch K4 is controlled by the first clock to turn off
  • the second chopper switch K2 and the third chopper switch K3 are controlled by the second clock to close.
  • the equivalent circuit is shown in Figure 5.
  • the chopper The first output terminal TP of the modulation module 200 outputs the negative temperature coefficient voltage VN
  • the second output terminal TN outputs the positive temperature coefficient voltage VP.
  • the amplification and demodulation module 300 is connected to the two output terminals TP and TN of the chopper modulation module 200, and is used to perform operational amplifier processing on the chopper-modulated positive temperature coefficient voltage and negative temperature coefficient voltage, and then chop them according to the chopping frequency.
  • the bias voltage VB is demodulated and generated, and the amplifier noise in the amplification and demodulation module 300 is chopper-modulated according to the chopping frequency.
  • the amplification and demodulation module 300 includes: a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, a fifth MOS transistor M7, and a third MOS transistor M4.
  • the source of the fourth MOS transistor M4 and the source of the fifth MOS transistor M5; the gate of the fourth MOS transistor M4 and the gate of the fifth MOS transistor M5 are respectively connected to the two output terminals of the chopper modulation module 200 (such as the fourth The gate of the MOS transistor M4 is connected to the first output terminal TP of the chopper modulation module 200, the gate of the fifth MOS transistor M5 is connected to the second output terminal TN) of the chopper modulation module 200, and the drain of the fourth MOS transistor M4 is connected to The drain of the sixth MOS tube M6, The first terminal of the fifth chopper switch K5 and the first terminal of the sixth chopper switch K6.
  • the drain of the fifth MOS tube M5 is connected to the drain of the seventh MOS tube M7 and the first terminal of the seventh chopper switch K7. and the first end of the eighth chopper switch K8; the gate of the sixth MOS transistor M6 is connected to the gate of the seventh MOS transistor M7, the source of the sixth MOS transistor M6 and the source of the seventh MOS transistor M7 are grounded;
  • the second terminal of the fifth chopper switch K5 is connected to the second terminal of the seventh chopper switch K7 and connected to the gate of the sixth MOS transistor M6, and the second terminal of the sixth chopper switch K6 is connected to the third terminal of the eighth chopper switch K8.
  • the two terminals are used as the output terminal of the amplification and demodulation module 300; among them, the fifth chopper switch K5 and the eighth chopper switch K8 are controlled by the first clock, and the sixth chopper switch K6 and the seventh chopper switch K7 are controlled by the first clock.
  • the first clock and the second clock are a set of inverted clocks.
  • the third MOS transistor M3 to the seventh MOS transistor M7 constitute an operational amplifier circuit, and the fifth to eighth chopper switches K5 to K8 are used in conjunction with the front-stage chopper modulation module 200 to complete the modulation and demodulation of the voltage signal.
  • the fifth chopper switch K5 to the eighth chopper switch K8 also perform chopper modulation on the amplifier noise of the operational amplifier to modulate the amplifier noise from low frequency to high frequency.
  • the amplification and demodulation module 300 includes: a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M7.
  • MOS tube M8 ninth MOS tube M9, tenth MOS tube M10, eleventh MOS tube M11, twelfth MOS tube M12, thirteenth MOS tube M13, fifth chopper switch K5, sixth chopper switch K6 , the seventh chopper switch K7, the eighth chopper switch K8, the ninth chopper switch K9, the tenth chopper switch K10, the eleventh chopper switch K11 and the twelfth chopper switch K12; the third MOS tube M3
  • the gate of the third MOS transistor M4 and the gate of the fourth MOS transistor M4 are respectively connected to the two output terminals of the chopper modulation module 200 (for example, the gate of the third MOS transistor M3 is connected to the first output terminal TP of the chopper modulation module 200, and the fourth MOS transistor M4 is connected to the first output terminal TP of the chopper modulation module 200.
  • the gate of the tube M4 is connected to the second output terminal TN) of the chopper modulation module 200, and the sources of the third MOS tube M3 and the fourth MOS tube M4 are connected to the drain of the fifth MOS tube M5.
  • the drain of M3 is connected to the drain of the twelfth MOS transistor, the drain of the fourth MOS transistor M4 is connected to the drain of the thirteenth MOS transistor M13; the gate of the fifth MOS transistor M5 is connected to the first gate control voltage Vb1, the source
  • the gate electrode of the sixth MOS transistor M6 is connected to the gate electrode of the seventh MOS transistor M7 and connected to the second gate control voltage Vb2.
  • the drain of the sixth MOS transistor M6 is connected to the first terminal of the fifth chopper switch K5 and the first terminal of the seventh chopper switch K7, and the drain of the seventh MOS tube M7 is connected to the first terminal of the sixth chopper switch K6.
  • the second terminal of the fifth chopper switch K5 is connected to the second terminal of the sixth chopper switch K6 and connected to the source of the eighth MOS tube M8, and the seventh chopper switch K5
  • the second end of the switch K7 is connected to the second end of the eighth chopper switch K8 and connected to the source of the ninth MOS tube M9; the gate of the eighth MOS tube M8 is connected
  • the gate of the ninth MOS transistor M9 is also connected to the third gate control voltage Vb3, and the drain of the eighth MOS transistor M8 is connected to the drain of the tenth MOS transistor M10, the first end of the ninth chopper switch K9 and the tenth chopper switch K9.
  • the first terminal of the switch K10 and the drain of the ninth MOS tube M9 are connected to the drain of the eleventh MOS tube M11, the first terminal of the eleventh chopper switch K11 and the first terminal of the twelfth chopper switch K12;
  • the gate of the tenth MOS transistor M10 is connected to the gate of the eleventh MOS transistor M11 and connected to the fourth gate control voltage Vb4.
  • the source of the tenth MOS transistor M10 is connected to the drain of the twelfth MOS transistor M12.
  • the eleventh MOS transistor The source of the tube M11 is connected to the drain of the thirteenth MOS tube M13; the gate of the twelfth MOS tube M12 is connected to the gate of the thirteenth MOS tube M13, and the source of the twelfth MOS tube M12 and the thirteenth MOS The source of the tube M13 is grounded; the second terminal of the ninth chopper switch K9 is connected to the second terminal of the eleventh chopper switch K11 and connected to the gate of the twelfth MOS tube M12; the second terminal of the tenth chopper switch K10 The terminal is connected to the second terminal of the twelfth chopper switch K12 and serves as the output terminal of the amplification and demodulation module 300; wherein, the fifth chopper switch K5, the eighth chopper switch K8, the ninth chopper switch K9, the twelfth chopper switch K9 The chopper switch K12 is controlled by the first clock, the sixth chopper switch K6, the seventh chopper
  • the sixth chopper switch K6 when the fifth chopper switch K5, the eighth chopper switch K8, the ninth chopper switch K9, and the twelfth chopper switch K12 are controlled by the first clock to close, the sixth chopper switch K6, the The seventh chopper switch K7, the tenth chopper switch K10, and the eleventh chopper switch K11 are controlled to be turned off by the second clock.
  • the equivalent circuit is shown in Figure 10; in the fifth chopper switch K5, the eighth chopper switch When the switch K8, the ninth chopper switch K9, and the twelfth chopper switch K12 are controlled by the first clock being turned off, the sixth chopper switch K6, the seventh chopper switch K7, the tenth chopper switch K10, and the tenth chopper switch K12 are controlled by the first clock.
  • a chopper switch K11 is controlled to close by the second clock, and the equivalent circuit is shown in Figure 11.
  • the third MOS transistor M3 to the thirteenth MOS transistor M13 constitute an operational amplifier circuit, and the fifth to twelfth chopper switches K5 to K12 are used in conjunction with the front-stage chopper modulation module 200 to complete the modulation and demodulation of the voltage signal.
  • the fifth chopper switch K5 to the twelfth chopper switch K12 also perform chopper modulation on the amplifier noise of the operational amplifier to modulate the amplifier noise from low frequency to high frequency.
  • the notch filter module 400 is connected to the output end of the amplification and demodulation module 300, and is used to notch the amplifier noise at the chopping frequency point, thereby reducing the clock glitch on the bias voltage VB.
  • the notch filter module 400 includes: a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, a second capacitor C2 and a third capacitor C3; the third resistor R3
  • the first end is connected to the first end of the first capacitor C1 and the output end of the amplification and demodulation module 300 to access the bias voltage VB, and the second end is connected to the first end of the fourth resistor R4 and the second end of the second capacitor C2
  • One end; the second end of the first capacitor C1 is connected to the first end of the third capacitor C3 and the first end of the fifth resistor R5; the second end of the fourth resistor is connected to the second end of the third capacitor and serves as a notch filter
  • the output terminal of the module 400 outputs the filtered bias voltage VB'; the second terminal of the second capacitor C2 is connected to the ground; the second terminal of the fifth resistor R5 is connected to the ground; wherein, the third resistor R3, the fourth resistor R4
  • the switched capacitor circuit includes capacitor C01, capacitor C02, switch K01 and switch K02, where switch K01 is controlled by the control clock and switch K02 is controlled by the inverse clock of the control clock (as shown in Figure 13); etc.
  • the effective resistance is 1/FC
  • F is the frequency of the control clock
  • C is the capacitance value of capacitor C01.
  • the resistances of the third resistor R3 and the fourth resistor R4 can be set to be equal and twice the value of the fifth resistor R5; the capacitances of the first capacitor C1 and the third capacitor C3 can be set to be equal and equal to the resistance of the second capacitor C2. 1/2.
  • the switches in the switched capacitor circuit are implemented using NMOS tubes.
  • the substrate of the NMOS tube includes a DPWDN (P-well/deep N-well) isolation diode and a DDNPWPSUB (deep P-well) well/deep N-well) isolation diode (shown in Figure 14).
  • DPWDN isolation diodes such as D1
  • DDNPWPSUB isolation diodes such as D2
  • the notch filter module 400 is implemented using a synchronous integration notch filter.
  • the synchronous integration notch filter uses a clock signal that is 45° divided and phase-shifted from the chopping clock in the pre-amplification demodulation module 300.
  • the control clock of the switch in the switched capacitor circuit can effectively reduce the clock glitch problem by integrating the positive and negative parts of the clock glitch caused by the amplifier noise in one clock cycle, that is, effectively suppressing the influence of the amplifier noise, thereby improving the benchmark
  • the noise characteristics of the voltage (as shown in Figure 15); using a clock related to the pre-stage chopping clock as the control clock avoids the clock aliasing problem caused by using irrelevant clocks, and the resulting filter sampling Larger noise at the clock folds back to low frequencies, severely reducing the effect of the pre-stage chopper modulation.
  • locating the synchronous integration notch filter in the reference generation loop rather than behind the reference output can effectively reduce the fluctuation at the output end.
  • the output driving module 500 is connected to the output end of the voltage generating module 100 and is used to enhance the load driving capability of the reference voltage VREF.
  • the output driver module 500 is implemented using an output buffer or a low dropout linear regulator (LD0).
  • LD0 low dropout linear regulator
  • the output buffer includes: an error amplifier EA.
  • the non-inverting input end of the error amplifier EA is connected to the output end of the voltage generation module 100 to access the reference voltage VREF, and the inverting input end is connected to its output end to access the feedback voltage.
  • VFB the output terminal serves as the output terminal of the output buffer to output voltage VO' and generate feedback voltage VFB.
  • the low dropout linear voltage regulator includes: an error amplifier EA, a drive tube MP, a first voltage dividing resistor Rd1 and a second voltage dividing resistor Rd2.
  • the inverting input end of the error amplifier EA is connected to the voltage generating module 100.
  • the output terminal is connected to the reference voltage VREF, the non-inverting input terminal is connected to the first terminal of the second voltage dividing resistor Rd2 to be connected to the feedback voltage VFB, the output terminal is connected to the gate of the driving tube MP, and the source of the driving tube MP is connected to the power supply voltage VDD.
  • the drain is connected to the first voltage dividing resistor Rd1
  • the first end serves as the output end of the low voltage dropout linear regulator to output voltage VO'
  • the second end of the first voltage dividing resistor Rd1 is connected to the first end of the second voltage dividing resistor Rd2
  • the second voltage dividing resistor Rd2 The second terminal is connected to ground.
  • the error amplifier EA is implemented using the circuit structure shown in Figure 18 or Figure 19.
  • the output driving module 500 includes: a chopper modulation unit 501, an amplification demodulation unit 502 and a notch filter unit 503; at this time, the output of the notch filter unit 503
  • the terminal serves as the output terminal of the output driving module 500 and generates the feedback voltage VFB.
  • the chopper modulation unit 501 is connected to the output end of the voltage generation module 100 and the output end of the notch filter unit 503, and is used to perform chopper modulation on the reference voltage VREF and the feedback voltage VFB according to the chopping frequency.
  • the chopper modulation unit 501 includes: a thirteenth chopper switch K13, a fourteenth chopper switch K14, a fifteenth chopper switch K15, and a sixteenth chopper switch K16;
  • the first end of the three-chopper switch K13 is connected to the first end of the fifteenth chopper switch K15 and connected to the output end of the voltage generation module 100 to access the reference voltage VREF.
  • the first end of the fourteenth chopper switch K14 is connected to the first end of the fourteenth chopper switch K15.
  • the first terminal of the sixteenth chopper switch K16 is connected to the feedback voltage VFB, and the second terminal of the thirteenth chopper switch K13 is connected to the second terminal of the fourteenth chopper switch K14 and serves as the chopper modulation unit 501
  • the first output terminal TP, the second terminal of the fifteenth chopper switch K15 is connected to the second terminal of the sixteenth chopper switch K16 and serves as the second output terminal TN of the chopper modulation unit 501; wherein, the thirteenth chopper switch K15
  • the wave switch K13 and the sixteenth chopper switch K16 are controlled by the first clock
  • the fourteenth chopper switch K14 and the fifteenth chopper switch K15 are controlled by the second clock
  • the first clock and the second clock are one of each other. Set of inverted clocks.
  • the fourteenth chopper switch K14 and the fifteenth chopper switch K15 are controlled by the second clock.
  • the equivalent circuit is shown in Figure 22.
  • the first output terminal TP of the chopper modulation unit 501 outputs the reference voltage VREF
  • the second output terminal TN outputs the feedback voltage VFB
  • the fourteenth chopper switch K14 and the fifteenth chopper switch K15 are controlled to be turned on by the second clock.
  • the equivalent circuit is shown in Figure 23.
  • the first output terminal TP of the chopper modulation unit 501 outputs the feedback voltage VFB
  • the second output terminal TN outputs the reference voltage VREF.
  • the amplification and demodulation unit 502 is connected to the two output terminals TP and TN of the chopper modulation unit 501, and is used to amplify the error of the chopper-modulated reference voltage and feedback voltage, and then perform chopper demodulation according to the chopper frequency and generate an intermediate voltage VM, and the amplifier noise in the amplification and demodulation unit 502 is chopping modulated according to the chopping frequency.
  • the amplification and demodulation unit 502 includes: a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, a sixteenth MOS transistor M16, a seventeenth MOS transistor M17, an eighteenth MOS transistor M18, the seventeenth chopper switch K17, the eighteenth chopper switch K18, the nineteenth chopper switch K19 and the twentieth chopper switch K20; the gate of the fourteenth MOS tube M14 is connected to the gate control voltage Vb, the source The pole is connected to the power supply voltage VDD, the drain is connected to the source of the fifteenth MOS transistor M15 and the source of the sixteenth MOS transistor M16; the gate of the fifteenth MOS transistor M15 and the gate of the sixteenth MOS transistor M16 are connected correspondingly.
  • the two output terminals of the chopper modulation unit 501 (for example, the gate of the fifteenth MOS transistor M15 is connected to the first output terminal TP of the chopper modulation unit 501, and the gate of the sixteenth MOS transistor M16 is connected to the chopper modulation unit 501).
  • the second output terminal TN), the drain of the fifteenth MOS transistor M15 is connected to the drain of the seventeenth MOS transistor M17, the first terminal of the seventeenth chopper switch K17 and the first terminal of the eighteenth chopper switch K18 , the drain of the sixteenth MOS tube M16 is connected to the drain of the eighteenth MOS tube M18, the first terminal of the nineteenth chopper switch K19 and the first terminal of the twentieth chopper switch K20; the seventeenth MOS tube
  • the gate of M17 is connected to the gate of the eighteenth MOS transistor M18, the source of the seventeenth MOS transistor M17 and the source of the eighteenth MOS transistor M18 are grounded;
  • the second end of the seventeenth chopper switch K17 is connected to the tenth
  • the second end of the nine-chopper switch K19 is connected to the gate of the seventeenth MOS transistor M17, and the second end of the eighteenth chopper switch K18 is connected to the second end of the twentieth c
  • the output terminal of 502 outputs the intermediate voltage VM; among them, the seventeenth chopper switch K17 and the twentieth chopper switch K20 are controlled by the first clock, and the eighteenth chopper switch K18 and the nineteenth chopper switch K19 are controlled by the first clock. Controlled by the second clock, the first clock and the second clock are a set of inverted clocks.
  • the fourteenth to eighteenth MOS transistors M14 to M18 constitute an error amplifier circuit, and the seventeenth to twentieth chopper switches K17 to K20 are used in conjunction with the front-stage chopper modulation unit 501 to complete the modulation and synthesis of the voltage signal. Demodulation, at the same time, the seventeenth chopper switch K17 to the twentieth chopper switch K20 also perform chopper modulation on the amplifier noise of the error amplifier to modulate the amplifier noise from low frequency to high frequency.
  • the amplification demodulation unit 502 includes: a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, a sixteenth MOS transistor M16, a seventeenth MOS transistor M17, an eighteenth MOS transistor tube M18, the nineteenth MOS tube M19, the twentieth MOS tube M20, the twenty-first MOS tube M21, the twenty-second MOS tube M22, the twenty-third MOS tube M23, the twenty-fourth MOS tube M24, the Seventeenth chopper switch K17, eighteenth chopper switch K18, nineteenth chopper switch K19, twentieth chopper switch K20, twenty-first chopper switch K21, twenty-second chopper switch K22, The twenty-third chopper switch K23 and the twenty-fourth chopper switch K24; the gate of the fourteenth MOS tube M14 and the fifteenth MOS
  • the gate of the tube M15 is connected to the two output terminals of the chopper modulation unit 501 (for
  • the source is connected to the source of the seventeenth MOS transistor M17 and the source of the eighteenth MOS transistor M18 and is connected to the power supply voltage VDD;
  • the gate of the seventeenth MOS transistor M17 is connected to the gate of the eighteenth MOS transistor M18 And connected to the second gate control voltage Vb2
  • the drain of the seventeenth MOS tube M17 is connected to the first terminal of the seventeenth chopper switch K17 and the first terminal of the nineteenth chopper switch K19, and the drain of the eighteenth MOS tube M18
  • the drain is connected to the first terminal of the eighteenth chopper switch K18 and the first terminal of the twentieth chopper switch K20;
  • the second terminal of the seventeenth chopper switch K17 and the second terminal of the eighteenth chopper switch K18 Connected and connected to the source of the nineteenth MOS tube M19, the second end of the nineteenth chopper switch K19 is connected to the second end of the twentieth chopper switch K20 and connected to the source
  • the drain of the nineteenth MOS transistor M19 is connected to the drain of the twenty-first MOS transistor M21 and the second gate control voltage Vb3.
  • the first terminal of the eleventh chopper switch K21 and the first terminal of the twenty-second chopper switch K22, and the drain of the twentieth MOS tube M20 are connected to the drain of the twenty-second MOS tube M22 and the twenty-third chopper switch K22.
  • the second terminal serves as the output terminal of the amplification and demodulation unit 502 to output the intermediate voltage VM; among them, the seventeenth chopper switch K17, the twentieth chopper switch K20, the twenty-first chopper switch K21 and the twenty-fourth chopper switch K20.
  • the chopper switch K24 is controlled by the first clock, and the eighteenth chopper switch K18, the nineteenth chopper switch K19, the twenty-second chopper switch K22 and the twenty-third chopper switch K23 are controlled by the second clock.
  • the first clock and the second clock are a set of inverted clocks.
  • the seventeenth chopper switch K17, the twentieth chopper switch K20, the twenty-first chopper switch K21 and the twenty-fourth chopper switch K24 are controlled by the first clock to close
  • the eighteenth The chopper switch K18, the nineteenth chopper switch K19, the twenty-second chopper switch K22 and the twenty-third chopper switch K23 are controlled to be turned off by the second clock.
  • the equivalent circuit is shown in Figure 28; in the When the seventeenth chopper switch K17, the twentieth chopper switch K20, the twenty-first chopper switch K21 and the twenty-fourth chopper switch K24 are controlled by the first clock being turned off, the eighteenth chopper switch K18, The nineteenth chopper switch K19, the twenty-second chopper switch The wave switch K22 and the twenty-third chopper switch K23 are controlled to be closed by the second clock, and the equivalent circuit is shown in Figure 29.
  • the fourteenth to twenty-fourth MOS transistors M14 to M24 constitute an error amplifier circuit, and the seventeenth to twenty-fourth chopper switches K17 to K24 are used in conjunction with the front-stage chopper modulation unit 501 to complete the voltage signal. Modulation and demodulation, at the same time, the seventeenth chopper switch K17 to the twenty-fourth chopper switch K24 also perform chopper modulation on the amplifier noise of the error amplifier to modulate the amplifier noise from low frequency to high frequency
  • the notch filter unit 503 is connected to the output end of the amplification and demodulation unit 502, and is used to perform notch processing on the amplifier noise at the chopping frequency point, thereby reducing the clock glitch on the intermediate voltage VM.
  • the notch filter unit 503 includes: a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a fourth capacitor C4, a fifth capacitor C5 and a sixth capacitor C6; the sixth resistor R6
  • the first end is connected to the first end of the fourth capacitor C4 and the output end of the amplification and demodulation unit 502 to access the intermediate voltage VM, and the second end is connected to the first end of the seventh resistor R7 and the first end of the fifth capacitor C5 terminal;
  • the second terminal of the fourth capacitor C4 is connected to the first terminal of the sixth capacitor C6 and the first terminal of the eighth resistor R8;
  • the second terminal of the seventh resistor R7 is connected to the second terminal of the sixth capacitor C6 and serves as a trap
  • the output terminal of the filtering unit 503 outputs the voltage VO; the second terminal of the fifth capacitor C5 is connected to the ground; the second terminal of the eighth resistor R8 is connected to the ground; among which, the sixth resistor R6, the seventh resistor
  • the switched capacitor circuit includes capacitor C01, capacitor C02, switch K01 and switch K02, where switch K01 is controlled by the control clock and switch K02 is controlled by the inverted signal of the control clock (as shown in Figure 13); etc.
  • the effective resistance is 1/FC
  • F is the frequency of the control clock
  • C is the capacitance value of capacitor C01.
  • the resistance values of the sixth resistor R6 and the seventh resistor R7 are equal and are twice the value of the eighth resistor R8; the capacitance values of the fourth capacitor C4 and the sixth capacitor C6 are equal and are equal to the fifth capacitor C5. 1/2.
  • the switches in the switched capacitor circuit are implemented using NMOS tubes.
  • the substrate of the NMOS tube includes a DPWDN (P-well/deep N-well) isolation diode and a DDNPWPSUB (deep P-well) well/deep N-well) isolation diode (shown in Figure 14).
  • DPWDN isolation diodes such as D1
  • DDNPWPSUB isolation diodes such as D2
  • the notch filter unit 503 is implemented using a synchronous integration notch filter.
  • the synchronous integration notch filter uses a clock signal that is 45° divided and phase-shifted from the chopping clock in the preamplification and demodulation unit 502.
  • the control clock of the switch in the switched capacitor circuit can effectively reduce the clock glitch problem by integrating the positive and negative parts of the clock glitch caused by the amplifier noise in one clock cycle, that is, effectively suppressing the influence of the amplifier noise, thereby improving the benchmark Voltage noise characteristics (as shown in Figure 15); and using a clock related to the pre-stage chopping clock as the control clock avoids the clock aliasing problem caused by using irrelevant clocks, and the resulting filter sampling clock at a relatively high position. Large noise folds back to low frequencies, thereby seriously reducing the effect of the pre-stage chopper modulation.
  • the output driver module 500 also includes: a driver tube. MP, the first voltage dividing resistor Rd1 and the second voltage dividing resistor Rd2.
  • the gate of the driving tube MP is connected to the output end of the notch filter unit 503, the source is connected to the power supply voltage VDD, and the drain is connected to the third voltage dividing resistor Rd1.
  • One end serves as the output end of the output driver module 500, the second end of the first voltage dividing resistor Rd is connected to the first end of the second voltage dividing resistor Rd and generates the feedback voltage VFB, and the second end of the second voltage dividing resistor Rd2 is connected to ground. . Since the chopper modulation unit 501, the amplification demodulation unit 502 and the notch filter unit 503 are the same as the circuit-level compensation scheme of the output buffer structure, they will not be described in detail here. The relevant content can be found above.
  • the synchronous integration notch filter is placed before the drive tube MP, which can greatly suppress the voltage fluctuation added to the drive tube MP and effectively improve the clock at the output end. Jitter problem.
  • the reference circuit of the present invention can effectively suppress the impact of amplifier noise on the reference voltage through the design of the chopper modulation module, amplification demodulation module, notch filter module and output driver module, thereby improving the reference voltage.
  • noise characteristics moreover, each module can be implemented with extremely small on-chip circuits, occupying a small area and having good system loop stability. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

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Abstract

A reference circuit (10), comprising: a voltage generation module (100) used for generating a reference voltage according to positive and negative temperature coefficient voltages, and regulating the positive and negative temperature coefficient voltages according to a bias voltage; a chopping modulation module (200) connected to positive and negative voltage ends of the voltage generation module (100) and used for performing chopping modulation on the positive and negative temperature coefficient voltages according to a chopping frequency; an amplification and demodulation module (300) connected to two output ends of the chopping modulation module (200) and used for carrying out operational amplification processing on the positive and negative temperature coefficient voltages subjected to the chopping modulation, then performing chopping demodulation according to the chopping frequency and generating a bias voltage, and performing chopping modulation on amplifier noise in the amplification and demodulation module (300) according to the chopping frequency; and a notch filtering module (400) connected to an output end of the amplification and demodulation module (300) and used for performing at a chopping frequency point notch processing on the amplifier noise. The present reference circuit (10) solves the problem of the poor reference noise performance of existing reference circuits.

Description

一种基准电路a reference circuit 技术领域Technical field
本发明涉及集成电路设计领域，特别是涉及一种基准电路。The invention relates to the field of integrated circuit design, and in particular to a reference circuit.
背景技术Background technique
传感器信号极其微弱(一般在nV～uV级别)，如图1所示，主流的信号处理采用高精度的前置放大器(pre-amplifer)加模数转换器(ADC)实现，但前置放大器和ADC都要牺牲面积和功耗来保证性能。The sensor signal is extremely weak (generally at the nV~uV level), as shown in Figure 1. The mainstream signal processing is implemented by a high-precision pre-amplifier (pre-amplifer) plus an analog-to-digital converter (ADC), but the pre-amplifier and ADCs have to sacrifice area and power consumption to ensure performance.
由于基准电压的噪声特性会直接作用于ADC，影响其输出精度，因此，此种信号处理方案对基准电压及其噪声要求极高。Since the noise characteristics of the reference voltage will directly act on the ADC and affect its output accuracy, this signal processing solution has extremely high requirements on the reference voltage and its noise.
在前置放大器的增益较高(如>100倍)时，模拟输入信号被放大至较大水平，因此对后端ADC精度要求降低，从而对基准噪声要求也会降低，这时系统整体噪声性能主要由前置放大器的等效输入噪声(RTI)决定。When the gain of the preamplifier is high (such as >100 times), the analog input signal is amplified to a larger level, so the accuracy requirements for the back-end ADC are reduced, and thus the reference noise requirements are also reduced. At this time, the overall noise performance of the system Mainly determined by the equivalent input noise (RTI) of the preamplifier.
鉴于功耗、面积等各方面考量，有些情况下，前置放大器的增益较小(如<50倍)，这时对后端ADC的噪声要求随之增加，而ADC的噪声水平除了与本身的量化噪声、器件噪声有关，还与基准噪声水平相关，基准噪声优化在这种情况下就显得非常重要，系统设计时必须给予重视。In view of various considerations such as power consumption and area, in some cases, the gain of the preamplifier is small (such as <50 times). At this time, the noise requirements for the back-end ADC increase, and the noise level of the ADC is not only related to its own Quantization noise, device noise, and reference noise levels are related. Reference noise optimization is very important in this case and must be paid attention to when designing the system.
发明内容Contents of the invention
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种基准电路，用于解决现有基准电路存在基准噪声性能差的问题。In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a reference circuit to solve the problem of poor reference noise performance of the existing reference circuit.
为实现上述目的及其他相关目的，本发明提供一种基准电路，所述基准电路包括：In order to achieve the above objects and other related objects, the present invention provides a reference circuit, which includes:
电压产生模块，用于根据正温度系数电压和负温度系数电压产生基准电压并输出，以及，根据偏置电压调控所述正温度系数电压和所述负温度系数电压；a voltage generation module, configured to generate and output a reference voltage according to the positive temperature coefficient voltage and the negative temperature coefficient voltage, and to regulate the positive temperature coefficient voltage and the negative temperature coefficient voltage according to the bias voltage;
斩波调制模块，连接所述电压产生模块的正电压端和负电压端，用于根据斩波频率对所述正温度系数电压和所述负温度系数电压进行斩波调制；A chopper modulation module, connected to the positive voltage terminal and the negative voltage terminal of the voltage generation module, for performing chopper modulation on the positive temperature coefficient voltage and the negative temperature coefficient voltage according to the chopping frequency;
放大解调模块，连接所述斩波调制模块的两个输出端，用于对经过斩波调制的正温度系数电压和负温度系数电压进行运放处理后再根据斩波频率进行斩波解调并产生所述偏置电压，以及，根据斩波频率对所述放大解调模块中的放大器噪声进行斩波调制；The amplification and demodulation module is connected to the two output terminals of the chopper modulation module, and is used to perform operational amplifier processing on the chopper-modulated positive temperature coefficient voltage and negative temperature coefficient voltage, and then perform chopper demodulation according to the chopping frequency. And generate the bias voltage, and perform chopping modulation on the amplifier noise in the amplification and demodulation module according to the chopping frequency;
陷波滤波模块，连接所述放大解调模块的输出端，用于在斩波频率点对所述放大器噪声 进行陷波处理。Notch filter module, connected to the output end of the amplification and demodulation module, used to filter the amplifier noise at the chopping frequency point. Perform notch processing.
可选地，所述电压产生模块包括：第一MOS管、第二MOS管、第一电阻、第二电阻、第一三极管及第二三极管；所述第一MOS管的栅极和所述第二MOS管的栅极连接偏置电压，所述第一MOS管的源极和所述第二MOS管的源极连接电源电压，所述第一MOS管的漏极连接所述第一电阻的第一端并作为所述电压产生模块的正电压端，所述第二MOS管的漏极连接所述第二电阻的第一端并作为所述电压产生模块的输出端；所述第一电阻的第二端连接所述第一三极管的发射极；所述第二电阻的第二端连接所述第二三极管的发射极并作为所述电压产生模块的负电压端；所述第一三极管的基极与其集电极相连并接地；所述第二三极管的基极与其集电极相连并接地。Optionally, the voltage generation module includes: a first MOS tube, a second MOS tube, a first resistor, a second resistor, a first triode and a second triode; the gate of the first MOS tube The gate of the second MOS transistor is connected to the bias voltage, the source of the first MOS transistor and the source of the second MOS transistor are connected to the power supply voltage, and the drain of the first MOS transistor is connected to the The first end of the first resistor serves as the positive voltage end of the voltage generating module, and the drain of the second MOS transistor is connected to the first end of the second resistor and serves as the output end of the voltage generating module; The second end of the first resistor is connected to the emitter of the first transistor; the second end of the second resistor is connected to the emitter of the second transistor and serves as the negative voltage of the voltage generating module. terminal; the base of the first triode is connected to its collector and grounded; the base of the second triode is connected to its collector and grounded.
可选地，所述斩波调制模块包括：第一斩波开关、第二斩波开关、第三斩波开关及第四斩波开关；所述第一斩波开关的第一端与所述第三斩波开关的第一端相连并连接所述电压产生模块的正电压端，所述第二斩波开关的第一端与所述第四斩波开关的第一端相连并连接所述电压产生模块的负电压端，所述第一斩波开关的第二端与所述第二斩波开关的第二端相连并作为所述斩波调制模块的第一输出端，所述第三斩波开关的第二端与所述第四斩波开关的第二端相连并作为所述斩波调制模块的第二输出端；其中，所述第一斩波开关和所述第四斩波开关受控于第一时钟，所述第二斩波开关和所述第三斩波开关受控于第二时钟，所述第一时钟和所述第二时钟互为一组反相时钟。Optionally, the chopper modulation module includes: a first chopper switch, a second chopper switch, a third chopper switch and a fourth chopper switch; the first end of the first chopper switch and the The first terminal of the third chopper switch is connected to the positive voltage terminal of the voltage generating module, and the first terminal of the second chopper switch is connected to the first terminal of the fourth chopper switch and connected to the positive voltage terminal of the voltage generating module. The negative voltage end of the voltage generation module, the second end of the first chopper switch is connected to the second end of the second chopper switch and serves as the first output end of the chopper modulation module, and the third The second end of the chopper switch is connected to the second end of the fourth chopper switch and serves as the second output end of the chopper modulation module; wherein the first chopper switch and the fourth chopper switch The switch is controlled by a first clock, the second chopping switch and the third chopping switch are controlled by a second clock, and the first clock and the second clock are a set of inverted clocks.
可选地，所述放大解调模块包括：第三MOS管、第四MOS管、第五MOS管、第六MOS管、第七MOS管、第五斩波开关、第六斩波开关、第七斩波开关及第八斩波开关；所述第三MOS管的栅极连接栅控电压，源极连接电源电压，漏极连接所述第四MOS管的源极和所述第五MOS管的源极；所述第四MOS管的栅极和所述第五MOS管的栅极对应连接所述斩波调制模块的两个输出端，所述第四MOS管的漏极连接所述第六MOS管的漏极、所述第五斩波开关的第一端和所述第六斩波开关的第一端，所述第五MOS管的漏极连接所述第七MOS管的漏极、所述第七斩波开关的第一端和所述第八斩波开关的第一端；所述第六MOS管的栅极连接所述第七MOS管的栅极，所述第六MOS管的源极和所述第七MOS管的源极接地；所述第五斩波开关的第二端连接所述第七斩波开关的第二端并连接所述第六MOS管的栅极，所述第六斩波开关的第二端连接所述第八斩波开关的第二端并作为所述放大解调模块的输出端；其中，所述第五斩波开关和所述第八斩波开关受控于第一时钟，所述第六斩波开关和所述第七斩波开关受控于第二时钟，所述第一时钟和所述第二时钟互为一组反相时钟；Optionally, the amplification and demodulation module includes: a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, a fifth chopper switch, a sixth chopper switch, and a third MOS transistor. Seven chopper switches and an eighth chopper switch; the gate of the third MOS tube is connected to the gate control voltage, the source is connected to the power supply voltage, and the drain is connected to the source of the fourth MOS tube and the fifth MOS tube. the source; the gate of the fourth MOS tube and the gate of the fifth MOS tube are connected to the two output terminals of the chopper modulation module, and the drain of the fourth MOS tube is connected to the The drains of the six MOS transistors, the first end of the fifth chopper switch and the first end of the sixth chopper switch. The drain of the fifth MOS transistor is connected to the drain of the seventh MOS transistor. , the first end of the seventh chopper switch and the first end of the eighth chopper switch; the gate of the sixth MOS tube is connected to the gate of the seventh MOS tube, and the sixth MOS The source of the tube and the source of the seventh MOS tube are grounded; the second end of the fifth chopper switch is connected to the second end of the seventh chopper switch and connected to the gate of the sixth MOS tube. , the second end of the sixth chopper switch is connected to the second end of the eighth chopper switch and serves as the output end of the amplification demodulation module; wherein, the fifth chopper switch and the eighth chopper switch The chopper switch is controlled by a first clock, the sixth chopper switch and the seventh chopper switch are controlled by a second clock, and the first clock and the second clock are a set of inverted clocks. ;
或者，所述放大解调模块包括：第三MOS管、第四MOS管、第五MOS管、第六MOS 管、第七MOS管、第八MOS管、第九MOS管、第十MOS管、第十一MOS管、第十二MOS管、第十三MOS管、第五斩波开关、第六斩波开关、第七斩波开关、第八斩波开关、第九斩波开关、第十斩波开关、第十一斩波开关及第十二斩波开关；所述第三MOS管的栅极和所述第四MOS管的栅极对应连接所述斩波调制模块的两个输出端，所述第三MOS管的源极和所述第四MOS管的源极连接所述第五MOS管的漏极，所述第三MOS管的漏极连接所述第十二MOS管的漏极，所述第四MOS管的漏极连接所述第十三MOS管的漏极；所述第五MOS管的栅极连接第一栅控电压，源极连接所述第六MOS管的源极和所述第七MOS管的源极并连接电源电压；所述第六MOS管的栅极连接所述第七MOS管的栅极并连接第二栅控电压，所述第六MOS管的漏极连接所述第五斩波开关的第一端和所述第七斩波开关的第一端，所述第七MOS管的漏极连接所述第六斩波开关的第一端和所述第八斩波开关的第一端；所述第五斩波开关的第二端与所述第六斩波开关的第二端相连并连接所述第八MOS管的源极，所述第七斩波开关的第二端与所述第八斩波开关的第二端相连并连接所述第九MOS管的源极；所述第八MOS管的栅极连接所述第九MOS管的栅极并连接第三栅控电压，所述第八MOS管的漏极连接所述第十MOS管的漏极、所述第九斩波开关的第一端和所述第十斩波开关的第一端，所述第九MOS管的漏极连接所述第十一MOS管的漏极、所述第十一斩波开关的第一端和所述第十二斩波开关的第一端；所述第十MOS管的栅极连接所述第十一MOS管的栅极并连接第四栅控电压，所述第十MOS管的源极连接所述第十二MOS管的漏极，所述第十一MOS管的源极连接所述第十三MOS管的漏极；所述第十二MOS管的栅极连接所述第十三MOS管的栅极，所述第十二MOS管的源极和所述第十三MOS管的源极接地；所述第九斩波开关的第二端连接所述第十一斩波开关的第二端并连接所述第十二MOS管的栅极，所述第十斩波开关的第二端连接所述第十二斩波开关的第二端并作为所述放大解调模块的输出端；其中，所述第五斩波开关、所述第八斩波开关、所述第九斩波开关、所述第十二斩波开关受控于第一时钟，所述第六斩波开关、所述第七斩波开关、所述第十斩波开关、所述第十一斩波开关受控于第二时钟，所述第一时钟和所述第二时钟互为一组反相时钟。Alternatively, the amplification and demodulation module includes: a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor tube, seventh MOS tube, eighth MOS tube, ninth MOS tube, tenth MOS tube, eleventh MOS tube, twelfth MOS tube, thirteenth MOS tube, fifth chopper switch, sixth chopper switch switch, the seventh chopper switch, the eighth chopper switch, the ninth chopper switch, the tenth chopper switch, the eleventh chopper switch and the twelfth chopper switch; the gate of the third MOS tube and The gate of the fourth MOS tube is connected to the two output terminals of the chopper modulation module, and the source of the third MOS tube and the source of the fourth MOS tube are connected to the fifth MOS tube. Drain, the drain of the third MOS tube is connected to the drain of the twelfth MOS tube, the drain of the fourth MOS tube is connected to the drain of the thirteenth MOS tube; the fifth MOS The gate of the tube is connected to the first gate control voltage, the source is connected to the source of the sixth MOS tube and the source of the seventh MOS tube and is connected to the power supply voltage; the gate of the sixth MOS tube is connected to the The gate of the seventh MOS transistor is connected to the second gate control voltage, and the drain of the sixth MOS transistor is connected to the first end of the fifth chopper switch and the first end of the seventh chopper switch, so The drain of the seventh MOS transistor is connected to the first end of the sixth chopper switch and the first end of the eighth chopper switch; the second end of the fifth chopper switch is connected to the sixth chopper switch. The second end of the wave switch is connected to the source of the eighth MOS transistor, and the second end of the seventh chopper switch is connected to the second end of the eighth chopper switch and connected to the ninth MOS transistor. The source of the tube; the gate of the eighth MOS tube is connected to the gate of the ninth MOS tube and connected to the third gate control voltage, and the drain of the eighth MOS tube is connected to the drain of the tenth MOS tube. pole, the first end of the ninth chopper switch and the first end of the tenth chopper switch, and the drain of the ninth MOS transistor is connected to the drain of the eleventh MOS transistor and the first end of the tenth chopper switch. The first end of the eleventh chopper switch and the first end of the twelfth chopper switch; the gate of the tenth MOS transistor is connected to the gate of the eleventh MOS transistor and connected to the fourth gate control voltage , the source of the tenth MOS tube is connected to the drain of the twelfth MOS tube, the source of the eleventh MOS tube is connected to the drain of the thirteenth MOS tube; the twelfth MOS The gate of the tube is connected to the gate of the thirteenth MOS tube, the source of the twelfth MOS tube and the source of the thirteenth MOS tube are grounded; the second terminal of the ninth chopper switch The second end of the eleventh chopper switch is connected to the gate of the twelfth MOS transistor, and the second end of the tenth chopper switch is connected to the second end of the twelfth chopper switch. and serves as the output end of the amplification and demodulation module; wherein, the fifth chopper switch, the eighth chopper switch, the ninth chopper switch, and the twelfth chopper switch are controlled by the A clock, the sixth chopper switch, the seventh chopper switch, the tenth chopper switch, the eleventh chopper switch are controlled by a second clock, the first clock and the The second clocks are a set of inverted clocks.
可选地，所述陷波滤波模块包括：第三电阻、第四电阻、第五电阻、第一电容、第二电容及第三电容；所述第三电阻的第一端连接所述第一电容的第一端并连接所述放大解调模块的输出端，第二端连接所述第四电阻的第一端和所述第二电容的第一端；所述第一电容的第二端连接所述第三电容的第一端和所述第五电阻的第一端；所述第四电阻的第二端连接所述第三电容的第二端并作为所述陷波滤波模块的输出端；所述第二电容的第二端接地；所述第五电阻的第二端接地；其中，所述第三电阻、所述第四电阻和所述第五电阻采用开关电容电 路实现，所述开关电容电路中开关的控制时钟与斩波时钟除频相移45°。Optionally, the notch filter module includes: a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor and a third capacitor; the first end of the third resistor is connected to the first The first end of the capacitor is connected to the output end of the amplification and demodulation module, and the second end is connected to the first end of the fourth resistor and the first end of the second capacitor; the second end of the first capacitor Connect the first end of the third capacitor and the first end of the fifth resistor; the second end of the fourth resistor is connected to the second end of the third capacitor and serve as the output of the notch filter module terminal; the second terminal of the second capacitor is grounded; the second terminal of the fifth resistor is grounded; wherein, the third resistor, the fourth resistor and the fifth resistor adopt switched capacitors. circuit implementation, the control clock of the switch in the switched capacitor circuit and the chopping clock are frequency-divided and phase-shifted by 45°.
可选地，所述基准电路还包括：输出驱动模块，连接所述电压产生模块的输出端，用于增强所述基准电压的负载驱动能力。Optionally, the reference circuit further includes: an output driving module, connected to the output end of the voltage generation module, for enhancing the load driving capability of the reference voltage.
可选地，所述输出驱动模块包括：Optionally, the output driver module includes:
斩波调制单元，连接所述电压产生模块的输出端，用于根据斩波频率对所述基准电压和反馈电压进行斩波调制；A chopper modulation unit, connected to the output end of the voltage generation module, used to perform chopper modulation on the reference voltage and feedback voltage according to the chopping frequency;
放大解调单元，连接所述斩波调制单元的两个输出端，用于对经过斩波调制的基准电压和反馈电压进行误差放大后再根据斩波频率进行斩波解调并产生中间电压，以及，根据斩波频率对所述放大解调单元中的放大器噪声进行斩波调制；An amplification and demodulation unit is connected to the two output terminals of the chopper modulation unit, and is used to amplify the error of the chopper-modulated reference voltage and feedback voltage, and then perform chopper demodulation according to the chopper frequency and generate an intermediate voltage, And, perform chopping modulation on the amplifier noise in the amplification and demodulation unit according to the chopping frequency;
陷波滤波单元，连接所述放大解调单元的输出端，用于在斩波频率点对所述放大器噪声进行陷波处理。The notch filter unit is connected to the output end of the amplification and demodulation unit, and is used to perform notch processing on the amplifier noise at the chopping frequency point.
可选地，在所述输出驱动模块采用输出缓冲器结构时，所述陷波滤波单元的输出端作为所述输出驱动模块的输出端并产生所述反馈电压；Optionally, when the output driving module adopts an output buffer structure, the output end of the notch filter unit serves as the output end of the output driving module and generates the feedback voltage;
在所述输出驱动模块采用低压差线性稳压器结构时，所述输出驱动模块还包括：驱动管、第一分压电阻及第二分压电阻，所述驱动管的栅极连接所述陷波滤波单元的输出端，源极连接电源电压，漏极连接所述第一分压电阻的第一端并作为所述输出驱动模块的输出端，所述第一分压电阻的第二端连接所述第二分压电阻的第一端并产生所述反馈电压，所述第二分压电阻的第二端接地。When the output driving module adopts a low voltage dropout linear regulator structure, the output driving module further includes: a driving tube, a first voltage dividing resistor and a second voltage dividing resistor. The gate of the driving tube is connected to the trap. The output end of the wave filter unit, the source is connected to the power supply voltage, the drain is connected to the first end of the first voltage dividing resistor and serves as the output end of the output driving module, and the second end of the first voltage dividing resistor is connected to The first end of the second voltage dividing resistor generates the feedback voltage, and the second end of the second voltage dividing resistor is connected to ground.
可选地，所述斩波调制单元包括：第十三斩波开关、第十四斩波开关、第十五斩波开关及第十六斩波开关；所述第十三斩波开关的第一端与所述第十五斩波开关的第一端相连并连接所述电压产生模块的输出端，所述第十四斩波开关的第一端与所述第十六斩波开关的第一端相连并连接所述反馈电压，所述第十三斩波开关的第二端与所述第十四斩波开关的第二端相连并作为所述斩波调制单元的第一输出端，所述第十五斩波开关的第二端与所述第十六斩波开关的第二端相连并作为所述斩波调制单元的第二输出端；其中，所述第十三斩波开关和所述第十六斩波开关受控于第一时钟，所述第十四斩波开关和所述第十五斩波开关受控于第二时钟，所述第一时钟和所述第二时钟互为一组反相时钟。。Optionally, the chopper modulation unit includes: a thirteenth chopper switch, a fourteenth chopper switch, a fifteenth chopper switch and a sixteenth chopper switch; the third chopper switch of the thirteenth chopper switch One end is connected to the first end of the fifteenth chopper switch and the output end of the voltage generating module, and the first end of the fourteenth chopper switch is connected to the first end of the sixteenth chopper switch. One end is connected to the feedback voltage, and the second end of the thirteenth chopper switch is connected to the second end of the fourteenth chopper switch and serves as the first output end of the chopper modulation unit, The second end of the fifteenth chopper switch is connected to the second end of the sixteenth chopper switch and serves as the second output end of the chopper modulation unit; wherein, the thirteenth chopper switch and the sixteenth chopper switch is controlled by a first clock, the fourteenth chopper switch and the fifteenth chopper switch are controlled by a second clock, the first clock and the second The clocks are a set of inverted clocks. .
可选地，所述放大解调单元包括：第十四MOS管、第十五MOS管、第十六MOS管、第十七MOS管、第十八MOS管、第十七斩波开关、第十八斩波开关、第十九斩波开关及第二十斩波开关；所述第十四MOS管的栅极连接栅控电压，源极连接电源电压，漏极连接所述第十五MOS管的源极和所述第十六MOS管的源极；所述第十五MOS管的栅极和所述第 十六MOS管的栅极对应连接所述斩波调制单元的两个输出端，所述第十五MOS管的漏极连接所述第十七MOS管的漏极、所述第十七斩波开关的第一端和所述第十八斩波开关的第一端，所述第十六MOS管的漏极连接所述第十八MOS管的漏极、所述第十九斩波开关的第一端和所述第二十斩波开关的第一端；所述第十七MOS管的栅极连接所述第十八MOS管的栅极，所述第十七MOS管的源极和所述第十八MOS管的源极接地；所述第十七斩波开关的第二端连接所述第十九斩波开关的第二端并连接所述第十七MOS管的栅极，所述第十八斩波开关的第二端连接所述第二十斩波开关的第二端并作为所述放大解调单元的输出端；其中，所述第十七斩波开关和所述第二十斩波开关受控于第一时钟，所述第十八斩波开关和所述第十九斩波开关受控于第二时钟，所述第一时钟和所述第二时钟互为一组反相时钟。Optionally, the amplification and demodulation unit includes: a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a seventeenth chopper switch, a Eighteenth chopper switch, nineteenth chopper switch and twentieth chopper switch; the gate of the fourteenth MOS transistor is connected to the gate control voltage, the source is connected to the power supply voltage, and the drain is connected to the fifteenth MOS transistor. The source of the tube and the source of the sixteenth MOS tube; the gate of the fifteenth MOS tube and the The gates of the sixteenth MOS tube are connected to the two output terminals of the chopper modulation unit, and the drain of the fifteenth MOS tube is connected to the drain of the seventeenth MOS tube and the seventeenth chopper modulation unit. The first end of the switch and the first end of the eighteenth chopper switch, the drain of the sixteenth MOS transistor is connected to the drain of the eighteenth MOS transistor and the drain of the nineteenth chopper switch. The first end and the first end of the twentieth chopper switch; the gate of the seventeenth MOS transistor is connected to the gate of the eighteenth MOS transistor, and the source of the seventeenth MOS transistor is connected to the first end of the twentieth chopper switch. The source of the eighteenth MOS transistor is grounded; the second end of the seventeenth chopper switch is connected to the second end of the nineteenth chopper switch and connected to the gate of the seventeenth MOS transistor, The second end of the eighteenth chopper switch is connected to the second end of the twentieth chopper switch and serves as the output end of the amplification and demodulation unit; wherein, the seventeenth chopper switch and the The twentieth chopper switch is controlled by a first clock. The eighteenth chopper switch and the nineteenth chopper switch are controlled by a second clock. The first clock and the second clock are mutually exclusive. A set of inverted clocks.
或者，所述放大解调单元包括：第十四MOS管、第十五MOS管、第十六MOS管、第十七MOS管、第十八MOS管、第十九MOS管、第二十MOS管、第二十一MOS管、第二十二MOS管、第二十三MOS管、第二十四MOS管、第十七斩波开关、第十八斩波开关、第十九斩波开关、第二十斩波开关、第二十一斩波开关、第二十二斩波开关、第二十三斩波开关及第二十四斩波开关；所述第十四MOS管的栅极和所述第十五MOS管的栅极对应连接所述斩波调制单元的两个输出端，所述第十四MOS管的源极和所述第十五MOS管的源极连接所述第十六MOS管的漏极，所述第十四MOS管的漏极连接所述第二十三MOS管的漏极，所述第十五MOS管的漏极连接所述第二十四MOS管的漏极；所述第十六MOS管的栅极连接第一栅控电压，源极连接所述第十七MOS管的源极和所述第十八MOS管的源极并连接电源电压；所述第十七MOS管的栅极连接所述第十八MOS管的栅极并连接第二栅控电压，所述第十七MOS管的漏极连接所述第十七斩波开关的第一端和所述第十九斩波开关的第一端，所述第十八MOS管的漏极连接所述第十八斩波开关的第一端和所述第二十斩波开关的第一端；所述第十七斩波开关的第二端与所述第十八斩波开关的第二端相连并连接所述第十九MOS管的源极，所述第十九斩波开关的第二端与所述第二十斩波开关的第二端相连并连接所述第二十MOS管的源极；所述第十九MOS管的栅极连接所述第二十MOS管的栅极并连接第三栅控电压，所述第十九MOS管的漏极连接所述第二十一MOS管的漏极、所述第二十一斩波开关的第一端和所述第二十二斩波开关的第一端，所述第二十MOS管的漏极连接所述第二十二MOS管的漏极、所述第二十三斩波开关的第一端和所述第二十四斩波开关的第一端；所述第二十一MOS管的栅极连接所述第二十二MOS管的栅极并连接第四栅控电压，所述第二十一MOS管的源极连接所述第二十三MOS管的漏极，所述第二十二MOS管的源极连接所述第二十四MOS管的漏极；所述第二十三MOS管的栅极连接所述第二十四MOS管 的栅极，所述第二十三MOS管的源极和所述第二十四MOS管的源极接地；所述第二十一斩波开关的第二端连接所述第二十三斩波开关的第二端并连接所述第二十三MOS管的栅极，所述第二十二斩波开关的第二端连接所述第二十四斩波开关的第二端并作为所述放大解调单元的输出端；其中，所述第十七斩波开关、所述第二十斩波开关、所述第二十一斩波开关和所述第二十四斩波开关受控于第一时钟，所述第十八斩波开关、所述第十九斩波开关、所述第二十二斩波开关和所述第二十三斩波开关受控于第二时钟，所述第一时钟和所述第二时钟互为一组反相时钟。Alternatively, the amplification and demodulation unit includes: a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube tube, the twenty-first MOS tube, the twenty-second MOS tube, the twenty-third MOS tube, the twenty-fourth MOS tube, the seventeenth chopper switch, the eighteenth chopper switch, the nineteenth chopper switch , the twentieth chopper switch, the twenty-first chopper switch, the twenty-second chopper switch, the twenty-third chopper switch and the twenty-fourth chopper switch; the gate of the fourteenth MOS tube The gate of the fifteenth MOS transistor is connected to the two output terminals of the chopper modulation unit, and the source of the fourteenth MOS transistor and the source of the fifteenth MOS transistor are connected to the source of the first MOS transistor. The drain of the sixteenth MOS tube, the drain of the fourteenth MOS tube is connected to the drain of the twenty-third MOS tube, and the drain of the fifteenth MOS tube is connected to the twenty-fourth MOS tube. The drain of the sixteenth MOS transistor is connected to the first gate control voltage, and the source is connected to the source of the seventeenth MOS transistor and the source of the eighteenth MOS transistor and connected to the power supply voltage; The gate of the seventeenth MOS transistor is connected to the gate of the eighteenth MOS transistor and connected to the second gate control voltage, and the drain of the seventeenth MOS transistor is connected to the seventh gate of the seventeenth chopper switch. One end is connected to the first end of the nineteenth chopper switch, and the drain of the eighteenth MOS tube is connected to the first end of the eighteenth chopper switch and the twentieth chopper switch. One end; the second end of the seventeenth chopper switch is connected to the second end of the eighteenth chopper switch and connected to the source of the nineteenth MOS tube. The nineteenth chopper switch The second end of the switch is connected to the second end of the twentieth chopper switch and connected to the source of the twentieth MOS tube; the gate of the nineteenth MOS tube is connected to the gate of the twentieth MOS tube. The gate is also connected to the third gate control voltage, and the drain of the nineteenth MOS transistor is connected to the drain of the twenty-first MOS transistor, the first end of the twenty-first chopper switch and the first end of the chopper switch. The first end of the twenty-second chopper switch, the drain of the twentieth MOS transistor is connected to the drain of the twenty-second MOS transistor, the first end of the twenty-third chopper switch and the The first end of the twenty-fourth chopper switch; the gate of the twenty-first MOS transistor is connected to the gate of the twenty-second MOS transistor and connected to the fourth gate control voltage. The source of the tube is connected to the drain of the twenty-third MOS tube, and the source of the twenty-second MOS tube is connected to the drain of the twenty-fourth MOS tube; The gate is connected to the twenty-fourth MOS tube The gate of the twenty-third MOS transistor and the source of the twenty-fourth MOS transistor are grounded; the second end of the twenty-first chopper switch is connected to the twenty-third chopper switch. The second end of the wave switch is connected to the gate of the twenty-third MOS transistor, and the second end of the twenty-second chopper switch is connected to the second end of the twenty-fourth chopper switch and serves as the The output end of the amplification and demodulation unit; wherein the seventeenth chopper switch, the twentieth chopper switch, the twenty-first chopper switch and the twenty-fourth chopper switch are controlled At the first clock, the eighteenth chopper switch, the nineteenth chopper switch, the twenty-second chopper switch and the twenty-third chopper switch are controlled by the second clock, so The first clock and the second clock are a set of inverted clocks.
可选地，所述陷波滤波单元包括：第六电阻、第七电阻、第八电阻、第四电容、第五电容及第六电容；所述第六电阻的第一端连接所述第四电容的第一端并连接所述放大解调单元的输出端，第二端连接所述第七电阻的第一端和所述第五电容的第一端；所述第四电容的第二端连接所述第六电容的第一端和所述第八电阻的第一端；所述第七电阻的第二端连接所述第六电容的第二端并作为所述陷波滤波单元的输出端；所述第五电容的第二端接地；所述第八电阻的第二端接地；其中，所述第六电阻、所述第七电阻和所述第八电阻采用开关电容电路实现，所述开关电容电路中开关的控制时钟与斩波时钟除频相移45°。Optionally, the notch filter unit includes: a sixth resistor, a seventh resistor, an eighth resistor, a fourth capacitor, a fifth capacitor and a sixth capacitor; the first end of the sixth resistor is connected to the fourth The first end of the capacitor is connected to the output end of the amplification and demodulation unit, and the second end is connected to the first end of the seventh resistor and the first end of the fifth capacitor; the second end of the fourth capacitor The first end of the sixth capacitor is connected to the first end of the eighth resistor; the second end of the seventh resistor is connected to the second end of the sixth capacitor and serves as the output of the notch filter unit terminal; the second terminal of the fifth capacitor is grounded; the second terminal of the eighth resistor is grounded; wherein the sixth resistor, the seventh resistor and the eighth resistor are implemented by a switched capacitor circuit, so The control clock of the switch in the switched capacitor circuit and the chopping clock are frequency-divided and phase-shifted by 45°.
可选地，所述开关电容电路中的开关采用NMOS管实现，其中，NMOS管的衬底中包括一个DPWDN隔离二极管及一个DDNPWPSUB隔离二极管。Optionally, the switches in the switched capacitor circuit are implemented using NMOS tubes, wherein the substrate of the NMOS tube includes a DPWDN isolation diode and a DDNPWPSUB isolation diode.
如上所述，本发明的基准电路，通过斩波调制模块、放大解调模块、陷波滤波模块和输出驱动模块的设计，可有效抑制放大器噪声对基准电压的影响，从而提升基准电压的噪声特性；而且，各模块可采用极小的片内电路实现，占用面积小，且系统环路稳定性好。As mentioned above, the reference circuit of the present invention can effectively suppress the impact of amplifier noise on the reference voltage through the design of the chopper modulation module, amplification demodulation module, notch filter module and output driver module, thereby improving the noise characteristics of the reference voltage. ; Moreover, each module can be implemented using extremely small on-chip circuits, occupying a small area and having good system loop stability.
附图说明Description of drawings
图1显示为现有由前置放大器和模数转换器构成的信号处理系统的示意图。Figure 1 shows a schematic diagram of an existing signal processing system consisting of a preamplifier and an analog-to-digital converter.
图2显示为本发明基准电路的示意图。Figure 2 shows a schematic diagram of the reference circuit of the present invention.
图3显示为本发明斩波调制模块的示意图。Figure 3 shows a schematic diagram of the chopper modulation module of the present invention.
图4显示为图3示出斩波调制模块在第一时钟有效时的等效电路图。Figure 4 shows the equivalent circuit diagram of Figure 3 showing the chopper modulation module when the first clock is valid.
图5显示为图3示出斩波调制模块在第二时钟有效时的等效电路图。FIG. 5 shows an equivalent circuit diagram of the chopper modulation module shown in FIG. 3 when the second clock is active.
图6显示为本发明一种放大解调模块的示意图。Figure 6 shows a schematic diagram of an amplification and demodulation module of the present invention.
图7显示为图6示出放大解调模块在第一时钟有效时的等效电路图。图8显示为图6示出放大解调模块在第二时钟有效时的等效电路图。Figure 7 shows the equivalent circuit diagram of Figure 6 showing the amplification and demodulation module when the first clock is valid. Figure 8 shows the equivalent circuit diagram of Figure 6 showing the amplification and demodulation module when the second clock is valid.
图9显示为本发明另一种放大解调模块的示意图。 Figure 9 shows a schematic diagram of another amplification and demodulation module of the present invention.
图10显示为图9示出放大解调模块在第一时钟有效时的等效电路图。Figure 10 shows the equivalent circuit diagram of Figure 9 showing the amplification and demodulation module when the first clock is valid.
图11显示为图9示出放大解调模块在第二时钟有效时的等效电路图。FIG. 11 shows an equivalent circuit diagram of the amplification demodulation module when the second clock is valid as shown in FIG. 9 .
图12显示为本发明陷波滤波模块的示意图。Figure 12 shows a schematic diagram of the notch filter module of the present invention.
图13显示为本发明开关电容电路的示意图。Figure 13 shows a schematic diagram of the switched capacitor circuit of the present invention.
图14显示为NMOS管的衬底中设有隔离二极管的示意图。Figure 14 shows a schematic diagram of an isolation diode provided in the substrate of an NMOS transistor.
图15显示为本发明中与同步积分的陷波滤波器相关的时钟和电压波形图。Figure 15 shows the clock and voltage waveforms associated with the synchronous integration notch filter of the present invention.
图16显示为本发明输出驱动模块采用输出缓冲器实现时的示意图。Figure 16 shows a schematic diagram of the output driving module of the present invention implemented using an output buffer.
图17显示为本发明输出驱动模块采用低压差线性稳压器实现时的示意图。Figure 17 shows a schematic diagram of the output driving module of the present invention when it is implemented using a low voltage dropout linear regulator.
图18显示为输出缓冲器或低压差线性稳压器中一种误差放大器的示意图。Figure 18 shows a schematic diagram of an error amplifier in an output buffer or low-dropout linear regulator.
图19显示为输出缓冲器或低压差线性稳压器中另一种误差放大器的示意图。Figure 19 shows a schematic diagram of an alternative error amplifier in an output buffer or low-dropout linear regulator.
图20显示为针对输出缓冲器结构的电路级补偿方案的示意图。Figure 20 shows a schematic diagram of a circuit-level compensation scheme for an output buffer structure.
图21显示为本发明斩波调制单元的示意图。Figure 21 shows a schematic diagram of the chopper modulation unit of the present invention.
图22显示为图21示出斩波调制单元在第一时钟有效时的等效电路图。FIG. 22 shows an equivalent circuit diagram of the chopper modulation unit when the first clock is active as shown in FIG. 21 .
图23显示为图21示出斩波调制单元在第二时钟有效时的等效电路图。FIG. 23 shows an equivalent circuit diagram of the chopper modulation unit when the second clock is active as shown in FIG. 21 .
图24显示为本发明一种放大解调单元的示意图。Figure 24 shows a schematic diagram of an amplification demodulation unit of the present invention.
图25显示为图24示出放大解调单元在第一时钟有效时的等效电路图。FIG. 25 shows an equivalent circuit diagram of the amplification demodulation unit shown in FIG. 24 when the first clock is valid.
图26显示为图24示出放大解调单元在第二时钟有效时的等效电路图。FIG. 26 shows an equivalent circuit diagram of the amplification demodulation unit when the second clock is valid as shown in FIG. 24 .
图27显示为本发明另一种放大解调单元的示意图。Figure 27 shows a schematic diagram of another amplification and demodulation unit of the present invention.
图28显示为图27示出放大解调单元在第一时钟有效时的等效电路图。FIG. 28 shows an equivalent circuit diagram of the amplification demodulation unit when the first clock is valid as shown in FIG. 27 .
图29显示为图27示出放大解调单元在第二时钟有效时的等效电路图。FIG. 29 shows an equivalent circuit diagram of the amplification demodulation unit shown in FIG. 27 when the second clock is valid.
图30显示为本发明陷波滤波单元的示意图。Figure 30 shows a schematic diagram of the notch filter unit of the present invention.
图31显示为针对低压差线性稳压器结构的电路级补偿方案的示意图。Figure 31 shows a schematic diagram of a circuit-level compensation scheme for a low-dropout linear regulator architecture.
元件标号说明Component label description
10                     基准电路10 Reference circuit
100                    电压产生模块100 Voltage generation module
200                    斩波调制模块200 chopper modulation module
300                    放大解调模块300 Amplification and Demodulation Module
400                    陷波滤波模块400 notch filter module
500                    输出驱动模块 500 output driver module
501                    斩波调制单元501 Chopper Modulation Unit
502                    放大解调单元502 Amplification and demodulation unit
503                    陷波滤波单元503 Notch filter unit
具体实施方式Detailed ways
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
请参阅图2至图31。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，虽图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的形态、数量及比例可为一种随意的改变，且其组件布局形态也可能更为复杂。See Figure 2 through Figure 31. It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Although the diagrams only show the components related to the present invention and do not follow the actual implementation of the component number, shape and Dimension drawing, in actual implementation, the shape, quantity and proportion of each component can be changed at will, and the component layout may also be more complex.
如图2所示，本实施例提供一种基准电路10，该基准电路10包括：电压产生模块100、斩波调制模块200、放大解调模块300及陷波滤波模块400。进一步的，该基准电路10还包括：输出驱动模块500。As shown in Figure 2, this embodiment provides a reference circuit 10. The reference circuit 10 includes: a voltage generation module 100, a chopper modulation module 200, an amplification demodulation module 300, and a notch filter module 400. Further, the reference circuit 10 also includes: an output driving module 500 .
电压产生模块100用于根据正温度系数电压VP和负温度系数电压VN产生基准电压VREF并输出，以及，根据偏置电压VB’调控正温度系数电压VP和负温度系数电压VN，以使二者相等。The voltage generation module 100 is used to generate and output a reference voltage VREF according to the positive temperature coefficient voltage VP and the negative temperature coefficient voltage VN, and to regulate the positive temperature coefficient voltage VP and the negative temperature coefficient voltage VN according to the bias voltage VB', so that both equal.
作为示例，如图2所示，电压产生模块100包括：第一MOS管M1、第二MOS管M2、第一电阻R1、第二电阻R2、第一三极管Q1及第二三极管Q2；第一MOS管M1的栅极和第二MOS管M2的栅极连接偏置电压VB’，第一MOS管M1的源极和第二MOS管M2的源极连接电源电压VDD，第一MOS管M1的漏极连接第一电阻R1的第一端并作为电压产生模块100的正电压端以产生正温度系数电压VP，第二MOS管M2的漏极连接第二电阻R2的第一端并作为电压产生模块100的输出端以输出基准电压VREF；第一电阻R1的第二端连接第一三极管Q1的发射极；第二电阻R2的第二端连接第二三极管Q2的发射极并作为电压产生模块100的负电压端以产生负温度系数电压VN；第一三极管Q1的基极与其集电极相连并接地，第二三极管Q2的基极与其集电极相连并接地。As an example, as shown in FIG. 2 , the voltage generation module 100 includes: a first MOS transistor M1, a second MOS transistor M2, a first resistor R1, a second resistor R2, a first transistor Q1 and a second transistor Q2. ;The gate of the first MOS transistor M1 and the gate of the second MOS transistor M2 are connected to the bias voltage VB', the source of the first MOS transistor M1 and the source of the second MOS transistor M2 are connected to the power supply voltage VDD, and the first MOS The drain of the tube M1 is connected to the first terminal of the first resistor R1 and serves as the positive voltage terminal of the voltage generation module 100 to generate the positive temperature coefficient voltage VP. The drain of the second MOS tube M2 is connected to the first terminal of the second resistor R2 and As the output end of the voltage generation module 100, the reference voltage VREF is output; the second end of the first resistor R1 is connected to the emitter of the first transistor Q1; the second end of the second resistor R2 is connected to the emitter of the second transistor Q2. The base of the first transistor Q1 is connected to its collector and grounded, and the base of the second transistor Q2 is connected to its collector and grounded. .
需要说明的是，电压产生模块100的具体电路并不局限于此，上述电路结构仅是一种示例；其可以是现有任意一种包括运放的带隙基准电路中除运放之外的电路结构，本实施例对 此不做限制。另外，电压产生模块100如何根据正温度系数电压VP和负温度系数电压VN产生基准电压VREF，以及，如何根据偏置电压VB’调控正温度系数电压VP和负温度系数电压VN使二者相等，是本领域技术人员所公知的，此处不再赘述。It should be noted that the specific circuit of the voltage generation module 100 is not limited to this, and the above circuit structure is only an example; it can be any existing bandgap reference circuit including an operational amplifier, except for the operational amplifier. Circuit structure, this embodiment is suitable for There is no restriction on this. In addition, how the voltage generation module 100 generates the reference voltage VREF according to the positive temperature coefficient voltage VP and the negative temperature coefficient voltage VN, and how to regulate the positive temperature coefficient voltage VP and the negative temperature coefficient voltage VN according to the bias voltage VB' to make them equal, It is well known to those skilled in the art and will not be described in detail here.
斩波调制模块200连接电压产生模块100的正电压端和负电压端，用于根据斩波频率对正温度系数电压VP和负温度系数电压VN进行斩波调制。The chopper modulation module 200 is connected to the positive voltage terminal and the negative voltage terminal of the voltage generation module 100, and is used to perform chopper modulation on the positive temperature coefficient voltage VP and the negative temperature coefficient voltage VN according to the chopping frequency.
作为示例，如图3所示，斩波调制模块200包括：第一斩波开关K1、第二斩波开关K2、第三斩波开关K3及第四斩波开关K4；第一斩波开关K1的第一端与第三斩波开关K3的第一端相连并连接电压产生模块100的正电压端以接入正温度系数电压VP，第二斩波开关K2的第一端与第四斩波开关K4的第一端相连并连接电压产生模块100的负电压端以接入负温度系数电压VN，第一斩波开关K1的第二端与第二斩波开关K2的第二端相连并作为斩波调制模块200的第一输出端TP，第三斩波开关K3的第二端与第四斩波开关K4的第二端相连并作为斩波调制模块200的第二输出端TN；其中，第一斩波开关K1和第四斩波开关K4受控于第一时钟，第二斩波开关K2和第三斩波开关K3受控于第二时钟，第一时钟和第二时钟互为一组反相时钟。需要说明的是，第一时钟即为斩波时钟，其频率即为斩波频率。As an example, as shown in FIG. 3 , the chopper modulation module 200 includes: a first chopper switch K1 , a second chopper switch K2 , a third chopper switch K3 and a fourth chopper switch K4 ; the first chopper switch K1 The first terminal of is connected to the first terminal of the third chopper switch K3 and is connected to the positive voltage terminal of the voltage generation module 100 to access the positive temperature coefficient voltage VP, and the first terminal of the second chopper switch K2 is connected to the fourth chopper switch K3. The first end of the switch K4 is connected to the negative voltage end of the voltage generation module 100 to access the negative temperature coefficient voltage VN, and the second end of the first chopper switch K1 is connected to the second end of the second chopper switch K2 and serves as The first output terminal TP of the chopper modulation module 200 and the second terminal of the third chopper switch K3 are connected to the second terminal of the fourth chopper switch K4 and serve as the second output terminal TN of the chopper modulation module 200; wherein, The first chopper switch K1 and the fourth chopper switch K4 are controlled by the first clock, the second chopper switch K2 and the third chopper switch K3 are controlled by the second clock, and the first clock and the second clock are one with each other. Set of inverted clocks. It should be noted that the first clock is the chopping clock, and its frequency is the chopping frequency.
本示例中，在第一斩波开关K1和第四斩波开关K4受控于第一时钟闭合时，第二斩波开关K2和第三斩波开关K3受控于第二时钟断开，等效电路如图4所示，此时，斩波调制模块200的第一输出端TP输出正温度系数电压VP，第二输出端TN输出负温度系数电压VN；在第一斩波开关K1和第四斩波开关K4受控于第一时钟断开时，第二斩波开关K2和第三斩波开关K3受控于第二时钟闭合，等效电路如图5所示，此时，斩波调制模块200的第一输出端TP输出负温度系数电压VN，第二输出端TN输出正温度系数电压VP。In this example, when the first chopper switch K1 and the fourth chopper switch K4 are controlled to be closed by the first clock, the second chopper switch K2 and the third chopper switch K3 are controlled to be turned off by the second clock, etc. The effective circuit is shown in Figure 4. At this time, the first output terminal TP of the chopper modulation module 200 outputs the positive temperature coefficient voltage VP, and the second output terminal TN outputs the negative temperature coefficient voltage VN; between the first chopper switch K1 and the When the four chopper switch K4 is controlled by the first clock to turn off, the second chopper switch K2 and the third chopper switch K3 are controlled by the second clock to close. The equivalent circuit is shown in Figure 5. At this time, the chopper The first output terminal TP of the modulation module 200 outputs the negative temperature coefficient voltage VN, and the second output terminal TN outputs the positive temperature coefficient voltage VP.
放大解调模块300连接斩波调制模块200的两个输出端TP和TN，用于对经过斩波调制的正温度系数电压和负温度系数电压进行运放处理后再根据斩波频率进行斩波解调并产生偏置电压VB，以及，根据斩波频率对放大解调模块300中的放大器噪声进行斩波调制。The amplification and demodulation module 300 is connected to the two output terminals TP and TN of the chopper modulation module 200, and is used to perform operational amplifier processing on the chopper-modulated positive temperature coefficient voltage and negative temperature coefficient voltage, and then chop them according to the chopping frequency. The bias voltage VB is demodulated and generated, and the amplifier noise in the amplification and demodulation module 300 is chopper-modulated according to the chopping frequency.
作为一示例，如图6所示，放大解调模块300包括：第三MOS管M3、第四MOS管M4、第五MOS管M5、第六MOS管M6、第七MOS管M7、第五斩波开关K5、第六斩波开关K6、第七斩波开关K7及第八斩波开关K8；第三MOS管M3的栅极连接栅控电压Vb，源极连接电源电压VDD，漏极连接第四MOS管M4的源极和第五MOS管M5的源极；第四MOS管M4的栅极和第五MOS管M5的栅极对应连接斩波调制模块200的两个输出端(如第四MOS管M4的栅极连接斩波调制模块200的第一输出端TP，第五MOS管M5的栅极连接斩波调制模块200的第二输出端TN)，第四MOS管M4的漏极连接第六MOS管M6的漏极、 第五斩波开关K5的第一端和第六斩波开关K6的第一端，第五MOS管M5的漏极连接第七MOS管M7的漏极、第七斩波开关K7的第一端和第八斩波开关K8的第一端；第六MOS管M6的栅极连接第七MOS管M7的栅极，第六MOS管M6的源极和第七MOS管M7的源极接地；第五斩波开关K5的第二端连接第七斩波开关K7的第二端并连接第六MOS管M6的栅极，第六斩波开关K6的第二端连接第八斩波开关K8的第二端并作为放大解调模块300的输出端；其中，第五斩波开关K5和第八斩波开关K8受控于第一时钟，第六斩波开关K6和第七斩波开关K7受控于第二时钟，第一时钟和第二时钟互为一组反相时钟。As an example, as shown in FIG. 6 , the amplification and demodulation module 300 includes: a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, a fifth MOS transistor M7, and a third MOS transistor M4. Wave switch K5, sixth chopper switch K6, seventh chopper switch K7 and eighth chopper switch K8; the gate of the third MOS transistor M3 is connected to the gate control voltage Vb, the source is connected to the power supply voltage VDD, and the drain is connected to the third MOS transistor M3. The source of the fourth MOS transistor M4 and the source of the fifth MOS transistor M5; the gate of the fourth MOS transistor M4 and the gate of the fifth MOS transistor M5 are respectively connected to the two output terminals of the chopper modulation module 200 (such as the fourth The gate of the MOS transistor M4 is connected to the first output terminal TP of the chopper modulation module 200, the gate of the fifth MOS transistor M5 is connected to the second output terminal TN) of the chopper modulation module 200, and the drain of the fourth MOS transistor M4 is connected to The drain of the sixth MOS tube M6, The first terminal of the fifth chopper switch K5 and the first terminal of the sixth chopper switch K6. The drain of the fifth MOS tube M5 is connected to the drain of the seventh MOS tube M7 and the first terminal of the seventh chopper switch K7. and the first end of the eighth chopper switch K8; the gate of the sixth MOS transistor M6 is connected to the gate of the seventh MOS transistor M7, the source of the sixth MOS transistor M6 and the source of the seventh MOS transistor M7 are grounded; The second terminal of the fifth chopper switch K5 is connected to the second terminal of the seventh chopper switch K7 and connected to the gate of the sixth MOS transistor M6, and the second terminal of the sixth chopper switch K6 is connected to the third terminal of the eighth chopper switch K8. The two terminals are used as the output terminal of the amplification and demodulation module 300; among them, the fifth chopper switch K5 and the eighth chopper switch K8 are controlled by the first clock, and the sixth chopper switch K6 and the seventh chopper switch K7 are controlled by the first clock. Regarding the second clock, the first clock and the second clock are a set of inverted clocks.
本示例中，在第五斩波开关K5和第八斩波开关K8受控于第一时钟闭合时，第六斩波开关K6和第七斩波开关K7受控于第二时钟断开，等效电路如图7所示；在第五斩波开关K5和第八斩波开关K8受控于第一时钟断开时，第六斩波开关K6和第七斩波开关K7受控于第二时钟闭合，等效电路如图8所示。第三MOS管M3至第七MOS管M7构成运放电路，第五斩波开关K5至第八斩波开关K8与前级斩波调制模块200配合使用来完成电压信号的调制和解调，同时，第五斩波开关K5至第八斩波开关K8还对运放的放大器噪声进行斩波调制，以将放大器噪声从低频调制至高频。In this example, when the fifth chopper switch K5 and the eighth chopper switch K8 are controlled to be closed by the first clock, the sixth chopper switch K6 and the seventh chopper switch K7 are controlled to be turned off by the second clock, etc. The effective circuit is shown in Figure 7; when the fifth chopper switch K5 and the eighth chopper switch K8 are controlled by the first clock to turn off, the sixth chopper switch K6 and the seventh chopper switch K7 are controlled by the second clock. The clock is closed and the equivalent circuit is shown in Figure 8. The third MOS transistor M3 to the seventh MOS transistor M7 constitute an operational amplifier circuit, and the fifth to eighth chopper switches K5 to K8 are used in conjunction with the front-stage chopper modulation module 200 to complete the modulation and demodulation of the voltage signal. , the fifth chopper switch K5 to the eighth chopper switch K8 also perform chopper modulation on the amplifier noise of the operational amplifier to modulate the amplifier noise from low frequency to high frequency.
作为另一示例，如图9所示，放大解调模块300包括：第三MOS管M3、第四MOS管M4、第五MOS管M5、第六MOS管M6、第七MOS管M7、第八MOS管M8、第九MOS管M9、第十MOS管M10、第十一MOS管M11、第十二MOS管M12、第十三MOS管M13、第五斩波开关K5、第六斩波开关K6、第七斩波开关K7、第八斩波开关K8、第九斩波开关K9、第十斩波开关K10、第十一斩波开关K11及第十二斩波开关K12；第三MOS管M3的栅极和第四MOS管M4的栅极对应连接斩波调制模块200的两个输出端(如第三MOS管M3的栅极连接斩波调制模块200的第一输出端TP，第四MOS管M4的栅极连接斩波调制模块200的第二输出端TN)，第三MOS管M3的源极和第四MOS管M4的源极连接第五MOS管M5的漏极，第三MOS管M3的漏极连接第十二MOS管的漏极，第四MOS管M4的漏极连接第十三MOS管M13的漏极；第五MOS管M5的栅极连接第一栅控电压Vb1，源极连接第六MOS管M6的源极和第七MOS管M7的源极并连接电源电压VDD；第六MOS管M6的栅极连接第七MOS管M7的栅极并连接第二栅控电压Vb2，第六MOS管M6的漏极连接第五斩波开关K5的第一端和第七斩波开关K7的第一端，第七MOS管M7的漏极连接第六斩波开关K6的第一端和第八斩波开关K8的第一端；第五斩波开关K5的第二端与第六斩波开关K6的第二端相连并连接第八MOS管M8的源极，第七斩波开关K7的第二端与第八斩波开关K8的第二端相连并连接第九MOS管M9的源极；第八MOS管M8的栅极连接 第九MOS管M9的栅极并连接第三栅控电压Vb3，第八MOS管M8的漏极连接第十MOS管M10的漏极、第九斩波开关K9的第一端和第十斩波开关K10的第一端，第九MOS管M9的漏极连接第十一MOS管M11的漏极、第十一斩波开关K11的第一端和第十二斩波开关K12的第一端；第十MOS管M10的栅极连接第十一MOS管M11的栅极并连接第四栅控电压Vb4，第十MOS管M10的源极连接第十二MOS管M12的漏极，第十一MOS管M11的源极连接第十三MOS管M13的漏极；第十二MOS管M12的栅极连接第十三MOS管M13的栅极，第十二MOS管M12的源极和第十三MOS管M13的源极接地；第九斩波开关K9的第二端连接第十一斩波开关K11的第二端并连接第十二MOS管M12的栅极，第十斩波开关K10的第二端连接第十二斩波开关K12的第二端并作为放大解调模块300的输出端；其中，第五斩波开关K5、第八斩波开关K8、第九斩波开关K9、第十二斩波开关K12受控于第一时钟，第六斩波开关K6、第七斩波开关K7、第十斩波开关K10、第十一斩波开关K11受控于第二时钟，第一时钟和第二时钟互为一组反相时钟。As another example, as shown in FIG. 9 , the amplification and demodulation module 300 includes: a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, an eighth MOS transistor M7. MOS tube M8, ninth MOS tube M9, tenth MOS tube M10, eleventh MOS tube M11, twelfth MOS tube M12, thirteenth MOS tube M13, fifth chopper switch K5, sixth chopper switch K6 , the seventh chopper switch K7, the eighth chopper switch K8, the ninth chopper switch K9, the tenth chopper switch K10, the eleventh chopper switch K11 and the twelfth chopper switch K12; the third MOS tube M3 The gate of the third MOS transistor M4 and the gate of the fourth MOS transistor M4 are respectively connected to the two output terminals of the chopper modulation module 200 (for example, the gate of the third MOS transistor M3 is connected to the first output terminal TP of the chopper modulation module 200, and the fourth MOS transistor M4 is connected to the first output terminal TP of the chopper modulation module 200. The gate of the tube M4 is connected to the second output terminal TN) of the chopper modulation module 200, and the sources of the third MOS tube M3 and the fourth MOS tube M4 are connected to the drain of the fifth MOS tube M5. The drain of M3 is connected to the drain of the twelfth MOS transistor, the drain of the fourth MOS transistor M4 is connected to the drain of the thirteenth MOS transistor M13; the gate of the fifth MOS transistor M5 is connected to the first gate control voltage Vb1, the source The gate electrode of the sixth MOS transistor M6 is connected to the gate electrode of the seventh MOS transistor M7 and connected to the second gate control voltage Vb2. , the drain of the sixth MOS transistor M6 is connected to the first terminal of the fifth chopper switch K5 and the first terminal of the seventh chopper switch K7, and the drain of the seventh MOS tube M7 is connected to the first terminal of the sixth chopper switch K6. terminal and the first terminal of the eighth chopper switch K8; the second terminal of the fifth chopper switch K5 is connected to the second terminal of the sixth chopper switch K6 and connected to the source of the eighth MOS tube M8, and the seventh chopper switch K5 The second end of the switch K7 is connected to the second end of the eighth chopper switch K8 and connected to the source of the ninth MOS tube M9; the gate of the eighth MOS tube M8 is connected The gate of the ninth MOS transistor M9 is also connected to the third gate control voltage Vb3, and the drain of the eighth MOS transistor M8 is connected to the drain of the tenth MOS transistor M10, the first end of the ninth chopper switch K9 and the tenth chopper switch K9. The first terminal of the switch K10 and the drain of the ninth MOS tube M9 are connected to the drain of the eleventh MOS tube M11, the first terminal of the eleventh chopper switch K11 and the first terminal of the twelfth chopper switch K12; The gate of the tenth MOS transistor M10 is connected to the gate of the eleventh MOS transistor M11 and connected to the fourth gate control voltage Vb4. The source of the tenth MOS transistor M10 is connected to the drain of the twelfth MOS transistor M12. The eleventh MOS transistor The source of the tube M11 is connected to the drain of the thirteenth MOS tube M13; the gate of the twelfth MOS tube M12 is connected to the gate of the thirteenth MOS tube M13, and the source of the twelfth MOS tube M12 and the thirteenth MOS The source of the tube M13 is grounded; the second terminal of the ninth chopper switch K9 is connected to the second terminal of the eleventh chopper switch K11 and connected to the gate of the twelfth MOS tube M12; the second terminal of the tenth chopper switch K10 The terminal is connected to the second terminal of the twelfth chopper switch K12 and serves as the output terminal of the amplification and demodulation module 300; wherein, the fifth chopper switch K5, the eighth chopper switch K8, the ninth chopper switch K9, the twelfth chopper switch K9 The chopper switch K12 is controlled by the first clock, the sixth chopper switch K6, the seventh chopper switch K7, the tenth chopper switch K10 and the eleventh chopper switch K11 are controlled by the second clock, the first clock and The second clocks are a set of inverted clocks.
本示例中，在第五斩波开关K5、第八斩波开关K8、第九斩波开关K9、第十二斩波开关K12受控于第一时钟闭合时，第六斩波开关K6、第七斩波开关K7、第十斩波开关K10、第十一斩波开关K11受控于第二时钟断开，等效电路如图10所示；在第五斩波开关K5、第八斩波开关K8、第九斩波开关K9、第十二斩波开关K12受控于第一时钟断开时，第六斩波开关K6、第七斩波开关K7、第十斩波开关K10、第十一斩波开关K11受控于第二时钟闭合，等效电路如图11所示。第三MOS管M3至第十三MOS管M13构成运放电路，第五斩波开关K5至第十二斩波开关K12与前级斩波调制模块200配合使用来完成电压信号的调制和解调，同时，第五斩波开关K5至第十二斩波开关K12还对运放的放大器噪声进行斩波调制，以将放大器噪声从低频调制至高频。In this example, when the fifth chopper switch K5, the eighth chopper switch K8, the ninth chopper switch K9, and the twelfth chopper switch K12 are controlled by the first clock to close, the sixth chopper switch K6, the The seventh chopper switch K7, the tenth chopper switch K10, and the eleventh chopper switch K11 are controlled to be turned off by the second clock. The equivalent circuit is shown in Figure 10; in the fifth chopper switch K5, the eighth chopper switch When the switch K8, the ninth chopper switch K9, and the twelfth chopper switch K12 are controlled by the first clock being turned off, the sixth chopper switch K6, the seventh chopper switch K7, the tenth chopper switch K10, and the tenth chopper switch K12 are controlled by the first clock. A chopper switch K11 is controlled to close by the second clock, and the equivalent circuit is shown in Figure 11. The third MOS transistor M3 to the thirteenth MOS transistor M13 constitute an operational amplifier circuit, and the fifth to twelfth chopper switches K5 to K12 are used in conjunction with the front-stage chopper modulation module 200 to complete the modulation and demodulation of the voltage signal. , at the same time, the fifth chopper switch K5 to the twelfth chopper switch K12 also perform chopper modulation on the amplifier noise of the operational amplifier to modulate the amplifier noise from low frequency to high frequency.
陷波滤波模块400连接放大解调模块300的输出端，用于在斩波频率点对放大器噪声进行陷波处理，以此减弱偏置电压VB上的时钟毛刺。The notch filter module 400 is connected to the output end of the amplification and demodulation module 300, and is used to notch the amplifier noise at the chopping frequency point, thereby reducing the clock glitch on the bias voltage VB.
作为示例，如图12所示，陷波滤波模块400包括：第三电阻R3、第四电阻R4、第五电阻R5、第一电容C1、第二电容C2及第三电容C3；第三电阻R3的第一端连接第一电容C1的第一端并连接放大解调模块300的输出端以接入偏置电压VB，第二端连接第四电阻R4的第一端和第二电容C2的第一端；第一电容C1的第二端连接第三电容C3的第一端和第五电阻R5的第一端；第四电阻的第二端连接第三电容的第二端并作为陷波滤波模块400的输出端以输出经过滤波的偏置电压VB’；第二电容C2的第二端接地；第五电阻R5的第二端接地；其中，第三电阻R3、第四电阻R4和第五电阻R5采用开关电容电路实现，该开关电容电路 中开关的控制时钟与斩波时钟(即第一时钟)除频相移45°。As an example, as shown in Figure 12, the notch filter module 400 includes: a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, a second capacitor C2 and a third capacitor C3; the third resistor R3 The first end is connected to the first end of the first capacitor C1 and the output end of the amplification and demodulation module 300 to access the bias voltage VB, and the second end is connected to the first end of the fourth resistor R4 and the second end of the second capacitor C2 One end; the second end of the first capacitor C1 is connected to the first end of the third capacitor C3 and the first end of the fifth resistor R5; the second end of the fourth resistor is connected to the second end of the third capacitor and serves as a notch filter The output terminal of the module 400 outputs the filtered bias voltage VB'; the second terminal of the second capacitor C2 is connected to the ground; the second terminal of the fifth resistor R5 is connected to the ground; wherein, the third resistor R3, the fourth resistor R4 and the fifth resistor R5 are connected to the ground. Resistor R5 is implemented using a switched capacitor circuit. This switched capacitor circuit The control clock of the middle switch and the chopping clock (i.e. the first clock) are frequency-divided and phase-shifted by 45°.
具体的，开关电容电路包括电容C01、电容C02、开关K01和开关K02，其中，开关K01受控于控制时钟，开关K02受控于控制时钟的反相时钟(如图13所示)；其等效电阻为1/FC，F为控制时钟的频率，C为电容C01的容值。实际应用中，可设第三电阻R3和第四电阻R4的阻值相等，且为第五电阻R5的2倍；第一电容C1和第三电容C3的容值相等，且为第二电容C2的1/2。Specifically, the switched capacitor circuit includes capacitor C01, capacitor C02, switch K01 and switch K02, where switch K01 is controlled by the control clock and switch K02 is controlled by the inverse clock of the control clock (as shown in Figure 13); etc. The effective resistance is 1/FC, F is the frequency of the control clock, and C is the capacitance value of capacitor C01. In practical applications, the resistances of the third resistor R3 and the fourth resistor R4 can be set to be equal and twice the value of the fifth resistor R5; the capacitances of the first capacitor C1 and the third capacitor C3 can be set to be equal and equal to the resistance of the second capacitor C2. 1/2.
更具体的，开关电容电路中的开关(如开关K01和开关K02)采用NMOS管实现，其中，NMOS管的衬底中包括一个DPWDN(P阱/深N阱)隔离二极管及一个DDNPWPSUB(深P阱/深N阱)隔离二极管(如图14所示)。在NMOS管的衬底中增设DPWDN隔离二极管(如D1)和DDNPWPSUB隔离二极管(如D2)，避免了传统NMOS开关器件存在时钟馈通、沟道电荷注入、噪声串扰等影响，可优化开关特性，从而优化噪声性能。需要说明的是，如上NMOS管的制备可采用常规半导体工艺实现，本实施例对此不做限制。More specifically, the switches in the switched capacitor circuit (such as switch K01 and switch K02) are implemented using NMOS tubes. The substrate of the NMOS tube includes a DPWDN (P-well/deep N-well) isolation diode and a DDNPWPSUB (deep P-well) well/deep N-well) isolation diode (shown in Figure 14). Adding DPWDN isolation diodes (such as D1) and DDNPWPSUB isolation diodes (such as D2) to the substrate of the NMOS tube avoids the effects of clock feedthrough, channel charge injection, noise crosstalk and other effects of traditional NMOS switching devices, and can optimize switching characteristics. thereby optimizing noise performance. It should be noted that the above-mentioned preparation of the NMOS transistor can be implemented using conventional semiconductor processes, and this embodiment is not limited to this.
本示例中，陷波滤波模块400采用同步积分的陷波滤波器实现，该同步积分的陷波滤波器采用和前级放大解调模块300中斩波时钟除频相移45°的时钟信号作为开关电容电路中开关的控制时钟，通过在一个时钟周期对因放大器噪声所引起的时钟毛刺正反两部分进行积分，可有效降低时钟毛刺问题，也即，有效抑制放大器噪声的影响，从而提升基准电压的噪声特性(如图15所示)；而采用与前级斩波时钟相关的时钟作为控制时钟，避免了采用不相关时钟所引起的时钟混叠问题，及由此导致的将滤波器采样时钟处较大的噪声折回至低频，从而严重降低前级斩波调制的效果。另外，将该同步积分的陷波滤波器设于基准产生环路内，而非基准输出后方，可以有效降低输出端的波动。In this example, the notch filter module 400 is implemented using a synchronous integration notch filter. The synchronous integration notch filter uses a clock signal that is 45° divided and phase-shifted from the chopping clock in the pre-amplification demodulation module 300. The control clock of the switch in the switched capacitor circuit can effectively reduce the clock glitch problem by integrating the positive and negative parts of the clock glitch caused by the amplifier noise in one clock cycle, that is, effectively suppressing the influence of the amplifier noise, thereby improving the benchmark The noise characteristics of the voltage (as shown in Figure 15); using a clock related to the pre-stage chopping clock as the control clock avoids the clock aliasing problem caused by using irrelevant clocks, and the resulting filter sampling Larger noise at the clock folds back to low frequencies, severely reducing the effect of the pre-stage chopper modulation. In addition, locating the synchronous integration notch filter in the reference generation loop rather than behind the reference output can effectively reduce the fluctuation at the output end.
输出驱动模块500连接电压产生模块100的输出端，用于增强基准电压VREF的负载驱动能力。The output driving module 500 is connected to the output end of the voltage generating module 100 and is used to enhance the load driving capability of the reference voltage VREF.
作为示例，输出驱动模块500采用输出缓冲器或者低压差线性稳压器(LD0)来实现。As an example, the output driver module 500 is implemented using an output buffer or a low dropout linear regulator (LD0).
如图16所示，输出缓冲器包括：误差放大器EA，误差放大器EA的同相输入端连接电压产生模块100的输出端以接入基准电压VREF，反相输入端连接其输出端以接入反馈电压VFB，输出端则作为输出缓冲器的输出端以输出电压VO’并产生反馈电压VFB。As shown in Figure 16, the output buffer includes: an error amplifier EA. The non-inverting input end of the error amplifier EA is connected to the output end of the voltage generation module 100 to access the reference voltage VREF, and the inverting input end is connected to its output end to access the feedback voltage. VFB, the output terminal serves as the output terminal of the output buffer to output voltage VO' and generate feedback voltage VFB.
如图17所示，低压差线性稳压器包括：误差放大器EA、驱动管MP、第一分压电阻Rd1及第二分压电阻Rd2，误差放大器EA的反相输入端连接电压产生模块100的输出端以接入基准电压VREF，同相输入端连接第二分压电阻Rd2的第一端以接入反馈电压VFB，输出端连接驱动管MP的栅极，驱动管MP的源极连接电源电压VDD，漏极连接第一分压电阻Rd1 的第一端并作为低压差线性稳压器的输出端以输出电压VO’，第一分压电阻Rd1的第二端连接第二分压电阻Rd2的第一端，第二分压电阻Rd2的第二端接地。As shown in Figure 17, the low dropout linear voltage regulator includes: an error amplifier EA, a drive tube MP, a first voltage dividing resistor Rd1 and a second voltage dividing resistor Rd2. The inverting input end of the error amplifier EA is connected to the voltage generating module 100. The output terminal is connected to the reference voltage VREF, the non-inverting input terminal is connected to the first terminal of the second voltage dividing resistor Rd2 to be connected to the feedback voltage VFB, the output terminal is connected to the gate of the driving tube MP, and the source of the driving tube MP is connected to the power supply voltage VDD. , the drain is connected to the first voltage dividing resistor Rd1 The first end serves as the output end of the low voltage dropout linear regulator to output voltage VO', the second end of the first voltage dividing resistor Rd1 is connected to the first end of the second voltage dividing resistor Rd2, and the second voltage dividing resistor Rd2 The second terminal is connected to ground.
其中，误差放大器EA采用如图18或图19所示的电路结构来实现。实际应用中，为了减弱前级斩波带来的高频时钟毛刺影响，通常需要在输出缓冲器或低压差线性稳压器的输出端外接一个大电容C0进行滤波(如图16和图17所示)。Among them, the error amplifier EA is implemented using the circuit structure shown in Figure 18 or Figure 19. In practical applications, in order to reduce the impact of high-frequency clock glitches caused by pre-stage chopping, it is usually necessary to connect a large capacitor C0 to the output end of the output buffer or low-voltage linear regulator for filtering (as shown in Figure 16 and Figure 17). Show).
然而，增设滤波大电容虽然能够减弱时钟毛刺的影响，却也增加了应用成本，还降低了环路稳定性；因此，提出了针对输出缓冲器或者低压差线性稳压器的电路级补偿方案。However, although adding a large filter capacitor can reduce the impact of clock glitches, it also increases application costs and reduces loop stability; therefore, circuit-level compensation solutions for output buffers or low-dropout linear regulators have been proposed.
针对输出缓冲器结构的电路级补偿方案如图20所示，输出驱动模块500包括：斩波调制单元501、放大解调单元502及陷波滤波单元503；此时，陷波滤波单元503的输出端作为输出驱动模块500的输出端并产生反馈电压VFB。The circuit-level compensation scheme for the output buffer structure is shown in Figure 20. The output driving module 500 includes: a chopper modulation unit 501, an amplification demodulation unit 502 and a notch filter unit 503; at this time, the output of the notch filter unit 503 The terminal serves as the output terminal of the output driving module 500 and generates the feedback voltage VFB.
斩波调制单元501连接电压产生模块100的输出端和陷波滤波单元503的输出端，用于根据斩波频率对基准电压VREF和反馈电压VFB进行斩波调制。The chopper modulation unit 501 is connected to the output end of the voltage generation module 100 and the output end of the notch filter unit 503, and is used to perform chopper modulation on the reference voltage VREF and the feedback voltage VFB according to the chopping frequency.
作为示例，如图21所示，斩波调制单元501包括：第十三斩波开关K13、第十四斩波开关K14、第十五斩波开关K15及第十六斩波开关K16；第十三斩波开关K13的第一端与第十五斩波开关K15的第一端相连并连接电压产生模块100的输出端以接入基准电压VREF，第十四斩波开关K14的第一端与第十六斩波开关K16的第一端相连并连接反馈电压VFB，第十三斩波开关K13的第二端与第十四斩波开关K14的第二端相连并作为斩波调制单元501的第一输出端TP，第十五斩波开关K15的第二端与第十六斩波开关K16的第二端相连并作为斩波调制单元501的第二输出端TN；其中，第十三斩波开关K13和第十六斩波开关K16受控于第一时钟，第十四斩波开关K14和第十五斩波开关K15受控于第二时钟，第一时钟和第二时钟互为一组反相时钟。As an example, as shown in Figure 21, the chopper modulation unit 501 includes: a thirteenth chopper switch K13, a fourteenth chopper switch K14, a fifteenth chopper switch K15, and a sixteenth chopper switch K16; The first end of the three-chopper switch K13 is connected to the first end of the fifteenth chopper switch K15 and connected to the output end of the voltage generation module 100 to access the reference voltage VREF. The first end of the fourteenth chopper switch K14 is connected to the first end of the fourteenth chopper switch K15. The first terminal of the sixteenth chopper switch K16 is connected to the feedback voltage VFB, and the second terminal of the thirteenth chopper switch K13 is connected to the second terminal of the fourteenth chopper switch K14 and serves as the chopper modulation unit 501 The first output terminal TP, the second terminal of the fifteenth chopper switch K15 is connected to the second terminal of the sixteenth chopper switch K16 and serves as the second output terminal TN of the chopper modulation unit 501; wherein, the thirteenth chopper switch K15 The wave switch K13 and the sixteenth chopper switch K16 are controlled by the first clock, the fourteenth chopper switch K14 and the fifteenth chopper switch K15 are controlled by the second clock, and the first clock and the second clock are one of each other. Set of inverted clocks.
本示例中，在第十三斩波开关K13和第十六斩波开关K16受控于第一时钟闭合时，第十四斩波开关K14和第十五斩波开关K15受控于第二时钟断开，等效电路如图22所示，此时，斩波调制单元501的第一输出端TP输出基准电压VREF，第二输出端TN输出反馈电压VFB；在第十三斩波开关K13和第十六斩波开关K16受控于第一时钟断开时，第十四斩波开关K14和第十五斩波开关K15受控于第二时钟闭合，等效电路如图23所示，此时，斩波调制单元501的第一输出端TP输出反馈电压VFB，第二输出端TN输出基准电压VREF。In this example, when the thirteenth chopper switch K13 and the sixteenth chopper switch K16 are controlled by the first clock to close, the fourteenth chopper switch K14 and the fifteenth chopper switch K15 are controlled by the second clock. off, the equivalent circuit is shown in Figure 22. At this time, the first output terminal TP of the chopper modulation unit 501 outputs the reference voltage VREF, and the second output terminal TN outputs the feedback voltage VFB; when the thirteenth chopper switch K13 and When the sixteenth chopper switch K16 is controlled to be turned off by the first clock, the fourteenth chopper switch K14 and the fifteenth chopper switch K15 are controlled to be turned on by the second clock. The equivalent circuit is shown in Figure 23. Here When , the first output terminal TP of the chopper modulation unit 501 outputs the feedback voltage VFB, and the second output terminal TN outputs the reference voltage VREF.
放大解调单元502连接斩波调制单元501的两个输出端TP和TN，用于对经过斩波调制的基准电压和反馈电压进行误差放大后再根据斩波频率进行斩波解调并产生中间电压VM，以及，根据斩波频率对放大解调单元502中的放大器噪声进行斩波调制。 The amplification and demodulation unit 502 is connected to the two output terminals TP and TN of the chopper modulation unit 501, and is used to amplify the error of the chopper-modulated reference voltage and feedback voltage, and then perform chopper demodulation according to the chopper frequency and generate an intermediate voltage VM, and the amplifier noise in the amplification and demodulation unit 502 is chopping modulated according to the chopping frequency.
作为一示例，如图24所示，放大解调单元502包括：第十四MOS管M14、第十五MOS管M15、第十六MOS管M16、第十七MOS管M17、第十八MOS管M18、第十七斩波开关K17、第十八斩波开关K18、第十九斩波开关K19及第二十斩波开关K20；第十四MOS管M14的栅极连接栅控电压Vb，源极连接电源电压VDD，漏极连接第十五MOS管M15的源极和第十六MOS管M16的源极；第十五MOS管M15的栅极和第十六MOS管M16的栅极对应连接斩波调制单元501的两个输出端(如第十五MOS管M15的栅极连接斩波调制单元501的第一输出端TP，第十六MOS管M16的栅极连接斩波调制单元501的第二输出端TN)，第十五MOS管M15的漏极连接第十七MOS管M17的漏极、第十七斩波开关K17的第一端和第十八斩波开关K18的第一端，第十六MOS管M16的漏极连接第十八MOS管M18的漏极、第十九斩波开关K19的第一端和第二十斩波开关K20的第一端；第十七MOS管M17的栅极连接第十八MOS管M18的栅极，第十七MOS管M17的源极和第十八MOS管M18的源极接地；第十七斩波开关K17的第二端连接第十九斩波开关K19的第二端并连接第十七MOS管M17的栅极，第十八斩波开关K18的第二端连接第二十斩波开关K20的第二端并作为放大解调单元502的输出端以输出中间电压VM；其中，第十七斩波开关K17和第二十斩波开关K20受控于第一时钟，第十八斩波开关K18和第十九斩波开关K19受控于第二时钟，第一时钟和第二时钟互为一组反相时钟。As an example, as shown in Figure 24, the amplification and demodulation unit 502 includes: a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, a sixteenth MOS transistor M16, a seventeenth MOS transistor M17, an eighteenth MOS transistor M18, the seventeenth chopper switch K17, the eighteenth chopper switch K18, the nineteenth chopper switch K19 and the twentieth chopper switch K20; the gate of the fourteenth MOS tube M14 is connected to the gate control voltage Vb, the source The pole is connected to the power supply voltage VDD, the drain is connected to the source of the fifteenth MOS transistor M15 and the source of the sixteenth MOS transistor M16; the gate of the fifteenth MOS transistor M15 and the gate of the sixteenth MOS transistor M16 are connected correspondingly. The two output terminals of the chopper modulation unit 501 (for example, the gate of the fifteenth MOS transistor M15 is connected to the first output terminal TP of the chopper modulation unit 501, and the gate of the sixteenth MOS transistor M16 is connected to the chopper modulation unit 501). The second output terminal TN), the drain of the fifteenth MOS transistor M15 is connected to the drain of the seventeenth MOS transistor M17, the first terminal of the seventeenth chopper switch K17 and the first terminal of the eighteenth chopper switch K18 , the drain of the sixteenth MOS tube M16 is connected to the drain of the eighteenth MOS tube M18, the first terminal of the nineteenth chopper switch K19 and the first terminal of the twentieth chopper switch K20; the seventeenth MOS tube The gate of M17 is connected to the gate of the eighteenth MOS transistor M18, the source of the seventeenth MOS transistor M17 and the source of the eighteenth MOS transistor M18 are grounded; the second end of the seventeenth chopper switch K17 is connected to the tenth The second end of the nine-chopper switch K19 is connected to the gate of the seventeenth MOS transistor M17, and the second end of the eighteenth chopper switch K18 is connected to the second end of the twentieth chopper switch K20 and serves as an amplification demodulation unit. The output terminal of 502 outputs the intermediate voltage VM; among them, the seventeenth chopper switch K17 and the twentieth chopper switch K20 are controlled by the first clock, and the eighteenth chopper switch K18 and the nineteenth chopper switch K19 are controlled by the first clock. Controlled by the second clock, the first clock and the second clock are a set of inverted clocks.
本示例中，在第十七斩波开关K17和第二十斩波开关K20受控于第一时钟闭合时，第十八斩波开关K18和第十九斩波开关K19受控于第二时钟断开，等效电路如图25所示；在第十七斩波开关K17和第二十斩波开关K20受控于第一时钟断开时，第十八斩波开关K18和第十九斩波开关K19受控于第二时钟闭合，等效电路如图26所示。第十四MOS管M14至第十八MOS管M18构成误差放大器电路，第十七斩波开关K17至第二十斩波开关K20与前级斩波调制单元501配合使用来完成电压信号的调制和解调，同时，第十七斩波开关K17至第二十斩波开关K20还对误差放大器的放大器噪声进行斩波调制，以将放大器噪声从低频调制至高频。In this example, when the seventeenth chopper switch K17 and the twentieth chopper switch K20 are controlled by the first clock to close, the eighteenth chopper switch K18 and the nineteenth chopper switch K19 are controlled by the second clock. is turned off, the equivalent circuit is shown in Figure 25; when the seventeenth chopper switch K17 and the twentieth chopper switch K20 are controlled by the first clock to turn off, the eighteenth chopper switch K18 and the nineteenth chopper switch K18 are turned off. The wave switch K19 is controlled to close by the second clock, and the equivalent circuit is shown in Figure 26. The fourteenth to eighteenth MOS transistors M14 to M18 constitute an error amplifier circuit, and the seventeenth to twentieth chopper switches K17 to K20 are used in conjunction with the front-stage chopper modulation unit 501 to complete the modulation and synthesis of the voltage signal. Demodulation, at the same time, the seventeenth chopper switch K17 to the twentieth chopper switch K20 also perform chopper modulation on the amplifier noise of the error amplifier to modulate the amplifier noise from low frequency to high frequency.
作为另一示例，如图27所示，放大解调单元502包括：第十四MOS管M14、第十五MOS管M15、第十六MOS管M16、第十七MOS管M17、第十八MOS管M18、第十九MOS管M19、第二十MOS管M20、第二十一MOS管M21、第二十二MOS管M22、第二十三MOS管M23、第二十四MOS管M24、第十七斩波开关K17、第十八斩波开关K18、第十九斩波开关K19、第二十斩波开关K20、第二十一斩波开关K21、第二十二斩波开关K22、第二十三斩波开关K23及第二十四斩波开关K24；第十四MOS管M14的栅极和第十五MOS 管M15的栅极对应连接斩波调制单元501的两个输出端(如第十四MOS管M14的栅极连接斩波调制单元501的第一输出端TP，第十五MOS管M15的栅极连接斩波调制单元501的第二输出端TN)，第十四MOS管M14的源极和第十五MOS管M15的源极连接第十六MOS管M16的漏极，第十四MOS管M14的漏极连接第二十三MOS管M23的漏极，第十五MOS管M15的漏极连接第二十四MOS管M24的漏极；第十六MOS管M16的栅极连接第一栅控电压Vb1，源极连接第十七MOS管M17的源极和第十八MOS管M18的源极并连接电源电压VDD；第十七MOS管M17的栅极连接第十八MOS管M18的栅极并连接第二栅控电压Vb2，第十七MOS管M17的漏极连接第十七斩波开关K17的第一端和第十九斩波开关K19的第一端，第十八MOS管M18的漏极连接第十八斩波开关K18的第一端和第二十斩波开关K20的第一端；第十七斩波开关K17的第二端与第十八斩波开关K18的第二端相连并连接第十九MOS管M19的源极，第十九斩波开关K19的第二端与第二十斩波开关K20的第二端相连并连接第二十MOS管M20的源极；第十九MOS管M19的栅极连接第二十MOS管M20的栅极并连接第三栅控电压Vb3，第十九MOS管M19的漏极连接第二十一MOS管M21的漏极、第二十一斩波开关K21的第一端和第二十二斩波开关K22的第一端，第二十MOS管M20的漏极连接第二十二MOS管M22的漏极、第二十三斩波开关K23的第一端和第二十四斩波开关K24的第一端；第二十一MOS管M21的栅极连接第二十二MOS管M22的栅极并连接第四栅控电压Vb4，第二十一MOS管M21的源极连接第二十三MOS管M23的漏极，第二十二MOS管M22的源极连接第二十四MOS管M24的漏极；第二十三MOS管M23的栅极连接第二十四MOS管M24的栅极，第二十三MOS管M23的源极和第二十四MOS管M24的源极接地；第二十一斩波开关K21的第二端连接第二十三斩波开关K23的第二端并连接第二十三MOS管M23的栅极，第二十二斩波开关K22的第二端连接第二十四斩波开关K24的第二端并作为放大解调单元502的输出端以输出中间电压VM；其中，第十七斩波开关K17、第二十斩波开关K20、第二十一斩波开关K21和第二十四斩波开关K24受控于第一时钟，第十八斩波开关K18、第十九斩波开关K19、第二十二斩波开关K22和第二十三斩波开关K23受控于第二时钟，第一时钟和第二时钟互为一组反相时钟。As another example, as shown in Figure 27, the amplification demodulation unit 502 includes: a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, a sixteenth MOS transistor M16, a seventeenth MOS transistor M17, an eighteenth MOS transistor tube M18, the nineteenth MOS tube M19, the twentieth MOS tube M20, the twenty-first MOS tube M21, the twenty-second MOS tube M22, the twenty-third MOS tube M23, the twenty-fourth MOS tube M24, the Seventeenth chopper switch K17, eighteenth chopper switch K18, nineteenth chopper switch K19, twentieth chopper switch K20, twenty-first chopper switch K21, twenty-second chopper switch K22, The twenty-third chopper switch K23 and the twenty-fourth chopper switch K24; the gate of the fourteenth MOS tube M14 and the fifteenth MOS The gate of the tube M15 is connected to the two output terminals of the chopper modulation unit 501 (for example, the gate of the fourteenth MOS tube M14 is connected to the first output terminal TP of the chopper modulation unit 501, and the gate of the fifteenth MOS tube M15 Connected to the second output terminal TN) of the chopper modulation unit 501, the source of the fourteenth MOS transistor M14 and the source of the fifteenth MOS transistor M15 are connected to the drain of the sixteenth MOS transistor M16, and the source of the fourteenth MOS transistor M14 The drain of the 23rd MOS transistor M23 is connected, the drain of the 15th MOS transistor M15 is connected with the drain of the 24th MOS transistor M24, and the gate of the 16th MOS transistor M16 is connected with the first gate control. Voltage Vb1, the source is connected to the source of the seventeenth MOS transistor M17 and the source of the eighteenth MOS transistor M18 and is connected to the power supply voltage VDD; the gate of the seventeenth MOS transistor M17 is connected to the gate of the eighteenth MOS transistor M18 And connected to the second gate control voltage Vb2, the drain of the seventeenth MOS tube M17 is connected to the first terminal of the seventeenth chopper switch K17 and the first terminal of the nineteenth chopper switch K19, and the drain of the eighteenth MOS tube M18 The drain is connected to the first terminal of the eighteenth chopper switch K18 and the first terminal of the twentieth chopper switch K20; the second terminal of the seventeenth chopper switch K17 and the second terminal of the eighteenth chopper switch K18 Connected and connected to the source of the nineteenth MOS tube M19, the second end of the nineteenth chopper switch K19 is connected to the second end of the twentieth chopper switch K20 and connected to the source of the twentieth MOS tube M20; The gate of the nineteenth MOS transistor M19 is connected to the gate of the twentieth MOS transistor M20 and connected to the third gate control voltage Vb3. The drain of the nineteenth MOS transistor M19 is connected to the drain of the twenty-first MOS transistor M21 and the second gate control voltage Vb3. The first terminal of the eleventh chopper switch K21 and the first terminal of the twenty-second chopper switch K22, and the drain of the twentieth MOS tube M20 are connected to the drain of the twenty-second MOS tube M22 and the twenty-third chopper switch K22. The first end of the wave switch K23 and the first end of the twenty-fourth chopper switch K24; the gate of the twenty-first MOS transistor M21 is connected to the gate of the twenty-second MOS transistor M22 and connected to the fourth gate control voltage Vb4 , the source of the twenty-first MOS tube M21 is connected to the drain of the twenty-third MOS tube M23, the source of the twenty-second MOS tube M22 is connected to the drain of the twenty-fourth MOS tube M24; the twenty-third MOS The gate of the tube M23 is connected to the gate of the twenty-fourth MOS tube M24, the source of the twenty-third MOS tube M23 and the source of the twenty-fourth MOS tube M24 are grounded; the twenty-first chopper switch K21 The two terminals are connected to the second terminal of the twenty-third chopper switch K23 and connected to the gate of the twenty-third MOS tube M23, and the second terminal of the twenty-second chopper switch K22 is connected to the twenty-fourth chopper switch K24. The second terminal serves as the output terminal of the amplification and demodulation unit 502 to output the intermediate voltage VM; among them, the seventeenth chopper switch K17, the twentieth chopper switch K20, the twenty-first chopper switch K21 and the twenty-fourth chopper switch K20. The chopper switch K24 is controlled by the first clock, and the eighteenth chopper switch K18, the nineteenth chopper switch K19, the twenty-second chopper switch K22 and the twenty-third chopper switch K23 are controlled by the second clock. , the first clock and the second clock are a set of inverted clocks.
本示例中，在第十七斩波开关K17、第二十斩波开关K20、第二十一斩波开关K21和第二十四斩波开关K24受控于第一时钟闭合时，第十八斩波开关K18、第十九斩波开关K19、第二十二斩波开关K22和第二十三斩波开关K23受控于第二时钟断开，等效电路如图28所示；在第十七斩波开关K17、第二十斩波开关K20、第二十一斩波开关K21和第二十四斩波开关K24受控于第一时钟断开时，第十八斩波开关K18、第十九斩波开关K19、第二十二斩 波开关K22和第二十三斩波开关K23受控于第二时钟闭合，等效电路如图29所示。第十四MOS管M14至第二十四MOS管M24构成误差放大器电路，第十七斩波开关K17至第二十四斩波开关K24与前级斩波调制单元501配合使用来完成电压信号的调制和解调，同时，第十七斩波开关K17至第二十四斩波开关K24还对误差放大器的放大器噪声进行斩波调制，以将放大器噪声从低频调制至高频。In this example, when the seventeenth chopper switch K17, the twentieth chopper switch K20, the twenty-first chopper switch K21 and the twenty-fourth chopper switch K24 are controlled by the first clock to close, the eighteenth The chopper switch K18, the nineteenth chopper switch K19, the twenty-second chopper switch K22 and the twenty-third chopper switch K23 are controlled to be turned off by the second clock. The equivalent circuit is shown in Figure 28; in the When the seventeenth chopper switch K17, the twentieth chopper switch K20, the twenty-first chopper switch K21 and the twenty-fourth chopper switch K24 are controlled by the first clock being turned off, the eighteenth chopper switch K18, The nineteenth chopper switch K19, the twenty-second chopper switch The wave switch K22 and the twenty-third chopper switch K23 are controlled to be closed by the second clock, and the equivalent circuit is shown in Figure 29. The fourteenth to twenty-fourth MOS transistors M14 to M24 constitute an error amplifier circuit, and the seventeenth to twenty-fourth chopper switches K17 to K24 are used in conjunction with the front-stage chopper modulation unit 501 to complete the voltage signal. Modulation and demodulation, at the same time, the seventeenth chopper switch K17 to the twenty-fourth chopper switch K24 also perform chopper modulation on the amplifier noise of the error amplifier to modulate the amplifier noise from low frequency to high frequency.
陷波滤波单元503连接放大解调单元502的输出端，用于在斩波频率点对放大器噪声进行陷波处理，以此减弱中间电压VM上的时钟毛刺。The notch filter unit 503 is connected to the output end of the amplification and demodulation unit 502, and is used to perform notch processing on the amplifier noise at the chopping frequency point, thereby reducing the clock glitch on the intermediate voltage VM.
作为示例，如图30所示，陷波滤波单元503包括：第六电阻R6、第七电阻R7、第八电阻R8、第四电容C4、第五电容C5及第六电容C6；第六电阻R6的第一端连接第四电容C4的第一端并连接放大解调单元502的输出端以接入中间电压VM，第二端连接第七电阻R7的第一端和第五电容C5的第一端；第四电容C4的第二端连接第六电容C6的第一端和第八电阻R8的第一端；第七电阻R7的第二端连接第六电容C6的第二端并作为陷波滤波单元503的输出端以输出电压VO；第五电容C5的第二端接地；第八电阻R8的第二端接地；其中，第六电阻R6、第七电阻R7和第八电阻R8采用开关电容电路实现，该开关电容电路中开关的控制时钟与斩波时钟(即第一时钟)除频相移45°。As an example, as shown in Figure 30, the notch filter unit 503 includes: a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a fourth capacitor C4, a fifth capacitor C5 and a sixth capacitor C6; the sixth resistor R6 The first end is connected to the first end of the fourth capacitor C4 and the output end of the amplification and demodulation unit 502 to access the intermediate voltage VM, and the second end is connected to the first end of the seventh resistor R7 and the first end of the fifth capacitor C5 terminal; the second terminal of the fourth capacitor C4 is connected to the first terminal of the sixth capacitor C6 and the first terminal of the eighth resistor R8; the second terminal of the seventh resistor R7 is connected to the second terminal of the sixth capacitor C6 and serves as a trap The output terminal of the filtering unit 503 outputs the voltage VO; the second terminal of the fifth capacitor C5 is connected to the ground; the second terminal of the eighth resistor R8 is connected to the ground; among which, the sixth resistor R6, the seventh resistor R7 and the eighth resistor R8 adopt switched capacitors. Circuit implementation: the control clock of the switch in the switched capacitor circuit and the chopper clock (i.e. the first clock) are frequency-divided and phase-shifted by 45°.
具体的，开关电容电路包括电容C01、电容C02、开关K01和开关K02，其中，开关K01受控于控制时钟，开关K02受控于控制时钟的反相信号(如图13所示)；其等效电阻为1/FC，F为控制时钟的频率，C为电容C01的容值。实际应用中，可设第六电阻R6和第七电阻R7的阻值相等，且为第八电阻R8的2倍；第四电容C4和第六电容C6的容值相等，且为第五电容C5的1/2。Specifically, the switched capacitor circuit includes capacitor C01, capacitor C02, switch K01 and switch K02, where switch K01 is controlled by the control clock and switch K02 is controlled by the inverted signal of the control clock (as shown in Figure 13); etc. The effective resistance is 1/FC, F is the frequency of the control clock, and C is the capacitance value of capacitor C01. In practical applications, it can be assumed that the resistance values of the sixth resistor R6 and the seventh resistor R7 are equal and are twice the value of the eighth resistor R8; the capacitance values of the fourth capacitor C4 and the sixth capacitor C6 are equal and are equal to the fifth capacitor C5. 1/2.
更具体的，开关电容电路中的开关(如开关K01和开关K02)采用NMOS管实现，其中，NMOS管的衬底中包括一个DPWDN(P阱/深N阱)隔离二极管及一个DDNPWPSUB(深P阱/深N阱)隔离二极管(如图14所示)。在NMOS管的衬底中增设DPWDN隔离二极管(如D1)和DDNPWPSUB隔离二极管(如D2)，避免了传统NMOS开关器件存在时钟馈通、沟道电荷注入、噪声串扰等影响，可优化开关特性，从而优化噪声性能。需要说明的是，如上NMOS管的制备可采用常规半导体工艺实现，本实施例对此不做限制。More specifically, the switches in the switched capacitor circuit (such as switch K01 and switch K02) are implemented using NMOS tubes. The substrate of the NMOS tube includes a DPWDN (P-well/deep N-well) isolation diode and a DDNPWPSUB (deep P-well) well/deep N-well) isolation diode (shown in Figure 14). Adding DPWDN isolation diodes (such as D1) and DDNPWPSUB isolation diodes (such as D2) to the substrate of the NMOS tube avoids the effects of clock feedthrough, channel charge injection, noise crosstalk and other effects of traditional NMOS switching devices, and can optimize switching characteristics. thereby optimizing noise performance. It should be noted that the above-mentioned preparation of the NMOS transistor can be implemented using conventional semiconductor processes, and this embodiment is not limited to this.
本示例中，陷波滤波单元503采用同步积分的陷波滤波器实现，该同步积分的陷波滤波器采用和前级放大解调单元502中斩波时钟除频相移45°的时钟信号作为开关电容电路中开关的控制时钟，通过在一个时钟周期对因放大器噪声所引起的时钟毛刺正反两部分进行积分，可有效降低时钟毛刺问题，也即，有效抑制放大器噪声的影响，从而提升基准电压的噪声特 性(如图15所示)；而采用与前级斩波时钟相关的时钟作为控制时钟，避免了采用不相关时钟所引起的时钟混叠问题，及由此导致的将滤波器采样时钟处较大的噪声折回至低频，从而严重降低前级斩波调制的效果。In this example, the notch filter unit 503 is implemented using a synchronous integration notch filter. The synchronous integration notch filter uses a clock signal that is 45° divided and phase-shifted from the chopping clock in the preamplification and demodulation unit 502. The control clock of the switch in the switched capacitor circuit can effectively reduce the clock glitch problem by integrating the positive and negative parts of the clock glitch caused by the amplifier noise in one clock cycle, that is, effectively suppressing the influence of the amplifier noise, thereby improving the benchmark Voltage noise characteristics (as shown in Figure 15); and using a clock related to the pre-stage chopping clock as the control clock avoids the clock aliasing problem caused by using irrelevant clocks, and the resulting filter sampling clock at a relatively high position. Large noise folds back to low frequencies, thereby seriously reducing the effect of the pre-stage chopper modulation.
针对低压差线性稳压器结构的电路级补偿方案如图31所示，输出驱动模块500除包括：斩波调制单元501、放大解调单元502及陷波滤波单元503外，还包括：驱动管MP、第一分压电阻Rd1及第二分压电阻Rd2，驱动管MP的栅极连接陷波滤波单元503的输出端，源极连接电源电压VDD，漏极连接第一分压电阻Rd1的第一端并作为输出驱动模块500的输出端，第一分压电阻Rd的第二端连接第二分压电阻Rd的第一端并产生反馈电压VFB，第二分压电阻Rd2的第二端接地。由于斩波调制单元501、放大解调单元502和陷波滤波单元503与输出缓冲器结构的电路级补偿方案相同，此处不再赘述，相关内容可参见上文。The circuit-level compensation scheme for the low-dropout linear regulator structure is shown in Figure 31. In addition to the chopper modulation unit 501, the amplification demodulation unit 502 and the notch filter unit 503, the output driver module 500 also includes: a driver tube. MP, the first voltage dividing resistor Rd1 and the second voltage dividing resistor Rd2. The gate of the driving tube MP is connected to the output end of the notch filter unit 503, the source is connected to the power supply voltage VDD, and the drain is connected to the third voltage dividing resistor Rd1. One end serves as the output end of the output driver module 500, the second end of the first voltage dividing resistor Rd is connected to the first end of the second voltage dividing resistor Rd and generates the feedback voltage VFB, and the second end of the second voltage dividing resistor Rd2 is connected to ground. . Since the chopper modulation unit 501, the amplification demodulation unit 502 and the notch filter unit 503 are the same as the circuit-level compensation scheme of the output buffer structure, they will not be described in detail here. The relevant content can be found above.
另外，针对低压差线性稳压器结构的电路级补偿方案，将该同步积分的陷波滤波器设于驱动管MP之前，可以大幅抑制加到驱动管MP上的电压波动，有效改善输出端的时钟抖动问题。In addition, for the circuit-level compensation scheme of the low-dropout linear regulator structure, the synchronous integration notch filter is placed before the drive tube MP, which can greatly suppress the voltage fluctuation added to the drive tube MP and effectively improve the clock at the output end. Jitter problem.
综上所述，本发明的一种基准电路，通过斩波调制模块、放大解调模块、陷波滤波模块和输出驱动模块的设计，可有效抑制放大器噪声对基准电压的影响，从而提升基准电压的噪声特性；而且，各模块可采用极小的片内电路实现，占用面积小，且系统环路稳定性好。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。To sum up, the reference circuit of the present invention can effectively suppress the impact of amplifier noise on the reference voltage through the design of the chopper modulation module, amplification demodulation module, notch filter module and output driver module, thereby improving the reference voltage. noise characteristics; moreover, each module can be implemented with extremely small on-chip circuits, occupying a small area and having good system loop stability. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。 The above embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims (12)

  1. 一种基准电路，其特征在于，所述基准电路包括：A reference circuit, characterized in that the reference circuit includes:
    电压产生模块，用于根据正温度系数电压和负温度系数电压产生基准电压并输出，以及，根据偏置电压调控所述正温度系数电压和所述负温度系数电压；a voltage generation module, configured to generate and output a reference voltage according to the positive temperature coefficient voltage and the negative temperature coefficient voltage, and to regulate the positive temperature coefficient voltage and the negative temperature coefficient voltage according to the bias voltage;
    斩波调制模块，连接所述电压产生模块的正电压端和负电压端，用于根据斩波频率对所述正温度系数电压和所述负温度系数电压进行斩波调制；A chopper modulation module, connected to the positive voltage terminal and the negative voltage terminal of the voltage generation module, for performing chopper modulation on the positive temperature coefficient voltage and the negative temperature coefficient voltage according to the chopping frequency;
    放大解调模块，连接所述斩波调制模块的两个输出端，用于对经过斩波调制的正温度系数电压和负温度系数电压进行运放处理后再根据斩波频率进行斩波解调并产生所述偏置电压，以及，根据斩波频率对所述放大解调模块中的放大器噪声进行斩波调制；The amplification and demodulation module is connected to the two output terminals of the chopper modulation module, and is used to perform operational amplifier processing on the chopper-modulated positive temperature coefficient voltage and negative temperature coefficient voltage, and then perform chopper demodulation according to the chopping frequency. And generate the bias voltage, and perform chopping modulation on the amplifier noise in the amplification and demodulation module according to the chopping frequency;
    陷波滤波模块，连接所述放大解调模块的输出端，用于在斩波频率点对所述放大器噪声进行陷波处理。The notch filter module is connected to the output end of the amplification and demodulation module, and is used to perform notch processing on the amplifier noise at the chopping frequency point.
  2. 根据权利要求1所述的基准电路，其特征在于，所述电压产生模块包括：第一MOS管、第二MOS管、第一电阻、第二电阻、第一三极管及第二三极管；所述第一MOS管的栅极和所述第二MOS管的栅极连接偏置电压，所述第一MOS管的源极和所述第二MOS管的源极连接电源电压，所述第一MOS管的漏极连接所述第一电阻的第一端并作为所述电压产生模块的正电压端，所述第二MOS管的漏极连接所述第二电阻的第一端并作为所述电压产生模块的输出端；所述第一电阻的第二端连接所述第一三极管的发射极；所述第二电阻的第二端连接所述第二三极管的发射极并作为所述电压产生模块的负电压端；所述第一三极管的基极与其集电极相连并接地；所述第二三极管的基极与其集电极相连并接地。The reference circuit according to claim 1, characterized in that the voltage generation module includes: a first MOS tube, a second MOS tube, a first resistor, a second resistor, a first transistor and a second transistor. ; The gate of the first MOS tube and the gate of the second MOS tube are connected to the bias voltage, and the source of the first MOS tube and the source of the second MOS tube are connected to the power supply voltage, and the The drain of the first MOS transistor is connected to the first end of the first resistor and serves as the positive voltage end of the voltage generating module. The drain of the second MOS transistor is connected to the first end of the second resistor and serves as the positive voltage end of the voltage generating module. The output end of the voltage generation module; the second end of the first resistor is connected to the emitter of the first triode; the second end of the second resistor is connected to the emitter of the second triode And as the negative voltage terminal of the voltage generating module; the base of the first triode is connected to its collector and grounded; the base of the second triode is connected to its collector and grounded.
  3. 根据权利要求1所述的基准电路，其特征在于，所述斩波调制模块包括：第一斩波开关、第二斩波开关、第三斩波开关及第四斩波开关；所述第一斩波开关的第一端与所述第三斩波开关的第一端相连并连接所述电压产生模块的正电压端，所述第二斩波开关的第一端与所述第四斩波开关的第一端相连并连接所述电压产生模块的负电压端，所述第一斩波开关的第二端与所述第二斩波开关的第二端相连并作为所述斩波调制模块的第一输出端，所述第三斩波开关的第二端与所述第四斩波开关的第二端相连并作为所述斩波调制模块的第二输出端；其中，所述第一斩波开关和所述第四斩波开关受控于第一时钟，所述第二斩波开关和所述第三斩波开关受控于第二时钟，所述第一时钟和所述第二时钟互为一组反相时钟。The reference circuit according to claim 1, wherein the chopper modulation module includes: a first chopper switch, a second chopper switch, a third chopper switch and a fourth chopper switch; the first chopper switch The first end of the chopper switch is connected to the first end of the third chopper switch and the positive voltage end of the voltage generating module, and the first end of the second chopper switch is connected to the fourth chopper switch. The first end of the switch is connected to the negative voltage end of the voltage generating module, and the second end of the first chopper switch is connected to the second end of the second chopper switch and serves as the chopper modulation module. The first output end of the third chopper switch is connected to the second end of the fourth chopper switch and serves as the second output end of the chopper modulation module; wherein, the first The chopper switch and the fourth chopper switch are controlled by a first clock, the second chopper switch and the third chopper switch are controlled by a second clock, the first clock and the second The clocks are a set of inverted clocks.
  4. 根据权利要求1所述的基准电路，其特征在于，所述放大解调模块包括：第三MOS管、 第四MOS管、第五MOS管、第六MOS管、第七MOS管、第五斩波开关、第六斩波开关、第七斩波开关及第八斩波开关；所述第三MOS管的栅极连接栅控电压，源极连接电源电压，漏极连接所述第四MOS管的源极和所述第五MOS管的源极；所述第四MOS管的栅极和所述第五MOS管的栅极对应连接所述斩波调制模块的两个输出端，所述第四MOS管的漏极连接所述第六MOS管的漏极、所述第五斩波开关的第一端和所述第六斩波开关的第一端，所述第五MOS管的漏极连接所述第七MOS管的漏极、所述第七斩波开关的第一端和所述第八斩波开关的第一端；所述第六MOS管的栅极连接所述第七MOS管的栅极，所述第六MOS管的源极和所述第七MOS管的源极接地；所述第五斩波开关的第二端连接所述第七斩波开关的第二端并连接所述第六MOS管的栅极，所述第六斩波开关的第二端连接所述第八斩波开关的第二端并作为所述放大解调模块的输出端；其中，所述第五斩波开关和所述第八斩波开关受控于第一时钟，所述第六斩波开关和所述第七斩波开关受控于第二时钟，所述第一时钟和所述第二时钟互为一组反相时钟；The reference circuit according to claim 1, characterized in that the amplification and demodulation module includes: a third MOS transistor, The fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the fifth chopper switch, the sixth chopper switch, the seventh chopper switch and the eighth chopper switch; the third MOS tube The gate is connected to the gate control voltage, the source is connected to the power supply voltage, and the drain is connected to the source of the fourth MOS tube and the source of the fifth MOS tube; the gate of the fourth MOS tube and the source of the fifth MOS tube are connected. The gates of the five MOS tubes are connected to the two output terminals of the chopper modulation module, and the drain of the fourth MOS tube is connected to the drain of the sixth MOS tube and the first terminal of the fifth chopper switch. terminal and the first terminal of the sixth chopper switch, the drain of the fifth MOS tube is connected to the drain of the seventh MOS tube, the first terminal of the seventh chopper switch and the eighth The first end of the chopper switch; the gate of the sixth MOS tube is connected to the gate of the seventh MOS tube, and the source of the sixth MOS tube and the source of the seventh MOS tube are grounded; The second end of the fifth chopper switch is connected to the second end of the seventh chopper switch and connected to the gate of the sixth MOS transistor, and the second end of the sixth chopper switch is connected to the eighth The second end of the chopper switch serves as the output end of the amplification and demodulation module; wherein the fifth chopper switch and the eighth chopper switch are controlled by the first clock, and the sixth chopper switch and the seventh chopper switch is controlled by a second clock, the first clock and the second clock being a set of inverted clocks;
    或者，所述放大解调模块包括：第三MOS管、第四MOS管、第五MOS管、第六MOS管、第七MOS管、第八MOS管、第九MOS管、第十MOS管、第十一MOS管、第十二MOS管、第十三MOS管、第五斩波开关、第六斩波开关、第七斩波开关、第八斩波开关、第九斩波开关、第十斩波开关、第十一斩波开关及第十二斩波开关；所述第三MOS管的栅极和所述第四MOS管的栅极对应连接所述斩波调制模块的两个输出端，所述第三MOS管的源极和所述第四MOS管的源极连接所述第五MOS管的漏极，所述第三MOS管的漏极连接所述第十二MOS管的漏极，所述第四MOS管的漏极连接所述第十三MOS管的漏极；所述第五MOS管的栅极连接第一栅控电压，源极连接所述第六MOS管的源极和所述第七MOS管的源极并连接电源电压；所述第六MOS管的栅极连接所述第七MOS管的栅极并连接第二栅控电压，所述第六MOS管的漏极连接所述第五斩波开关的第一端和所述第七斩波开关的第一端，所述第七MOS管的漏极连接所述第六斩波开关的第一端和所述第八斩波开关的第一端；所述第五斩波开关的第二端与所述第六斩波开关的第二端相连并连接所述第八MOS管的源极，所述第七斩波开关的第二端与所述第八斩波开关的第二端相连并连接所述第九MOS管的源极；所述第八MOS管的栅极连接所述第九MOS管的栅极并连接第三栅控电压，所述第八MOS管的漏极连接所述第十MOS管的漏极、所述第九斩波开关的第一端和所述第十斩波开关的第一端，所述第九MOS管的漏极连接所述第十一MOS管的漏极、所述第十一斩波开关的第一端和所述第十二斩波开关的第一端；所述第十MOS管的栅极连接所述第十一MOS管的栅极并连接第四栅控电 压，所述第十MOS管的源极连接所述第十二MOS管的漏极，所述第十一MOS管的源极连接所述第十三MOS管的漏极；所述第十二MOS管的栅极连接所述第十三MOS管的栅极，所述第十二MOS管的源极和所述第十三MOS管的源极接地；所述第九斩波开关的第二端连接所述第十一斩波开关的第二端并连接所述第十二MOS管的栅极，所述第十斩波开关的第二端连接所述第十二斩波开关的第二端并作为所述放大解调模块的输出端；其中，所述第五斩波开关、所述第八斩波开关、所述第九斩波开关、所述第十二斩波开关受控于第一时钟，所述第六斩波开关、所述第七斩波开关、所述第十斩波开关、所述第十一斩波开关受控于第二时钟，所述第一时钟和所述第二时钟互为一组反相时钟。Alternatively, the amplification and demodulation module includes: a third MOS tube, a fourth MOS tube, a fifth MOS tube, a sixth MOS tube, a seventh MOS tube, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, The eleventh MOS tube, the twelfth MOS tube, the thirteenth MOS tube, the fifth chopper switch, the sixth chopper switch, the seventh chopper switch, the eighth chopper switch, the ninth chopper switch, the tenth A chopper switch, an eleventh chopper switch and a twelfth chopper switch; the gate of the third MOS transistor and the gate of the fourth MOS transistor are respectively connected to the two output terminals of the chopper modulation module. , the source of the third MOS transistor and the source of the fourth MOS transistor are connected to the drain of the fifth MOS transistor, and the drain of the third MOS transistor is connected to the drain of the twelfth MOS transistor. The drain of the fourth MOS tube is connected to the drain of the thirteenth MOS tube; the gate of the fifth MOS tube is connected to the first gate control voltage, and the source is connected to the source of the sixth MOS tube. The gate of the sixth MOS transistor is connected to the gate of the seventh MOS transistor and connected to the second gate control voltage, and the gate of the sixth MOS transistor is connected to the source of the seventh MOS transistor. The drain is connected to the first end of the fifth chopper switch and the first end of the seventh chopper switch, and the drain of the seventh MOS transistor is connected to the first end of the sixth chopper switch and the first end of the seventh chopper switch. The first end of the eighth chopper switch; the second end of the fifth chopper switch is connected to the second end of the sixth chopper switch and connected to the source of the eighth MOS tube, and the second end of the fifth chopper switch is connected to the source of the eighth MOS transistor. The second end of the seventh chopper switch is connected to the second end of the eighth chopper switch and connected to the source of the ninth MOS transistor; the gate of the eighth MOS transistor is connected to the gate of the ninth MOS transistor. The gate is also connected to the third gate control voltage, and the drain of the eighth MOS transistor is connected to the drain of the tenth MOS transistor, the first end of the ninth chopper switch and the tenth chopper switch. The first end, the drain of the ninth MOS transistor is connected to the drain of the eleventh MOS transistor, the first end of the eleventh chopper switch and the first end of the twelfth chopper switch. ;The gate of the tenth MOS transistor is connected to the gate of the eleventh MOS transistor and connected to the fourth gate control circuit. voltage, the source of the tenth MOS tube is connected to the drain of the twelfth MOS tube, the source of the eleventh MOS tube is connected to the drain of the thirteenth MOS tube; the twelfth MOS tube The gate of the MOS tube is connected to the gate of the thirteenth MOS tube, the source of the twelfth MOS tube and the source of the thirteenth MOS tube are grounded; the second terminal of the ninth chopper switch The second terminal of the eleventh chopper switch is connected to the gate of the twelfth MOS transistor, and the second terminal of the tenth chopper switch is connected to the second terminal of the twelfth chopper switch. terminal and serves as the output terminal of the amplification and demodulation module; wherein, the fifth chopper switch, the eighth chopper switch, the ninth chopper switch, and the twelfth chopper switch are controlled by A first clock, the sixth chopper switch, the seventh chopper switch, the tenth chopper switch, the eleventh chopper switch are controlled by a second clock, the first clock and the The second clocks are a set of inverted clocks.
  5. 根据权利要求1所述的基准电路，其特征在于，所述陷波滤波模块包括：第三电阻、第四电阻、第五电阻、第一电容、第二电容及第三电容；所述第三电阻的第一端连接所述第一电容的第一端并连接所述放大解调模块的输出端，第二端连接所述第四电阻的第一端和所述第二电容的第一端；所述第一电容的第二端连接所述第三电容的第一端和所述第五电阻的第一端；所述第四电阻的第二端连接所述第三电容的第二端并作为所述陷波滤波模块的输出端；所述第二电容的第二端接地；所述第五电阻的第二端接地；其中，所述第三电阻、所述第四电阻和所述第五电阻采用开关电容电路实现，所述开关电容电路中开关的控制时钟与斩波时钟除频相移45°。The reference circuit according to claim 1, characterized in that the notch filter module includes: a third resistor, a fourth resistor, a fifth resistor, a first capacitor, a second capacitor and a third capacitor; the third The first end of the resistor is connected to the first end of the first capacitor and the output end of the amplification and demodulation module, and the second end is connected to the first end of the fourth resistor and the first end of the second capacitor. ; The second end of the first capacitor is connected to the first end of the third capacitor and the first end of the fifth resistor; the second end of the fourth resistor is connected to the second end of the third capacitor and serves as the output end of the notch filter module; the second end of the second capacitor is grounded; the second end of the fifth resistor is grounded; wherein, the third resistor, the fourth resistor and the The fifth resistor is implemented using a switched capacitor circuit. In the switched capacitor circuit, the control clock of the switch and the chopping clock are frequency-divided and phase-shifted by 45°.
  6. 根据权利要求1-5任一项所述的基准电路，其特征在于，所述基准电路还包括：输出驱动模块，连接所述电压产生模块的输出端，用于增强所述基准电压的负载驱动能力。The reference circuit according to any one of claims 1 to 5, characterized in that the reference circuit further includes: an output drive module connected to the output end of the voltage generation module for enhancing the load drive of the reference voltage. ability.
  7. 根据权利要求6所述的基准电路，其特征在于，所述输出驱动模块包括：The reference circuit according to claim 6, characterized in that the output driving module includes:
    斩波调制单元，连接所述电压产生模块的输出端，用于根据斩波频率对所述基准电压和反馈电压进行斩波调制；A chopper modulation unit, connected to the output end of the voltage generation module, used to perform chopper modulation on the reference voltage and feedback voltage according to the chopping frequency;
    放大解调单元，连接所述斩波调制单元的两个输出端，用于对经过斩波调制的基准电压和反馈电压进行误差放大后再根据斩波频率进行斩波解调并产生中间电压，以及，根据斩波频率对所述放大解调单元中的放大器噪声进行斩波调制；An amplification and demodulation unit is connected to the two output terminals of the chopper modulation unit, and is used to amplify the error of the chopper-modulated reference voltage and feedback voltage, and then perform chopper demodulation according to the chopper frequency and generate an intermediate voltage, And, perform chopping modulation on the amplifier noise in the amplification and demodulation unit according to the chopping frequency;
    陷波滤波单元，连接所述放大解调单元的输出端，用于在斩波频率点对所述放大器噪声进行陷波处理。The notch filter unit is connected to the output end of the amplification and demodulation unit, and is used to perform notch processing on the amplifier noise at the chopping frequency point.
  8. 根据权利要求7所述的基准电路，其特征在于，在所述输出驱动模块采用输出缓冲器结构 时，所述陷波滤波单元的输出端作为所述输出驱动模块的输出端并产生所述反馈电压；The reference circuit according to claim 7, characterized in that the output driver module adopts an output buffer structure. When, the output end of the notch filter unit serves as the output end of the output driving module and generates the feedback voltage;
    在所述输出驱动模块采用低压差线性稳压器结构时，所述输出驱动模块还包括：驱动管、第一分压电阻及第二分压电阻，所述驱动管的栅极连接所述陷波滤波单元的输出端，源极连接电源电压，漏极连接所述第一分压电阻的第一端并作为所述输出驱动模块的输出端，所述第一分压电阻的第二端连接所述第二分压电阻的第一端并产生所述反馈电压，所述第二分压电阻的第二端接地。When the output driving module adopts a low voltage dropout linear regulator structure, the output driving module further includes: a driving tube, a first voltage dividing resistor and a second voltage dividing resistor. The gate of the driving tube is connected to the trap. The output end of the wave filter unit, the source is connected to the power supply voltage, the drain is connected to the first end of the first voltage dividing resistor and serves as the output end of the output driving module, and the second end of the first voltage dividing resistor is connected to The first end of the second voltage dividing resistor generates the feedback voltage, and the second end of the second voltage dividing resistor is connected to ground.
  9. 根据权利要求7所述的基准电路，其特征在于，所述斩波调制单元包括：第十三斩波开关、第十四斩波开关、第十五斩波开关及第十六斩波开关；所述第十三斩波开关的第一端与所述第十五斩波开关的第一端相连并连接所述电压产生模块的输出端，所述第十四斩波开关的第一端与所述第十六斩波开关的第一端相连并连接所述反馈电压，所述第十三斩波开关的第二端与所述第十四斩波开关的第二端相连并作为所述斩波调制单元的第一输出端，所述第十五斩波开关的第二端与所述第十六斩波开关的第二端相连并作为所述斩波调制单元的第二输出端；其中，所述第十三斩波开关和所述第十六斩波开关受控于第一时钟，所述第十四斩波开关和所述第十五斩波开关受控于第二时钟，所述第一时钟和所述第二时钟互为一组反相时钟。。The reference circuit according to claim 7, wherein the chopper modulation unit includes: a thirteenth chopper switch, a fourteenth chopper switch, a fifteenth chopper switch and a sixteenth chopper switch; The first end of the thirteenth chopper switch is connected to the first end of the fifteenth chopper switch and the output end of the voltage generating module, and the first end of the fourteenth chopper switch is connected to the first end of the fifteenth chopper switch. The first end of the sixteenth chopper switch is connected to the feedback voltage, and the second end of the thirteenth chopper switch is connected to the second end of the fourteenth chopper switch and serves as the The first output end of the chopper modulation unit, the second end of the fifteenth chopper switch is connected to the second end of the sixteenth chopper switch and serves as the second output end of the chopper modulation unit; Wherein, the thirteenth chopper switch and the sixteenth chopper switch are controlled by a first clock, and the fourteenth chopper switch and the fifteenth chopper switch are controlled by a second clock, The first clock and the second clock are a set of inverted clocks. .
  10. 根据权利要求7所述的基准电路，其特征在于，所述放大解调单元包括：第十四MOS管、第十五MOS管、第十六MOS管、第十七MOS管、第十八MOS管、第十七斩波开关、第十八斩波开关、第十九斩波开关及第二十斩波开关；所述第十四MOS管的栅极连接栅控电压，源极连接电源电压，漏极连接所述第十五MOS管的源极和所述第十六MOS管的源极；所述第十五MOS管的栅极和所述第十六MOS管的栅极对应连接所述斩波调制单元的两个输出端，所述第十五MOS管的漏极连接所述第十七MOS管的漏极、所述第十七斩波开关的第一端和所述第十八斩波开关的第一端，所述第十六MOS管的漏极连接所述第十八MOS管的漏极、所述第十九斩波开关的第一端和所述第二十斩波开关的第一端；所述第十七MOS管的栅极连接所述第十八MOS管的栅极，所述第十七MOS管的源极和所述第十八MOS管的源极接地；所述第十七斩波开关的第二端连接所述第十九斩波开关的第二端并连接所述第十七MOS管的栅极，所述第十八斩波开关的第二端连接所述第二十斩波开关的第二端并作为所述放大解调单元的输出端；其中，所述第十七斩波开关和所述第二十斩波开关受控于第一时钟，所述第十八斩波开关和所述第十九斩波开关受控于第二时钟，所述第一时钟和所述第二时钟互为一组反相时钟。 The reference circuit according to claim 7, characterized in that the amplification and demodulation unit includes: a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube tube, the seventeenth chopper switch, the eighteenth chopper switch, the nineteenth chopper switch and the twentieth chopper switch; the gate of the fourteenth MOS tube is connected to the gate control voltage, and the source is connected to the power supply voltage , the drain is connected to the source of the fifteenth MOS transistor and the source of the sixteenth MOS transistor; the gate of the fifteenth MOS transistor and the gate of the sixteenth MOS transistor are connected correspondingly. The two output terminals of the chopper modulation unit, the drain of the fifteenth MOS tube is connected to the drain of the seventeenth MOS tube, the first end of the seventeenth chopper switch and the tenth The first end of the eight-chopper switch, the drain of the sixteenth MOS transistor is connected to the drain of the eighteenth MOS transistor, the first end of the nineteenth chopper switch and the twentieth chopper switch. The first end of the wave switch; the gate of the seventeenth MOS tube is connected to the gate of the eighteenth MOS tube, the source of the seventeenth MOS tube and the source of the eighteenth MOS tube Grounded; the second terminal of the seventeenth chopper switch is connected to the second terminal of the nineteenth chopper switch and connected to the gate of the seventeenth MOS tube, and the second terminal of the eighteenth chopper switch is connected to the ground. Two terminals are connected to the second terminal of the twentieth chopper switch and serve as the output terminal of the amplification and demodulation unit; wherein the seventeenth chopper switch and the twentieth chopper switch are controlled by the A clock, the eighteenth chopper switch and the nineteenth chopper switch are controlled by a second clock, and the first clock and the second clock are a set of inverted clocks.
    或者，所述放大解调单元包括：第十四MOS管、第十五MOS管、第十六MOS管、第十七MOS管、第十八MOS管、第十九MOS管、第二十MOS管、第二十一MOS管、第二十二MOS管、第二十三MOS管、第二十四MOS管、第十七斩波开关、第十八斩波开关、第十九斩波开关、第二十斩波开关、第二十一斩波开关、第二十二斩波开关、第二十三斩波开关及第二十四斩波开关；所述第十四MOS管的栅极和所述第十五MOS管的栅极对应连接所述斩波调制单元的两个输出端，所述第十四MOS管的源极和所述第十五MOS管的源极连接所述第十六MOS管的漏极，所述第十四MOS管的漏极连接所述第二十三MOS管的漏极，所述第十五MOS管的漏极连接所述第二十四MOS管的漏极；所述第十六MOS管的栅极连接第一栅控电压，源极连接所述第十七MOS管的源极和所述第十八MOS管的源极并连接电源电压；所述第十七MOS管的栅极连接所述第十八MOS管的栅极并连接第二栅控电压，所述第十七MOS管的漏极连接所述第十七斩波开关的第一端和所述第十九斩波开关的第一端，所述第十八MOS管的漏极连接所述第十八斩波开关的第一端和所述第二十斩波开关的第一端；所述第十七斩波开关的第二端与所述第十八斩波开关的第二端相连并连接所述第十九MOS管的源极，所述第十九斩波开关的第二端与所述第二十斩波开关的第二端相连并连接所述第二十MOS管的源极；所述第十九MOS管的栅极连接所述第二十MOS管的栅极并连接第三栅控电压，所述第十九MOS管的漏极连接所述第二十一MOS管的漏极、所述第二十一斩波开关的第一端和所述第二十二斩波开关的第一端，所述第二十MOS管的漏极连接所述第二十二MOS管的漏极、所述第二十三斩波开关的第一端和所述第二十四斩波开关的第一端；所述第二十一MOS管的栅极连接所述第二十二MOS管的栅极并连接第四栅控电压，所述第二十一MOS管的源极连接所述第二十三MOS管的漏极，所述第二十二MOS管的源极连接所述第二十四MOS管的漏极；所述第二十三MOS管的栅极连接所述第二十四MOS管的栅极，所述第二十三MOS管的源极和所述第二十四MOS管的源极接地；所述第二十一斩波开关的第二端连接所述第二十三斩波开关的第二端并连接所述第二十三MOS管的栅极，所述第二十二斩波开关的第二端连接所述第二十四斩波开关的第二端并作为所述放大解调单元的输出端；其中，所述第十七斩波开关、所述第二十斩波开关、所述第二十一斩波开关和所述第二十四斩波开关受控于第一时钟，所述第十八斩波开关、所述第十九斩波开关、所述第二十二斩波开关和所述第二十三斩波开关受控于第二时钟，所述第一时钟和所述第二时钟互为一组反相时钟。Alternatively, the amplification and demodulation unit includes: a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a nineteenth MOS tube, a twentieth MOS tube tube, the twenty-first MOS tube, the twenty-second MOS tube, the twenty-third MOS tube, the twenty-fourth MOS tube, the seventeenth chopper switch, the eighteenth chopper switch, the nineteenth chopper switch , the twentieth chopper switch, the twenty-first chopper switch, the twenty-second chopper switch, the twenty-third chopper switch and the twenty-fourth chopper switch; the gate of the fourteenth MOS tube The gate of the fifteenth MOS transistor is connected to the two output terminals of the chopper modulation unit, and the source of the fourteenth MOS transistor and the source of the fifteenth MOS transistor are connected to the source of the first MOS transistor. The drain of the sixteenth MOS tube, the drain of the fourteenth MOS tube is connected to the drain of the twenty-third MOS tube, and the drain of the fifteenth MOS tube is connected to the twenty-fourth MOS tube. The drain of the sixteenth MOS transistor is connected to the first gate control voltage, and the source is connected to the source of the seventeenth MOS transistor and the source of the eighteenth MOS transistor and connected to the power supply voltage; The gate of the seventeenth MOS transistor is connected to the gate of the eighteenth MOS transistor and connected to the second gate control voltage, and the drain of the seventeenth MOS transistor is connected to the seventh gate of the seventeenth chopper switch. One end is connected to the first end of the nineteenth chopper switch, and the drain of the eighteenth MOS tube is connected to the first end of the eighteenth chopper switch and the twentieth chopper switch. One end; the second end of the seventeenth chopper switch is connected to the second end of the eighteenth chopper switch and connected to the source of the nineteenth MOS tube. The nineteenth chopper switch The second end of the switch is connected to the second end of the twentieth chopper switch and connected to the source of the twentieth MOS tube; the gate of the nineteenth MOS tube is connected to the gate of the twentieth MOS tube. The gate is also connected to the third gate control voltage, and the drain of the nineteenth MOS transistor is connected to the drain of the twenty-first MOS transistor, the first end of the twenty-first chopper switch and the first end of the chopper switch. The first end of the twenty-second chopper switch, the drain of the twentieth MOS transistor is connected to the drain of the twenty-second MOS transistor, the first end of the twenty-third chopper switch and the The first end of the twenty-fourth chopper switch; the gate of the twenty-first MOS transistor is connected to the gate of the twenty-second MOS transistor and connected to the fourth gate control voltage. The source of the tube is connected to the drain of the twenty-third MOS tube, and the source of the twenty-second MOS tube is connected to the drain of the twenty-fourth MOS tube; The gate is connected to the gate of the twenty-fourth MOS tube, the source of the twenty-third MOS tube and the source of the twenty-fourth MOS tube are grounded; the twenty-first chopper switch The second terminal is connected to the second terminal of the twenty-third chopper switch and to the gate of the twenty-third MOS transistor, and the second terminal of the twenty-second chopper switch is connected to the twentieth The second end of the four chopper switches serves as the output end of the amplification and demodulation unit; wherein, the seventeenth chopper switch, the twentieth chopper switch, the twenty-first chopper switch and The twenty-fourth chopper switch is controlled by a first clock, the eighteenth chopper switch, the nineteenth chopper switch, the twenty-second chopper switch and the twenty-third chopper switch The chopper switch is controlled by a second clock, and the first clock and the second clock are a set of inverted clocks.
  11. 根据权利要求7所述的基准电路，其特征在于，所述陷波滤波单元包括：第六电阻、 第七电阻、第八电阻、第四电容、第五电容及第六电容；所述第六电阻的第一端连接所述第四电容的第一端并连接所述放大解调单元的输出端，第二端连接所述第七电阻的第一端和所述第五电容的第一端；所述第四电容的第二端连接所述第六电容的第一端和所述第八电阻的第一端；所述第七电阻的第二端连接所述第六电容的第二端并作为所述陷波滤波单元的输出端；所述第五电容的第二端接地；所述第八电阻的第二端接地；其中，所述第六电阻、所述第七电阻和所述第八电阻采用开关电容电路实现，所述开关电容电路中开关的控制时钟与斩波时钟除频相移45°。The reference circuit according to claim 7, characterized in that the notch filter unit includes: a sixth resistor, A seventh resistor, an eighth resistor, a fourth capacitor, a fifth capacitor and a sixth capacitor; the first end of the sixth resistor is connected to the first end of the fourth capacitor and connected to the output end of the amplification and demodulation unit , the second end is connected to the first end of the seventh resistor and the first end of the fifth capacitor; the second end of the fourth capacitor is connected to the first end of the sixth capacitor and the eighth resistor The first end of the seventh resistor is connected to the second end of the sixth capacitor and serves as the output end of the notch filter unit; the second end of the fifth capacitor is connected to ground; the second end of the fifth capacitor is connected to the ground; The second end of the eight resistors is grounded; wherein the sixth resistor, the seventh resistor and the eighth resistor are implemented by a switched capacitor circuit, and the control clock of the switch in the switched capacitor circuit is in phase with the chopping clock. Move 45°.
  12. 根据权利要求5或11所述的基准电路，其特征在于，所述开关电容电路中的开关采用NMOS管实现，其中，NMOS管的衬底中包括一个DPWDN隔离二极管及一个DDNPWPSUB隔离二极管。 The reference circuit according to claim 5 or 11, characterized in that the switch in the switched capacitor circuit is implemented by an NMOS tube, wherein the substrate of the NMOS tube includes a DPWDN isolation diode and a DDNPWPSUB isolation diode.
PCT/CN2023/082753 2022-08-09 2023-03-21 Reference circuit WO2024031991A1 (en)

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CN110247654A (en) * 2019-06-19 2019-09-17 许昌学院 A kind of amplification demodulator circuit applied to portable patient monitor equipment
CN111628735A (en) * 2020-06-11 2020-09-04 上海传卓电子有限公司 High-precision linear Hall sensor reading circuit
CN115237194A (en) * 2022-08-09 2022-10-25 上海烨映微电子科技股份有限公司 Reference circuit
CN217821383U (en) * 2022-08-09 2022-11-15 上海烨映微电子科技股份有限公司 Reference circuit

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CN103488232A (en) * 2013-09-30 2014-01-01 深圳市芯海科技有限公司 Chopping band-gap reference circuit based on CMOS process and reference voltage chip
CN104601127A (en) * 2013-10-31 2015-05-06 上海华虹集成电路有限责任公司 Operational amplifier circuit and reference voltage generating circuit module
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CN110247654A (en) * 2019-06-19 2019-09-17 许昌学院 A kind of amplification demodulator circuit applied to portable patient monitor equipment
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