CN105680835B - Hysteresis comparator applied to the receiving end RS-485 - Google Patents
Hysteresis comparator applied to the receiving end RS-485 Download PDFInfo
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- CN105680835B CN105680835B CN201610140026.5A CN201610140026A CN105680835B CN 105680835 B CN105680835 B CN 105680835B CN 201610140026 A CN201610140026 A CN 201610140026A CN 105680835 B CN105680835 B CN 105680835B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
Abstract
The invention discloses a kind of hysteresis comparators applied to the receiving end RS-485, including bleeder circuit, folded cascode Op Amp, polarity switch and hysteresis voltage control circuit, bleeder circuit is used to carry out level linear displacement to two input signals of hysteresis comparator, handles convenient for subsequent conditioning circuit；Folded cascode Op Amp is connected with the bleeder circuit, is compared to two signals after level shift；Polarity switch is in the folded cascode Op Amp, according to the digital output results of external polarity detection system, is accordingly exchanged comparator polarity；Hysteresis voltage control circuit is connected with the folded cascode Op Amp, for adjusting hysteresis voltage section.Hysteresis comparator of the invention solves the problems, such as in the nonpolarity receiving end RS-485 after the exchange of comparator polarity that sluggish section is positive section, and polarity exchange front and back can guarantee that the sluggish section of comparator is between -200mV ~ -50mV.
Description
Technical field
The present invention relates to electric energy communication system of power grids field or Analogical Circuit Technique fields, more particularly to are applied to RS-485 and receive
A kind of hysteresis comparator at end.
Background technique
RS-485 is by Electronic Industries Association (EIA) and a kind of serial line interface mark formulated with Telecommunications Industries Association (TIA)
It is quasi-.RS-485 interface has the characteristics that strong noise inhibition, relatively high transmission rate, long transmission distance, wide common mode range, simultaneously
RS-485 communication interface chip has many advantages, such as easy to control, low in cost.
The pin definitions of RS-485 communication interface chip are as shown in Fig. 2, wherein：RO is receiving end output signal；RE is
Receiving end enable signal；DE is transmitting terminal enable signal；DI is transmitting terminal input signal；VDD is power supply；A/B is signal pins,
Letter when DE, RE are high level " 1 ", as the output pin of balance driver, when DE, RE are 0, as receiving end
Number input pin；GND is ground.
Nonpolarity RS-485 communication interface chip can detect the polarity of A, B signal line automatically, and according to testing result in core
It is adjusted inside piece, it is completely compatible, it can be achieved that substitution, does not increase in pin definitions with original polarized RS-485 chip
Cost.
Chinese No. 201220086354.9 utility model patents disclose a kind of non-polar 485 chip, mainly include difference
Component voltage detection circuit, 5ms integrating circuit, communication polarity identification switch circuit, the voltage between communication A, the B foot of 485 chips
In lasting 5ms, Vab is kept>When 0, communication polarity identification switch circuit is failure to actuate, and the communication A foot access of 485 chips of default is logical
On the A route for interrogating bus, on the B route of the communication B foot incoming communication bus of 485 chips；When between communication A, the B foot of 485 chips
The lasting 5ms of voltage in, keep Vab<When 0, the overturning of communication polarity identification circuit, it is total that the communication A foot of 485 chips is connected to communication
In the B bus of line, on the A route of the communication B foot incoming communication bus of 485 chips.
Although above-mentioned patented technology provides a kind of non-polar 485 chip, but it has the disadvantage that, when receiving end is compared
When device sluggishness section is between -200mV~-50mV, after the method, comparator hysteresis section becomes+50mV~+200mV, A/
In the states such as short circuit, idle, open circuit, RO output can change in the case of just connecing and being reversely connected two kinds at the end B.
Summary of the invention
In order to solve above-mentioned technical problem, the object of the present invention is to provide a kind of sluggish ratios applied to the receiving end RS-485
Compared with device, to solve the problems, such as that comparator hysteresis section becomes positive section after polarity exchange.
In order to achieve the above objectives, a kind of hysteresis comparator applied to the receiving end RS-485 of the invention, including partial pressure electricity
Road, folded cascode Op Amp, polarity switch and hysteresis voltage control circuit, bleeder circuit are used for hysteresis comparator
Two input signals carry out level linear displacement, convenient for subsequent conditioning circuit handle；Folded cascode Op Amp and the partial pressure
Circuit is connected, and is compared to two signals after level shift；Polarity switch is in Foldable cascade fortune
In putting, according to the digital output results of external polarity detection system, comparator polarity is accordingly exchanged；Hysteresis voltage control
Circuit is connected with the folded cascode Op Amp, for adjusting hysteresis voltage section.
Further improvement is that the bleeder circuit contains：First PMOS tube, the second PMOS tube, third PMOS tube, the 4th
PMOS tube and four resistance：First resistor, second resistance, 3rd resistor, the 4th resistance；Wherein, first PMOS tube
Source electrode and the source electrode of the second PMOS tube all meet supply voltage VDD, and grid connects the first bias voltage VBP1, the leakage of first PMOS tube
Pole is connected with the source electrode of the third PMOS tube, and the drain electrode of second PMOS tube is connected with the source electrode of the 4th PMOS tube, institute
The grid for stating third PMOS tube is connected with drain electrode, then is connected with one end of first resistor, second resistance, the 4th PMOS tube
Grid is connected with drain electrode, then is connected with one end of 3rd resistor, the 4th resistance, another termination input signal of the first resistor
A, another termination GND of the second resistance, another termination input signal B of the 3rd resistor, the 4th resistance it is another
One termination GND.
Further improvement is that the folded cascode Op Amp is by five PMOS tube：5th PMOS tube, the 6th PMOS
Pipe, the 7th PMOS tube, the 8th PMOS tube, the 9th PMOS tube, four NMOS tubes：5th NMOS tube, the 6th NMOS tube, the 7th NMOS
Pipe, the 8th NMOS tube composition；
Source electrode, the source electrode of the 8th PMOS tube and the source electrode of the 9th PMOS tube of 5th PMOS tube all connect electricity
Source voltage VDD, the grid of the 5th PMOS tube meet the first bias voltage VBP1, and the source electrode and substrate of the 6th PMOS tube are mutual
Connection, then is connected with the drain electrode of the 5th PMOS tube, source electrode and the substrate interconnection of the 7th PMOS tube, then with the 5th PMOS
The drain electrode of pipe is connected, and the grid of the 6th PMOS tube is connected with the source electrode of the drain electrode of the first PMOS tube and third PMOS tube, this
The drain electrode of the grid of seven PMOS tube and the second PMOS tube and the source electrode of the 4th PMOS tube are connected, the grid of the 7th NMOS tube with
The grid of 8th NMOS tube is connected, and is all connected on the second bias voltage VBN2, the source electrode and the 8th NMOS of the 7th NMOS tube
The source electrode of pipe is all connect with GND, and the grid of the 5th NMOS tube and the grid of the 6th NMOS tube are connected, and it is inclined to be all connected to third
It sets on voltage VBN3, the source electrode of the 5th NMOS tube is connected with the drain electrode of the 7th NMOS tube, the source electrode of the 6th NMOS tube
It is connected with the drain electrode of the 8th NMOS tube, the 8th PMOS tube is connected with the grid of the 9th PMOS tube, the 8th PMOS
The grid of pipe is connected with drain electrode, then is connected with the drain electrode of the 5th NMOS tube, the drain electrode of the 9th PMOS tube and described the
The drain electrode of six NMOS tubes is connected.
Further improvement is that the polarity switch contains：First NMOS tube, the second NMOS tube, third NMOS tube,
Four NMOS tubes；The digital output signal of the external polarity detection system is CLK and CLK '；Wherein：First NMOS tube
Drain electrode is connected with the drain electrode of the third NMOS tube, then is connected with the drain electrode of the 6th PMOS tube, the drain electrode of second NMOS tube
It is connected with the drain electrode of the 4th NMOS tube, then is connected with the drain electrode of the 7th PMOS tube, the grid of first NMOS tube and
The grid of two NMOS tubes is connected, and is all connected on CLK, and the grid of the third NMOS tube and the grid of the 4th NMOS tube are connected,
It is all connected on CLK ', the source electrode of first NMOS tube and the source electrode of the 4th NMOS tube are connected, then the leakage with the 8th NMOS tube
Extremely it is connected, the source electrode of second NMOS tube is connected with the source electrode of third NMOS tube, then is connected with the drain electrode of the 7th NMOS tube.
Further improvement is that the hysteresis voltage control circuit contains：5th resistance, also containing there are five NMOS tubes：9th
NMOS tube, the tenth NMOS tube, the 11st NMOS tube, the 12nd NMOS tube, the 13rd NMOS tube, also containing there are three phase inverters：The
One phase inverter, the second phase inverter, third phase inverter；Wherein：The grid and third bias voltage VBN3 of 9th NMOS tube connect
It connecing, the drain electrode of the 9th NMOS tube is connected with one end of the 5th resistance, another termination supply voltage VDD of the 5th resistance,
The drain electrode of the source electrode of 9th NMOS tube and the 9th PMOS tube and the drain electrode of the 6th NMOS tube are connected, then with the first phase inverter
Input is connected, and the output of first phase inverter is connected with the input of the second phase inverter, the output of second phase inverter and institute
The input for stating third phase inverter is connected, and the output of the third phase inverter is OUT, and the grid of the tenth NMOS tube and first is instead
The output end of phase device is connected, and the drain electrode of the tenth NMOS tube is connected with the drain electrode of the 8th NMOS tube, the source electrode of the tenth NMOS tube
It is connected with the drain electrode of the 12nd NMOS tube, the grid of the 11st NMOS tube is connected with the output end of the second phase inverter,
The drain electrode of 11st NMOS tube is connected with the drain electrode of the 7th NMOS tube, the source electrode of the 11st NMOS tube and the described 13rd
The drain electrode of NMOS tube is connected, and the grid of the 12nd NMOS tube is connected with the grid of the 13rd NMOS tube, is all connected to
On second bias voltage VBN2, the source electrode of the 12nd NMOS tube and the source electrode of the 13rd NMOS tube are all connect with GND.
The beneficial effects of the invention are as follows：The invention proposes a kind of hysteresis comparator applied to the receiving end RS-485, solutions
Determined in the nonpolarity receiving end RS-485 sluggish section after the exchange of comparator polarity be positive section the problem of, polarity exchange front and back is all
It can guarantee that the sluggish section of comparator is between -200mV~-50mV.
Detailed description of the invention
Fig. 1 is the circuit diagram of hysteresis comparator of the invention.
Fig. 2 is the pin definitions of RS-485 communication interface chip.
Specific embodiment
The present invention will be described in detail below with reference to the accompanying drawings and embodiments.
Referring to shown in attached drawing 1, a kind of hysteresis comparator applied to the receiving end RS-485 of the present invention, including partial pressure
Circuit, folded cascode Op Amp, polarity switch and hysteresis voltage control circuit：
The bleeder circuit contains：First PMOS tube MP6, the second PMOS tube MP7, third PMOS tube MP4, the 4th PMOS tube
MP5 and four resistance：First resistor r1, second resistance r2,3rd resistor r3, the 4th resistance r4, wherein described first
The source electrode of the source electrode of PMOS tube MP6 and the second PMOS tube MP7 all meet supply voltage VDD, and grid meets the first bias voltage VBP1, should
The drain electrode of first PMOS tube MP6 is connected with the source electrode of the third PMOS tube MP4, the drain electrode of second PMOS tube MP7 and described
The source electrode of 4th PMOS tube MP5 is connected, and the grid of the third PMOS tube MP4 and draining is connected, then with first resistor r1, second
One end of resistance r2 is connected, and the grid of the 4th PMOS tube MP5 and draining is connected, then with 3rd resistor r3, the 4th resistance r4
One end be connected, another termination input signal A of the first resistor r1, another termination GND of the second resistance r2 are described
Another termination input signal B, another termination GND of the 4th resistance r4 of 3rd resistor r3.
The folded cascode Op Amp and polarity switch circuit contain：Five PMOS tube：5th PMOS tube
MP3, the 6th PMOS tube MP1, the 7th PMOS tube MP2, the 8th PMOS tube MP8, the 9th PMOS tube MP9 also contain：Eight NMOS
Pipe：First NMOS tube MN1, the second NMOS tube MN2, third NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th
NMOS tube MN6, the 7th NMOS tube MN8, the 8th NMOS tube MN9, wherein：The source electrode of the 5th PMOS tube MP3, the described 8th
The source electrode of the source electrode of PMOS tube MP8 and the 9th PMOS tube MP9 all connect supply voltage VDD, the grid of the 5th PMOS tube MP3
The first bias voltage is connect, the source electrode and substrate of the 6th PMOS tube MP1 is connected with each other, then the drain electrode with the 5th PMOS tube MP3
It is connected, the source electrode and substrate of the 7th PMOS tube MP2 is connected with each other, then is connected with the drain electrode of the 5th PMOS tube MP3, and the 6th
The grid of PMOS tube MP1 is connected with the source electrode of the drain electrode of the first PMOS tube MP6 and third PMOS tube MP4, the 7th PMOS tube MP2
The drain electrode of grid and the second PMOS tube MP7 and the source electrode of the 4th PMOS tube MP5 be connected, the drain electrode of the first NMOS tube MN1
It is connected with the drain electrode of the third NMOS tube MN3, then is connected with the drain electrode of the 6th PMOS tube MP1, the second NMOS tube MN2's
Drain electrode is connected with the drain electrode of the 4th NMOS tube MN4, then is connected with the drain electrode of the 7th PMOS tube MP2, first NMOS tube
The grid of the grid of MN1 and the second NMOS tube MN2 are connected, and are all connected on CLK, the grid of the third NMOS tube MN3 and the
The grid of four NMOS tube MN4 is connected, and is all connected on CLK ', the source electrode of the first NMOS tube MN1 and the 4th NMOS tube MN4's
Source electrode is connected, then is connected with the drain electrode of the 8th NMOS tube MN9, the source electrode of the second NMOS tube MN2 and third NMOS tube MN3's
Source electrode is connected, then is connected with the drain electrode of the 7th NMOS tube MN8, the grid of the 7th NMOS tube MN8 and the 8th NMOS tube MN9's
Grid is connected, and is all connected on the second bias voltage VBN2, the source electrode of the 7th NMOS tube MN8 and the source of the 8th NMOS tube MN9
Pole is all connect with GND, and the grid of the 5th NMOS tube MN5 and the grid of the 6th NMOS tube MN6 are connected, and it is inclined to be all connected to third
It sets on voltage VBN3, the source electrode of the 5th NMOS tube MN5 is connected with the drain electrode of the 7th NMOS tube MN8, the 6th NMOS tube
The source electrode of MN6 is connected with the drain electrode of the 8th NMOS tube MN9, the grid of the 8th PMOS tube MP8 and the 9th PMOS tube MP9
It is connected, the grid of the 8th PMOS tube MP8 is connected with draining, then is connected with the drain electrode of the 5th NMOS tube MN5, and described the
The drain electrode of nine PMOS tube MP9 is connected with the drain electrode of the 6th NMOS tube MN6.
The hysteresis voltage control circuit contains：5th resistance r5, also containing there are five NMOS tubes：9th NMOS tube MN7, the
Ten NMOS tube MN10, the 11st NMOS tube MN11, the 12nd NMOS tube MN12, the 13rd NMOS tube MN13, also containing there are three anti-
Phase device：First phase inverter inv1, the second phase inverter inv2, third phase inverter inv3, wherein：The grid of the 9th NMOS tube MN7
Pole is connect with third bias voltage VBN3, and the drain electrode of the 9th NMOS tube MN7 is connected with one end of the 5th resistance r5, and the described 5th
The drain electrode of the source electrode and the 9th PMOS tube MP9 of another termination supply voltage VDD of resistance r5, the 9th NMOS tube MN7 and
The drain electrode of six NMOS tube MN6 is connected, then is connected with the input of the first phase inverter inv1, the output of the first phase inverter inv1 and
The input of second phase inverter inv2 is connected, the output and the input phase of the third phase inverter inv3 of the second phase inverter inv2
Even, the output of the third phase inverter inv3 is OUT, and the grid of the tenth NMOS tube MN10 is defeated with the first phase inverter inv1's
Outlet is connected, and the drain electrode of the tenth NMOS tube MN10 is connected with the drain electrode of the 8th NMOS tube MN9, the source of the tenth NMOS tube MN10
Pole is connected with the drain electrode of the 12nd NMOS tube MN12, the grid and the second phase inverter inv2 of the 11st NMOS tube MN11
Output end be connected, the drain electrode of the 11st NMOS tube MN11 is connected with the drain electrode of the 7th NMOS tube MN8, the 11st NMOS tube
The source electrode of MN11 is connected with the drain electrode of the 13rd NMOS tube MN13, the grid of the 12nd NMOS tube MN12 and described the
The grid of 13 NMOS tube MN13 is connected, and is all connected on the second bias voltage VBN2, the source of the 12nd NMOS tube MN12
The source electrode of pole and the 13rd NMOS tube MN13 are all connect with GND.
Referring to shown in attached drawing 1, in order to seek the positive and negative turn threshold point of comparator, when CLK is that high level makes MN1 and MN2
Conducting when CLK ' is that low level turns off MN3 and MN4, allows the end A voltage to be fixed on 0V, and the input of the end B gradually subtracts from 12V to -7V
Small voltage, MP1 is connected when beginning, and MP2 almost ends, and the electric current of MP3 is nearly all flowed through from MP1, and the drain terminal voltage of MN6 is
The electric current of height, MP9 and MN7 are all almost that the electric current of 0, MN5 all flows into MN8, the electric current very little of MN11 branch, with the end B voltage
Continuing to reduce, the electric current of MP2 slowly increases, and the electric current of MP1 reduces, so that MN5 drain terminal voltage reduces, the electric current of MP8 reduces,
The electric current of MP9, MN5 all slowly increase, when the electric current of MP8 and MP9 is equal, phase inverter overturning, and after overturning, the electricity of MP9
Stream reduces, and the electric current of MN7 increases, and correspondence can acquire positive turn threshold point and be：
Negative turn threshold point, which can similarly be acquired, is：
When polarity needs to overturn, the port A/B is exchanged, while CLK should be low level and MN1 and MN2 is turned off, and CLK ' is answered
For high level MN3 and MN4 is connected, the positive and negative turn threshold voltage after may make polarity upset so is still all negative value.
It is understood that the foregoing is only a preferred embodiment of the present invention, it is not intended to restrict the invention, such as
Alteration switch in the present invention is not limited to NMOS switch, is also possible to PMOS switch or transmission gate switch etc., those skilled in the art
Member can be subject to equivalent substitution or change according to the technical scheme of the invention and its inventive conception, and all these changes or replacement
It all should belong to scope of protection of the claims attached by the present invention.
Claims (1)
1. a kind of hysteresis comparator applied to the receiving end RS-485, which is characterized in that including：
- bleeder circuit carries out level linear displacement for two input signals to hysteresis comparator, convenient at subsequent conditioning circuit
Reason；The bleeder circuit is by the first PMOS tube (MP6), the second PMOS tube (MP7), third PMOS tube (MP4), the 4th PMOS tube
(MP5) and four resistance：First resistor (r1), second resistance (r2), 3rd resistor (r3), the 4th resistance (r4) composition, institute
The source electrode of the source electrode and the second PMOS tube (MP7) of stating the first PMOS tube (MP6) all meets supply voltage VDD, and grid connects the first biasing
Voltage VBP1, the drain electrode of first PMOS tube (MP6) are connected with the source electrode of the third PMOS tube (MP4), second PMOS tube
(MP7) drain electrode is connected with the source electrode of the 4th PMOS tube (MP5), the grid and drain electrode phase of the third PMOS tube (MP4)
Even, then it is connected with one end of first resistor (r1), second resistance (r2), the grid and drain electrode phase of the 4th PMOS tube (MP5)
Even, then it is connected with one end of 3rd resistor (r3), the 4th resistance (r4), another termination input signal of the first resistor (r1)
A, another termination GND of the second resistance (r2), another termination input signal B of the 3rd resistor (r3), the described 4th
Another termination GND of resistance (r4)；
- folded cascode Op Amp is connected with the bleeder circuit, is compared to two signals after level shift；Institute
Folded cascode Op Amp is stated by five PMOS tube：5th PMOS tube (MP3), the 6th PMOS tube (MP1), the 7th PMOS tube
(MP2), the 8th PMOS tube (MP8), the 9th PMOS tube (MP9), four NMOS tubes：5th NMOS tube (MN5), the 6th NMOS tube
(MN6), the 7th NMOS tube (MN8), the 8th NMOS tube (MN9) composition, the source electrode of the 5th PMOS tube (MP3), the described 8th
The source electrode of PMOS tube (MP8) and the source electrode of the 9th PMOS tube (MP9) all meet supply voltage VDD, the 5th PMOS tube (MP3)
Grid meets the first bias voltage VBP1, and the source electrode and substrate of the 6th PMOS tube (MP1) are connected with each other, then with the 5th PMOS tube
(MP3) drain electrode is connected, and the source electrode and substrate of the 7th PMOS tube (MP2) are connected with each other, then with the 5th PMOS tube (MP3)
Drain electrode is connected, the grid of the 6th PMOS tube (MP1) and the drain electrode of the first PMOS tube (MP6) and third PMOS tube (MP4)
Source electrode is connected, the source electrode of the grid of the 7th PMOS tube (MP2) and the drain electrode of the second PMOS tube (MP7) and the 4th PMOS tube (MP5)
It is connected, the grid of the 7th NMOS tube (MN8) and the grid of the 8th NMOS tube (MN9) are connected, and are all connected to the second biased electrical
It presses on VBN2, the source electrode of the 7th NMOS tube (MN8) and the source electrode of the 8th NMOS tube (MN9) are all connect with GND, the 5th NMOS
The grid of the grid and the 6th NMOS tube (MN6) of managing (MN5) is connected, and is all connected on third bias voltage VBN3, the described 5th
The source electrode of NMOS tube (MN5) is connected with the drain electrode of the 7th NMOS tube (MN8), the source electrode and the 8th of the 6th NMOS tube (MN6)
The drain electrode of NMOS tube (MN9) is connected, and the 8th PMOS tube (MP8) is connected with the grid of the 9th PMOS tube (MP9), described
The grid of 8th PMOS tube (MP8) is connected with drain electrode, then is connected with the drain electrode of the 5th NMOS tube (MN5), and the described 9th
The drain electrode of PMOS tube (MP9) is connected with the drain electrode of the 6th NMOS tube (MN6)；
- polarity switch, it is defeated according to the number of external polarity detection system in the folded cascode Op Amp
Out as a result, accordingly being exchanged comparator polarity；The polarity switch is by the first NMOS tube (MN1), the second NMOS tube
(MN2), third NMOS tube (MN3), the 4th NMOS tube (MN4) composition；The digital output signal of the external polarity detection system
For CLK and CLK ', the drain electrode of first NMOS tube (MN1) is connected with the drain electrode of the third NMOS tube (MN3), then with the 6th
The drain electrode of PMOS tube (MP1) is connected, the drain electrode of second NMOS tube (MN2) and the drain electrode phase of the 4th NMOS tube (MN4)
Even, then it is connected with the drain electrode of the 7th PMOS tube (MP2), the grid of first NMOS tube (MN1) and the second NMOS tube (MN2)
Grid is connected, and is all connected on CLK, and the grid of the third NMOS tube (MN3) and the grid of the 4th NMOS tube (MN4) are connected,
It is all connected on CLK ', the source electrode of the source electrode of first NMOS tube (MN1) and the 4th NMOS tube (MN4) is connected, then with the 8th
The drain electrode of NMOS tube (MN9) is connected, and the source electrode of second NMOS tube (MN2) is connected with the source electrode of third NMOS tube (MN3), then
It is connected with the drain electrode of the 7th NMOS tube (MN8)；
- hysteresis voltage control circuit, is connected with the folded cascode Op Amp, for adjusting hysteresis voltage section；It is described
Hysteresis voltage control circuit is by the 5th resistance (r5), five NMOS tubes：9th NMOS tube (MN7), the tenth NMOS tube (MN10),
11 NMOS tubes (MN11), the 12nd NMOS tube (MN12), the 13rd NMOS tube (MN13), three phase inverters：First phase inverter
(inv1), the second phase inverter (inv2), third phase inverter (inv3) composition, the grid and third of the 9th NMOS tube (MN7)
Bias voltage VBN3 connection, the drain electrode of the 9th NMOS tube (MN7) are connected with one end of the 5th resistance (r5), the 5th resistance
(r5) another termination supply voltage VDD, the source electrode of the 9th NMOS tube (MN7) and the drain electrode of the 9th PMOS tube (MP9) and
The drain electrode of 6th NMOS tube (MN6) is connected, then is connected with the input of the first phase inverter (inv1), first phase inverter (inv1)
Output be connected with the input of the second phase inverter (inv2), the output of second phase inverter (inv2) and the third phase inverter
(inv3) input is connected, and the output of the third phase inverter (inv3) is OUT, the grid of the tenth NMOS tube (MN10) with
The output end of first phase inverter (inv1) is connected, the drain electrode of the tenth NMOS tube (MN10) and the drain electrode of the 8th NMOS tube (MN9)
It is connected, the source electrode of the tenth NMOS tube (MN10) is connected with the drain electrode of the 12nd NMOS tube (MN12), and the described 11st
The grid of NMOS tube (MN11) is connected with the output end of the second phase inverter (inv2), the drain electrode of the 11st NMOS tube (MN11) with
The drain electrode of 7th NMOS tube (MN8) is connected, the source electrode of the 11st NMOS tube (MN11) and the 13rd NMOS tube (MN13)
Drain electrode be connected, the grid of the 12nd NMOS tube (MN12) is connected with the grid of the 13rd NMOS tube (MN13), all
It is connected on the second bias voltage VBN2, the source electrode of the 12nd NMOS tube (MN12) and the 13rd NMOS tube (MN13)
Source electrode all connect with GND.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610140026.5A CN105680835B (en) | 2016-03-14 | 2016-03-14 | Hysteresis comparator applied to the receiving end RS-485 |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610140026.5A CN105680835B (en) | 2016-03-14 | 2016-03-14 | Hysteresis comparator applied to the receiving end RS-485 |
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| CN105680835A CN105680835A (en) | 2016-06-15 |
| CN105680835B true CN105680835B (en) | 2018-11-20 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106330104A (en) * | 2016-10-14 | 2017-01-11 | 湘潭芯力特电子科技有限公司 | Fully differential amplifier circuit with high accuracy and high dynamic range |
| CN112311363A (en) * | 2019-07-30 | 2021-02-02 | 光宝科技新加坡私人有限公司 | Comparator circuit with hysteresis function |
| CN110806777B (en) * | 2019-12-02 | 2021-02-12 | 湖南品腾电子科技有限公司 | Low-power consumption small-area temperature compensation low-voltage detection circuit |
| CN110958031B (en) * | 2019-12-26 | 2021-05-07 | 上海贝岭股份有限公司 | RS485 receiver circuit, integrated circuit and transceiver |
| CN113556103B (en) * | 2020-04-26 | 2023-07-04 | 智原微电子(苏州)有限公司 | Comparison circuit and comparison module with hysteresis function |
| CN112671359B (en) * | 2020-12-24 | 2024-04-02 | 上海贝岭股份有限公司 | Comparator circuit and RS485 receiver circuit |
| CN114553207B (en) * | 2022-03-02 | 2022-11-25 | 成都芯翼科技有限公司 | Low-jitter receiver circuit |
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