CN112825477A - High-voltage operational amplifier and input stage circuit thereof - Google Patents
High-voltage operational amplifier and input stage circuit thereof Download PDFInfo
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- CN112825477A CN112825477A CN201911141749.7A CN201911141749A CN112825477A CN 112825477 A CN112825477 A CN 112825477A CN 201911141749 A CN201911141749 A CN 201911141749A CN 112825477 A CN112825477 A CN 112825477A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
Abstract
The application discloses high-voltage operational amplifier and input stage circuit thereof, input stage circuit is including constituting first transistor and the second transistor of differential transistor pair, the current source and connect first clamp module and the second clamp module between the control end of first transistor and second transistor and first end respectively, when the differential input signal of input is greater than threshold voltage, first clamp module or second clamp module begin to play a role, with the control end voltage clamp of differential transistor pair in normal voltage scope, avoid the production of heavy current in the circuit, protect input stage circuit's differential transistor pair.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a high-voltage operational amplifier and an input stage circuit thereof.
Background
An operational amplifier is a circuit that can amplify a difference between two input voltages, and is also called a differential amplifier. Fig. 1 shows a schematic structure of an existing operational amplifier, and as shown in fig. 1, an operational amplifier 100 includes a differential input circuit 110, an intermediate stage circuit 120, an output stage circuit 130, and a bias circuit 140. The differential input circuit 110 is also called a pre-stage circuit, and is generally a two-terminal input high-performance differential amplifier circuit, and its input terminal is used to input a pair of differential signals. The intermediate stage circuit 120 is a main amplifier circuit of the amplifier, and functions to make the operational amplifier have a strong amplification capability, and a cascode (common source) amplifier circuit is often used. The output stage circuit 130 is used for outputting the amplified signal. The bias circuit is used for setting the static operating point of each stage of amplifying circuit in the operational amplifier.
With the development of technology, operational amplifiers are widely used in various circuits as comparators, and when the operational amplifiers are used as comparators, differential signals input at input terminals thereof are also developed from small differential signals to large differential signals such as positive power terminals. When a large differential signal equal to a power supply voltage is input to the input end of the operational amplifier, the gate-source voltage of the transistor of the differential input circuit is close to the power supply voltage, so that large current appears in a chip, and the chip is damaged.
Disclosure of Invention
In view of the above problems, it is an object of the present invention to provide a high voltage operational amplifier and an input stage circuit thereof, which clamp the control terminal voltage of a differential input transistor pair within a safe voltage range when a large differential signal equal to a power supply voltage is input, thereby preventing a large current from occurring in a chip and protecting the chip from damage.
According to a first aspect of the present invention, there is provided an input stage circuit of a high voltage operational amplifier, comprising: a first transistor having a control terminal for receiving a first input signal; a second transistor having a control terminal for receiving a second input signal; a current source connected to first ends of the first and second transistors; and the first clamping module and the second clamping module are respectively connected between the control ends and the first ends of the first transistor and the second transistor, and are respectively used for clamping the control ends of the first transistor and the second transistor at a constant preset voltage.
Preferably, the first input signal and the second input signal are differential input signals.
Preferably, the first clamping module and the second clamping module each include a first diode and a second diode, wherein anodes of the first diode and the second diode are connected to each other, a cathode of the first diode is connected to a first terminal of the first transistor or the second transistor, and a cathode of the second diode is connected to a control terminal of the first transistor or the second transistor.
Preferably, the first diode and the second diode are selected from zener diodes.
Preferably, the input stage circuit further comprises: a third transistor having a first terminal for receiving the first input signal, a control terminal connected to the first terminal of the first transistor, and a second terminal connected to the control terminal of the first transistor; and a fourth transistor having a first terminal for receiving the second input signal, a control terminal connected to the first terminal of the second transistor, and a second terminal connected to the control terminal of the second transistor.
Preferably, the input stage circuit further comprises: a first resistor having a first terminal connected to the first terminal of the third transistor and a second terminal connected to the control terminal of the first transistor; and a second resistor having a first terminal connected to the first terminal of the fourth transistor and a second terminal connected to the control terminal of the second transistor.
Preferably, the preset voltage is equal to the sum of a forward conduction voltage of the first diode, a reverse breakdown voltage of the second diode, and a gate-source voltage of the transistor.
According to a second aspect of the present invention, there is provided a high voltage operational amplifier, comprising the input stage circuit described above.
The input stage circuit of the high-voltage operational amplifier of the embodiment comprises a first transistor and a second transistor which form a differential transistor pair, a current source, and two clamping modules and two transistors which are respectively connected between the control end and the first end of the first transistor and the second transistor. When the differential input signal is small, the two transistors connected to the control terminals of the differential transistor pair operate in a linear state, which corresponds to two resistors. When the input differential input signal is greater than the threshold voltage, the clamping module starts to act to clamp the voltage of the control end of the differential transistor pair within a normal voltage range, so that the generation of large current in the circuit is avoided, and the differential transistor pair of the input stage circuit is protected.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 shows a circuit schematic of an operational amplifier according to the prior art;
FIG. 2 shows a circuit schematic of a high voltage operational amplifier according to an embodiment of the invention;
fig. 3 shows the variation of the control terminal voltage of the P-type MOSFET Mp1 in fig. 2 with the first input signal VIP.
Detailed Description
Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by the same or similar reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale.
It should be understood that in the following description, a "circuit" refers to a conductive loop formed by at least one element or sub-circuit through an electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.
In this application, the MOSFET comprises a first terminal, a second terminal and a control terminal, and in the on-state of the MOSFET a current flows from the first terminal to the second terminal. The first end, the second end and the control end of the P-type MOSFET are respectively a source electrode, a drain electrode and a grid electrode, and the first end, the second end and the control end of the N-type MOSFET are respectively a drain electrode, a source electrode and a grid electrode.
The invention is further illustrated with reference to the following figures and examples.
Fig. 2 shows a circuit schematic of a high voltage operational amplifier according to an embodiment of the invention. As shown in fig. 2, the high voltage operational amplifier 200 includes an input stage circuit 210 and an output stage circuit 220. The input stage circuit 210 is also called a pre-stage circuit, and is generally a two-terminal input high-performance differential amplifier circuit, in which a positive input terminal is used for inputting a first input signal VIP, a negative input terminal is used for inputting a second input signal VIN, and the first input signal VIP and the second input signal VIN are differential input signals. The output stage circuit 220 is an operational amplifier folded cascode single-ended output circuit.
Specifically, the input stage circuit 210 includes P-type MOSFETs Mp1 and Mp2 and a current source I1. The P-type MOSFETs Mp1 and Mp2 form a differential transistor pair, i.e. the first terminals of the P-type MOSFETs Mp1 and Mp2 are connected to each other, and the first terminals of the P-type MOSFETs Mp1 and Mp2 are both connected to the second terminal of the current source I1, and the first terminal of the current source I1 is connected to the positive power supply terminal VDD. The control terminal of the P-type MOSFET Mp1 is connected to the positive input terminal of the input stage circuit 210 for receiving the first input signal VIP, and the control terminal of the P-type MOSFET Mp2 is connected to the negative input terminal of the input stage circuit 210 for receiving the second input signal VIN. Second terminals of the P-type MOSFETs Mp1 and Mp2 are respectively connected to the output stage circuit 220.
The input stage circuit 210 also includes a first clamping block 211 and a second clamping block 212. The first clamping module 211 is connected between the first terminal and the control terminal of the P-type MOSFET Mp1, and is configured to clamp the control terminal voltage of the P-type MOSFET Mp1 at a constant predetermined voltage when the first input signal VIP is greater than a threshold voltage. The second clamping module 212 is connected between the first terminal and the control terminal of the P-type MOSFET Mp2, and is configured to clamp the control terminal voltage of the P-type MOSFET Mp2 at a constant predetermined voltage when the second input signal VIN is greater than a threshold voltage.
Further, the first clamping module 211 includes a diode D1 and a diode D2 which are connected in reverse, an anode of the diode D1 and an anode of the diode D2 are connected to each other, a cathode of the diode D1 is connected to the first terminal of the P-type MOSFET Mp1, and a cathode of the diode D2 is connected to the control terminal of the P-type MOSFET Mp 1. When the first input signal VIP increases to the sum of the forward conduction voltage of the diode D1 and the reverse breakdown voltage of the diode D2, the diode D1 and the diode D2 conduct, clamping the control terminal voltage of the P-type MOSFET Mp1 at a constant predetermined voltage.
The first clamping module 212 includes a diode D3 and a diode D4 connected in reverse, an anode of the diode D3 and an anode of the diode D4 are connected to each other, a cathode of the diode D3 is connected to a first terminal of the P-type MOSFET Mp2, and a cathode of the diode D4 is connected to a control terminal of the P-type MOSFET Mp 2. When the second input signal VIN increases to the sum of the forward conduction voltage of the diode D3 and the reverse breakdown voltage of the diode D4, the diode D3 and the diode D4 conduct to clamp the control terminal voltage of the P-type MOSFET Mp2 at a constant predetermined voltage.
In a further embodiment, the input stage circuit 210 further includes an N-type MOSFET Mn1 and a resistor R3. The control terminal of the N-type MOSFET Mn1 is connected to the first terminal of the P-type MOSFET Mp1, the first terminal of the N-type MOSFET Mn1 is connected to the positive input terminal of the input stage circuit 210, and the second terminal of the N-type MOSFET Mn1 is connected to the control terminal of the P-type MOSFET Mp 1. The resistor R3 has a first terminal connected to the positive input terminal of the input stage circuit 210 and a second terminal connected to the control terminal of the P-type MOSFET Mp 1.
Further, the input stage circuit 210 further includes an N-type MOSFET Mn2 and a resistor R4. The control terminal of the N-type MOSFET Mn2 is connected to the first terminal of the P-type MOSFET Mp2, the first terminal of the N-type MOSFET Mn2 is connected to the negative input terminal of the input stage circuit 210, and the second terminal of the N-type MOSFET Mn2 is connected to the control terminal of the P-type MOSFET Mp 2. The resistor R4 has a first terminal connected to the negative input terminal of the input stage circuit 210 and a second terminal connected to the control terminal of the P-type MOSFET Mp 2.
Fig. 3 shows the variation of the control terminal voltage of the P-type MOSFET Mp1 in fig. 2 with the first input signal VIP. In fig. 3, the voltage variation curve of the first input signal VIP is a dashed line, the voltage variation curve of the control terminal voltage VPG1 of the P-type MOSFET Mp1 is a solid line, and the voltage variation curves of the control terminal voltages VNG1 and VNG2 of the N-type MOSFETs Mn1 and Mn2 are dashed-dotted lines.
In the present embodiment, the diodes D1-D4 are, for example, zener diodes, and assuming that the forward conduction voltages of the diodes D1-D4 are 0.7V and the reverse breakdown voltage is 5.5V, the N-type MOSFETs Mn1 and Mn2 are depletion type high-voltage NMOS transistors, the resistances of the resistor R3 and the resistor R4 are 10M Ω, and the voltage of the positive power supply terminal VDD is 36V.
When the first input signal VIP is equal to 0, the N-type MOSFETs Mn1 and Mn2 are turned on, the control terminal voltage VPG1 of the P-type MOSFET Mp1 is equal to 0, and when the voltage of the first input signal VIP gradually increases, the control terminal voltage VPG1 of the P-type MOSFET Mp1 increases following the increase of the voltage of the first input signal VIP, and the control terminal voltage of the P-type MOSFET Mp2 remains unchanged.
When the first input signal VIP is equal to 3.2V, the N-type MOSFET Mn1 is turned off, the N-type MOSFET Mn2 remains turned on, and the control terminal voltage VPG1 of the P-type MOSFET Mp1 continues to increase following the increase in the voltage of the first input signal VIP.
When the first input signal VIP ≧ 7.4V (i.e., the voltage of the first input signal VIP is greater than the sum of the forward conduction voltage of the diode D1 and the reverse breakdown voltage of the diode D2), the diode D1 and the diode D2 conduct to clamp the control terminal voltage VPG1 of the P-type MOSFET Mp1 at 7.4V, and the control terminal voltage VPG1 of the P-type MOSFET Mp1 does not change as the voltage of the first input signal VIP increases. The maximum current in the chip at this time is:
Imax＝(36-7.4)V/10MΩ＝2.86uA
similarly, when the second input signal VIN is gradually increased, the working process of the first input signal VIP being unchanged is the opposite process to the above working process, and is not described herein again.
With continued reference to fig. 2, the amplifier stage circuit 220 includes P-type MOSFETs Mp 3-Mp 6, and N-type MOSFETs Mn 3-Mn 6.
The P-type MOSFETs Mp3 and Mp5, and the N-type MOSFETs Mn3 and Mn5 are sequentially connected in series in a first branch between a positive power supply terminal VDD and a negative power supply terminal VSS. In the on state of the four, a current flows from the positive power supply terminal VDD to the negative power supply terminal VSS through the P-type MOSFETs Mp3 and Mp5 and the N-type MOSFETs Mn3 and Mn 5.
And the P-type MOSFETs Mp4 and Mp6 and the N-type MOSFETs Mn4 and Mn6 are sequentially connected in series in a second branch between the positive power supply terminal VDD and the negative power supply terminal VSS. In the on state of the four, a current flows from the positive power supply terminal VDD to the negative power supply terminal VSS through the P-type MOSFETs Mp4 and Mp6 and the N-type MOSFETs Mn4 and Mn 6.
The control terminals of the P-type MOSFETs Mp3 and Mp4 are connected to each other and to the second terminal of the P-type MOSFET Mp5, forming mirror transistors with each other. The control terminals of the P-type MOSFETs Mp5 and Mp6 are connected to each other, and both receive the bias voltage Vb 1. The control terminals of the N-type MOSFETs Mn3 and Mn4 are connected to each other, and both receive the bias voltage Vb 2. The control terminals of the N-type mosfets Mn5 and Mn6 are connected to each other and receive a bias voltage Vb 3. The middle node of the N-type MOSFETs Mn3 and Mn5 is connected to the second end of the P-type MOSFET Mp1, and the middle node of the N-type MOSFETs Mn4 and Mn6 is connected to the second end of the P-type MOSFET Mp 2. The node A between the P-type MOSFET Mp6 and the N-type MOSFET Mn4 is used to provide the output signal Vout.
In summary, the input stage circuit of the high voltage operational amplifier of the present embodiment includes a first transistor and a second transistor that form a differential transistor pair, a current source, and two clamping modules and two transistors that are respectively connected between the control end and the first end of the first transistor and the second transistor. When the differential input signal is small, the two transistors connected to the control terminals of the differential transistor pair operate in a linear state, which corresponds to two resistors. When the input differential input signal is greater than the threshold voltage, the clamping module starts to act to clamp the voltage of the control end of the differential transistor pair within a normal voltage range, so that the generation of large current in the circuit is avoided, and the differential transistor pair of the input stage circuit is protected.
In accordance with the present invention, as set forth above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The scope of the invention should be determined from the following claims.
Claims (8)
1. An input stage circuit of a high-voltage operational amplifier, comprising:
a first transistor having a control terminal for receiving a first input signal;
a second transistor having a control terminal for receiving a second input signal;
a current source connected to first ends of the first and second transistors; and
first and second clamping modules connected between control and first terminals of the first and second transistors, respectively,
the first clamping module and the second clamping module are respectively used for clamping the control end voltage of the first transistor and the control end voltage of the second transistor at a constant preset voltage.
2. The input stage circuit of claim 1, wherein the first input signal and the second input signal are differential input signals.
3. The input stage circuit of claim 2, wherein the first clamping block and the second clamping block each comprise a first diode and a second diode,
wherein anodes of the first diode and the second diode are connected to each other,
a cathode of the first diode is connected to a first terminal of the first transistor or the second transistor,
the cathode of the second diode is connected to the control terminal of the first transistor or the second transistor.
4. The input stage circuit of claim 3, wherein the first diode and the second diode are selected from zener diodes.
5. The input stage circuit of claim 4, further comprising:
a third transistor having a first terminal for receiving the first input signal, a control terminal connected to the first terminal of the first transistor, and a second terminal connected to the control terminal of the first transistor; and
a fourth transistor having a first terminal for receiving the second input signal, a control terminal connected to the first terminal of the second transistor, and a second terminal connected to the control terminal of the second transistor.
6. The input stage circuit of claim 5, further comprising:
a first resistor having a first terminal connected to the first terminal of the third transistor and a second terminal connected to the control terminal of the first transistor; and
a second resistor having a first terminal connected to the first terminal of the fourth transistor and a second terminal connected to the control terminal of the second transistor.
7. The input stage circuit of claim 3, wherein the predetermined voltage is equal to a sum of a forward conduction voltage of the first diode, a reverse breakdown voltage of the second diode, and a gate-source voltage of a transistor.
8. A high voltage operational amplifier comprising an input stage circuit as claimed in any one of claims 1 to 7.
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| CN201911141749.7A CN112825477A (en) | 2019-11-20 | 2019-11-20 | High-voltage operational amplifier and input stage circuit thereof |
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| CN201911141749.7A CN112825477A (en) | 2019-11-20 | 2019-11-20 | High-voltage operational amplifier and input stage circuit thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023198037A1 (en) * | 2022-04-12 | 2023-10-19 | 圣邦微电子（北京）股份有限公司 | High-voltage input stage circuit without bias current |
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| US3879640A (en) * | 1974-02-11 | 1975-04-22 | Rca Corp | Protective diode network for MOS devices |
| US4158178A (en) * | 1978-05-15 | 1979-06-12 | Rca Corporation | Anti-latch circuit for amplifier stage including bipolar and field-effect transistors |
| JPS60160710A (en) * | 1984-01-31 | 1985-08-22 | Mitsubishi Heavy Ind Ltd | Two-way current control amplifier |
| US6114872A (en) * | 1996-05-31 | 2000-09-05 | Nippon Steel Corporation | Differential input circuit |
| US6121798A (en) * | 1998-10-05 | 2000-09-19 | Analog Devices, Inc. | High-speed comparator with improved latch accuracy |
| CN106020315A (en) * | 2015-03-26 | 2016-10-12 | 拉碧斯半导体株式会社 | Semiconductor device |
| CN108880488A (en) * | 2018-06-29 | 2018-11-23 | 思瑞浦微电子科技（苏州）股份有限公司 | The protection circuit of differential pair tube |
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2019
- 2019-11-20 CN CN201911141749.7A patent/CN112825477A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3879640A (en) * | 1974-02-11 | 1975-04-22 | Rca Corp | Protective diode network for MOS devices |
| US4158178A (en) * | 1978-05-15 | 1979-06-12 | Rca Corporation | Anti-latch circuit for amplifier stage including bipolar and field-effect transistors |
| JPS60160710A (en) * | 1984-01-31 | 1985-08-22 | Mitsubishi Heavy Ind Ltd | Two-way current control amplifier |
| US6114872A (en) * | 1996-05-31 | 2000-09-05 | Nippon Steel Corporation | Differential input circuit |
| US6121798A (en) * | 1998-10-05 | 2000-09-19 | Analog Devices, Inc. | High-speed comparator with improved latch accuracy |
| CN106020315A (en) * | 2015-03-26 | 2016-10-12 | 拉碧斯半导体株式会社 | Semiconductor device |
| CN108880488A (en) * | 2018-06-29 | 2018-11-23 | 思瑞浦微电子科技（苏州）股份有限公司 | The protection circuit of differential pair tube |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2023198037A1 (en) * | 2022-04-12 | 2023-10-19 | 圣邦微电子（北京）股份有限公司 | High-voltage input stage circuit without bias current |
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Application publication date: 20210521 |