CN216313052U - Operational amplification circuit - Google Patents
Operational amplification circuit Download PDFInfo
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- CN216313052U CN216313052U CN202123105164.5U CN202123105164U CN216313052U CN 216313052 U CN216313052 U CN 216313052U CN 202123105164 U CN202123105164 U CN 202123105164U CN 216313052 U CN216313052 U CN 216313052U
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Abstract
The utility model discloses an operational amplifier circuit, which relates to the technical field of circuits and comprises a P-type MOS tube MP1, a P-type MOS tube MP2, a P-type MOS tube MP4, a P-type MOS tube MP5, a P-type MOS tube MP6, an N-type MOS tube MN1, an N-type MOS tube MN2, an N-type MOS tube MN3, an N-type MOS tube MN4, an N-type MOS tube MN5, a resistor R1 and a capacitor C1.
Description
Technical Field
The utility model relates to the technical field of circuits, in particular to an operational amplifier circuit.
Background
Current sensing technology is widely used in various areas of modern industry, such as power management systems, over-current protection circuits, programmable current sources, linear and switched mode power supplies, and battery chargers. Common current detection modes include a series resistor, a power tube on-resistance, a power tube mirror copy and the like.
The series resistor causes power loss, for a series resistor detection circuit, the resistance value deviation of a resistor to be detected in an actual circuit is usually 20%, and the output power changes +/-0.2 mW if 1 kilohm resistor flows 1mA current, but the detection precision is higher; the conducting resistance of the power tube can perform overcurrent protection, but the conducting resistance is greatly influenced by factors such as process, temperature, power supply and the like, and is difficult to apply to high-precision current detection; the current of the detection tube of the power tube mirror image copy is small, the power consumption is reduced, but the detection precision is not high. The methods have defects in power consumption, speed and precision, and a series resistance detection circuit is selected for high-precision requirements.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the technical problem of providing an operational amplifier circuit aiming at the defects of the background technology, the circuit structure is simple, the loop gain can be improved by using two-stage operational amplifier, the miller capacitor is added, and the stability of the circuit can be improved by using the miller resistor.
The utility model adopts the following technical scheme for solving the technical problems:
an operational amplifier circuit comprises a P-type MOS tube MP1, a P-type MOS tube MP2, a P-type MOS tube MP4, a P-type MOS tube MP5, a P-type MOS tube MP6, an N-type MOS tube MN1, an N-type MOS tube MN2, an N-type MOS tube MN3, an N-type MOS tube MN4, an N-type MOS tube MN5, a resistor R1, a capacitor C1, a VDD voltage end, a VB voltage end, a VBIAS voltage end, a V1 voltage end, a V2 voltage end and a VOUT output end;
wherein, the VBIAS voltage end is connected with the grid electrode of the N-type MOS tube MN1, the source electrode of the N-type MOS tube MN1 is respectively connected with the source electrode of the N-type MOS tube MN3, the source electrode of the N-type MOS tube MN4 and the source electrode of the N-type MOS tube MN5 and grounded, the drain electrode of the N-type MOS tube MN1 is connected with the source electrode of the N-type MOS tube MN2, the grid electrode of the N-type MOS tube MN2 is connected with the VB voltage end, the drain electrode of the N-type MOS tube MN2 is respectively connected with the source electrode of the P-type MOS tube MP1, the drain electrode of the P-type MOS tube MP1, the grid electrode of the P-type MOS tube MP1, the grid electrode of the P-type MOS tube 2, the grid electrode of the P-type MOS tube MP6, the VDD voltage end, the source electrode of the P-type MOS tube MP2 and the source electrode of the P-type MOS tube MP6, the drain electrode of the P-type MOS tube MP tube 2 is respectively connected with the source electrode of the P-type MOS tube MP4, the source electrode of the P-type MOS tube MP5, the drain electrode of the P-type MOS tube MP tube MN 53 and the drain electrode of the P-type MOS tube MN tube 368658, the drain electrode of the N-type MOS transistor MN4 is respectively connected with the drain electrode of the P-type MOS transistor MP5, one end of the resistor R1 and the gate electrode of the N-type MOS transistor MN5, the gate electrode of the P-type MOS transistor MP5 is connected with the voltage end of V2, the other end of the resistor R1 is connected with one end of the capacitor C1, and the other end of the capacitor C1 is respectively connected with the drain electrode of the P-type MOS transistor MP6, the output end VOUT and the drain electrode of the N-type MOS transistor MN 5.
As a further preferable mode of the operational amplifier circuit of the present invention, the VB voltage terminal and the VBIAS voltage terminal are bias voltages.
In a further preferred embodiment of the operational amplifier circuit of the present invention, the capacitor C1 is a miller capacitor.
In a further preferred embodiment of the operational amplifier circuit of the present invention, the resistor R1 is a miller resistor.
Compared with the prior art, the utility model adopting the technical scheme has the following technical effects:
the utility model relates to an operational amplifier circuit, which comprises a P-type MOS tube MP1, a P-type MOS tube MP2, a P-type MOS tube MP4, a P-type MOS tube MP5, a P-type MOS tube MP6, an N-type MOS tube MN1, an N-type MOS tube MN2, an N-type MOS tube MN3, an N-type MOS tube MN4, an N-type MOS tube MN5, a resistor R1 and a capacitor C1.
Drawings
Fig. 1 is a circuit diagram of an operational amplifier circuit according to the present invention.
Detailed Description
The technical scheme of the utility model is further explained in detail by combining the attached drawings:
the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An operational amplifier circuit comprises a P-type MOS tube MP1, a P-type MOS tube MP2, a P-type MOS tube MP4, a P-type MOS tube MP5, a P-type MOS tube MP6, an N-type MOS tube MN1, an N-type MOS tube MN2, an N-type MOS tube MN3, an N-type MOS tube MN4, an N-type MOS tube MN5, a resistor R1, a capacitor C1, a VDD voltage end, a VB voltage end, a VBIAS voltage end, a V1 voltage end, a V2 voltage end and a VOUT output end;
wherein, the VBIAS voltage end is connected with the grid electrode of the N-type MOS tube MN1, the source electrode of the N-type MOS tube MN1 is respectively connected with the source electrode of the N-type MOS tube MN3, the source electrode of the N-type MOS tube MN4 and the source electrode of the N-type MOS tube MN5 and grounded, the drain electrode of the N-type MOS tube MN1 is connected with the source electrode of the N-type MOS tube MN2, the grid electrode of the N-type MOS tube MN2 is connected with the VB voltage end, the drain electrode of the N-type MOS tube MN2 is respectively connected with the source electrode of the P-type MOS tube MP1, the drain electrode of the P-type MOS tube MP1, the grid electrode of the P-type MOS tube MP1, the grid electrode of the P-type MOS tube 2, the grid electrode of the P-type MOS tube MP6, the VDD voltage end, the source electrode of the P-type MOS tube MP2 and the source electrode of the P-type MOS tube MP6, the drain electrode of the P-type MOS tube MP tube 2 is respectively connected with the source electrode of the P-type MOS tube MP4, the source electrode of the P-type MOS tube MP5, the drain electrode of the P-type MOS tube MP tube MN 53 and the drain electrode of the P-type MOS tube MN tube 368658, the drain electrode of the N-type MOS transistor MN4 is respectively connected with the drain electrode of the P-type MOS transistor MP5, one end of the resistor R1 and the gate electrode of the N-type MOS transistor MN5, the gate electrode of the P-type MOS transistor MP5 is connected with the voltage end of V2, the other end of the resistor R1 is connected with one end of the capacitor C1, and the other end of the capacitor C1 is respectively connected with the drain electrode of the P-type MOS transistor MP6, the output end VOUT and the drain electrode of the N-type MOS transistor MN 5.
The circuit structure is a single-end output two-stage operational amplifier, the first stage is a traditional five-transistor OTA structure, the input is a differential pair transistor P type MOS transistor MP4 and a P type MOS transistor MP5, the load is a current mirror N type MOS transistor MN3 and an N type MOS transistor MN4, the proportion is 1:1, high gain is provided, and differential input voltage is converted into current; the second stage is a transimpedance amplifier, a simple common source, to provide a high output swing and convert the first stage output current to an output voltage.
The VB voltage end and the VBIAS voltage end are bias voltages, a bias circuit composed of an N-type MOS tube MN1, an N-type MOS tube MN2 and a P-type MOS tube MP1 is powered on, the bias circuit supplies current to the P-type MOS tube MP2, the capacitor C1 is a Miller capacitor, and the resistor R1 is a Miller resistor, so that the influence of a zero point is eliminated, and the stability of the circuit is improved.
The circuit is simple in structure, loop gain can be improved by using two-stage operational amplifiers, and stability of the circuit can be improved by adding the Miller capacitor and the Miller resistor.
While certain exemplary embodiments of the present invention have been described above by way of illustration only, it will be apparent to those of ordinary skill in the art that the described embodiments may be modified in various different ways without departing from the spirit and scope of the utility model. Accordingly, the drawings and description are illustrative in nature and should not be construed as limiting the scope of the utility model.
Claims (4)
1. An operational amplifier circuit, comprising: the high-voltage power supply comprises a P-type MOS tube MP1, a P-type MOS tube MP2, a P-type MOS tube MP4, a P-type MOS tube MP5, a P-type MOS tube MP6, an N-type MOS tube MN1, an N-type MOS tube MN2, an N-type MOS tube MN3, an N-type MOS tube MN4, an N-type MOS tube MN5, a resistor R1, a capacitor C1, a VDD voltage end, a VB voltage end, a VBIAS voltage end, a V1 voltage end, a V2 voltage end and a VOUT output end;
wherein, the VBIAS voltage end is connected with the grid electrode of the N-type MOS tube MN1, the source electrode of the N-type MOS tube MN1 is respectively connected with the source electrode of the N-type MOS tube MN3, the source electrode of the N-type MOS tube MN4 and the source electrode of the N-type MOS tube MN5 and grounded, the drain electrode of the N-type MOS tube MN1 is connected with the source electrode of the N-type MOS tube MN2, the grid electrode of the N-type MOS tube MN2 is connected with the VB voltage end, the drain electrode of the N-type MOS tube MN2 is respectively connected with the source electrode of the P-type MOS tube MP1, the drain electrode of the P-type MOS tube MP1, the grid electrode of the P-type MOS tube MP1, the grid electrode of the P-type MOS tube 2, the grid electrode of the P-type MOS tube MP6, the VDD voltage end, the source electrode of the P-type MOS tube MP2 and the source electrode of the P-type MOS tube MP6, the drain electrode of the P-type MOS tube MP tube 2 is respectively connected with the source electrode of the P-type MOS tube MP4, the source electrode of the P-type MOS tube MP5, the drain electrode of the P-type MOS tube MP tube MN 53 and the drain electrode of the P-type MOS tube MN tube 368658, the drain electrode of the N-type MOS transistor MN4 is respectively connected with the drain electrode of the P-type MOS transistor MP5, one end of the resistor R1 and the gate electrode of the N-type MOS transistor MN5, the gate electrode of the P-type MOS transistor MP5 is connected with the voltage end of V2, the other end of the resistor R1 is connected with one end of the capacitor C1, and the other end of the capacitor C1 is respectively connected with the drain electrode of the P-type MOS transistor MP6, the output end VOUT and the drain electrode of the N-type MOS transistor MN 5.
2. The operational amplifier circuit according to claim 1, wherein: and the VB voltage end and the VBIAS voltage end are bias voltages.
3. The operational amplifier circuit according to claim 1, wherein: the capacitor C1 is a miller capacitor.
4. The operational amplifier circuit according to claim 1, wherein: the resistor R1 is a miller resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123105164.5U CN216313052U (en) | 2021-12-12 | 2021-12-12 | Operational amplification circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202123105164.5U CN216313052U (en) | 2021-12-12 | 2021-12-12 | Operational amplification circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN216313052U true CN216313052U (en) | 2022-04-15 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202123105164.5U Active CN216313052U (en) | 2021-12-12 | 2021-12-12 | Operational amplification circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN216313052U (en) |
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2021
- 2021-12-12 CN CN202123105164.5U patent/CN216313052U/en active Active
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20230630 Address after: 710025 Room 208, Building 1, No. 599, Fangyuan Third Road, Xi'an Modern Textile Industrial Park, Baqiao District, Xi'an, Shaanxi Patentee after: Xi'an Qiushiyuan Electronic Technology Co.,Ltd. Address before: 510000 Room 502, building 32, poly cotton garden, Jiangyan South 1st Street, Jiangyan Road, Haizhu District, Guangzhou City, Guangdong Province Patentee before: Wen Meiai |
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| TR01 | Transfer of patent right |