CN107765751B - Common mode feedback circuit and signal processing circuit - Google Patents
Common mode feedback circuit and signal processing circuit Download PDFInfo
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- CN107765751B CN107765751B CN201711225331.5A CN201711225331A CN107765751B CN 107765751 B CN107765751 B CN 107765751B CN 201711225331 A CN201711225331 A CN 201711225331A CN 107765751 B CN107765751 B CN 107765751B
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Abstract
The invention discloses a common mode feedback circuit and a signal processing circuit, and relates to the technical field of integrated circuits. The common mode feedback circuit comprises a current source sub-circuit which is connected with a power supply and provides a bias current source for the common mode feedback circuit, a comparison sub-circuit which is connected with a reference voltage and a common mode output voltage of the fully differential operational amplifier circuit, and a load sub-circuit which is connected with the comparison sub-circuit; the current source sub-circuit is connected with the comparison sub-circuit, and the comparison sub-circuit compares the reference voltage with the common mode output voltage and outputs a feedback voltage to adjust and stabilize the voltage of the fully differential operational amplifier circuit. According to the technical scheme, the comparison sub-circuit in the common mode feedback circuit is used for comparing the reference voltage with the common mode output voltage, and outputting the feedback voltage to the fully differential operational amplifier circuit to adjust the tail current to match the load current, so that the common mode output voltage can be stabilized, and a wider swing and a higher gain are provided.
Description
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a common mode feedback circuit and a signal processing circuit.
Background
With the development of analog integrated circuit technology, high-speed and high-precision operational amplifiers are widely used. The fully differential operational amplifier has great advantages over single-ended output operational amplifiers in terms of output swing, output dynamic range, power supply rejection ratio (Power Supply Rejection Ratio, PSRR), etc. However, the full differential operational amplifier has the problem of unstable output common mode level, and negative feedback of differential signals can not stabilize a direct current working point. Therefore, a Common-mode feedback (CMFB) circuit needs to be designed to ensure that the operational amplifier works normally, so that the output swing of the operational amplifier is improved while the operational amplifier is at the direct-current working point of the stabilizing circuit.
Disclosure of Invention
The invention mainly aims to provide a common mode feedback circuit and a signal processing circuit, which aim to enable an operational amplifier to improve the output swing while stabilizing a direct current working point of a circuit.
In order to achieve the above object, the present invention provides a common mode feedback circuit, including a current source sub-circuit connected to a power supply and providing a bias current source for the common mode feedback circuit, a comparison sub-circuit connected to a reference voltage and a common mode output voltage of a fully differential operational amplifier circuit, and a load sub-circuit connected to the comparison sub-circuit; the current source sub-circuit is connected with the comparison sub-circuit, and the comparison sub-circuit compares the reference voltage with the common mode output voltage and outputs a feedback voltage to adjust and stabilize the voltage of the fully differential operational amplifier circuit.
Preferably, the current source sub-circuit comprises a first field effect transistor and a second field effect transistor, wherein sources of the first field effect transistor and the second field effect transistor are both connected with a power supply, and gates of the first field effect transistor and the second field effect transistor are both connected with a first bias voltage; the drain electrode of the first field effect transistor is connected with the source electrodes of the third field effect transistor and the fourth field effect transistor in the comparison sub-circuit, and the drain electrode of the second field effect transistor is connected with the source electrodes of the fifth field effect transistor and the sixth field effect transistor in the comparison sub-circuit.
Preferably, the gate of the third field effect transistor is connected to the first common mode output voltage, and the drain is connected to the load sub-circuit; the grid electrode of the fourth field effect tube and the grid electrode of the fifth field effect tube are connected to the reference voltage, and the drain electrodes of the fourth field effect tube and the fifth field effect tube are connected to the load sub-circuit; and the drain electrode of the sixth field effect transistor is connected with the load sub-circuit, and the grid electrode of the sixth field effect transistor is connected with the second common mode output voltage.
Preferably, the load sub-circuit is connected to a load of the common mode feedback circuit and comprises a seventh field effect transistor and an eighth field effect transistor; the drain electrode and the grid electrode of the seventh field effect transistor are connected with each other, and are connected with the drain electrodes of the third field effect transistor and the sixth field effect transistor at the same time, and feedback voltage is output to the fully differential operational amplifier circuit; the grid electrode and the drain electrode of the eighth field effect transistor are connected with each other and are connected with the drain electrodes of the fourth field effect transistor and the fifth field effect transistor; and the sources of the seventh field effect transistor and the eighth field effect transistor are grounded.
The invention also provides a signal processing circuit, which comprises a fully differential operational amplifier circuit and the common mode feedback circuit, wherein the fully differential operational amplifier circuit comprises a first-stage sub-circuit, a second-stage sub-circuit connected with the first-stage sub-circuit through a first miller compensation circuit, and a mirror image sub-circuit mirrored with the first-stage sub-circuit, the first miller compensation circuit and the second-stage sub-circuit;
the first stage sub-circuit is connected to the feedback voltage output end of the common mode feedback circuit, and the second stage sub-circuit is connected to the comparison sub-circuit and is used for receiving the first common mode output voltage output by the common mode feedback circuit.
Preferably, the first stage sub-circuit comprises a ninth field effect transistor, a tenth field effect transistor, an eleventh field effect transistor and a twelfth field effect transistor which are sequentially connected, wherein the ninth field effect transistor is connected with a power supply, and the twelfth field effect transistor is grounded;
the source electrode of the ninth field effect transistor is connected with a power supply, and the drain electrode of the ninth field effect transistor is connected with the source electrode of the tenth field effect transistor; the drain electrode of the tenth field effect transistor is connected with the source electrode of the eleventh field effect transistor; the source electrode of the twelfth field effect transistor is grounded, the grid electrode is connected with the comparison subcircuit, and the drain electrode is connected with the drain electrode of the eleventh field effect transistor;
the first stage subcircuit further comprises a thirteenth field effect transistor, a fourteenth field effect transistor, a fifteenth field effect transistor and a sixteenth field effect transistor; the source electrode of the thirteenth field effect transistor is connected with a power supply, the grid electrode of the thirteenth field effect transistor is connected with a first bias voltage, and the drain electrode of the thirteenth field effect transistor is connected with the source electrode of the fourteenth field effect transistor; the grid electrode of the fourteenth field effect transistor is connected with a second bias voltage, and the drain electrode of the fourteenth field effect transistor is respectively connected with the drain electrode of the fifteenth field effect transistor, the first miller compensation circuit and the second-stage sub-circuit; the grid electrode of the fifteenth field effect transistor is connected with a third bias voltage, the drain electrode of the fifteenth field effect transistor is respectively connected with the drain electrode of the fourteenth field effect transistor, the first miller compensation circuit and the second-stage subcircuit, and the source electrode of the fifteenth field effect transistor is respectively connected with the drain electrode of the eleventh field effect transistor, the drain electrode of the twelfth field effect transistor and the drain electrode of the sixteenth field effect transistor; the grid electrode of the sixteenth field effect transistor is connected to the fourth bias voltage, and the source electrode of the sixteenth field effect transistor is grounded.
Preferably, the second stage sub-circuit comprises a seventeenth field effect transistor and an eighteenth field effect transistor which are connected in sequence; the source electrode of the seventeenth field effect transistor is connected with a power supply, and the grid electrode of the seventeenth field effect transistor is connected with the drain electrode of the fourteenth field effect transistor and the drain electrode of the fifteenth field effect transistor; the grid electrode of the eighteenth field effect transistor is connected with the fourth bias voltage, and the source electrode is grounded;
the drain electrode of the seventeenth field effect transistor and the drain electrode of the eighteenth field effect transistor are connected with each other and the comparison sub-circuit, so as to receive the first common-mode output voltage output by the common-mode feedback circuit.
Preferably, the first miller compensation circuit includes a first capacitor and a first resistor connected in series, one end of the first capacitor is connected to the drain of the fourteenth field effect transistor, the drain of the fifteenth field effect transistor and the gate of the seventeenth field effect transistor, the other end of the first capacitor is connected to one end of the first resistor, and the other end of the first resistor is connected to the drain of the seventeenth field effect transistor and the drain of the eighteenth field effect transistor.
According to the technical scheme, the comparison sub-circuit in the common mode feedback circuit is used for comparing the reference voltage with the common mode output voltage, and outputting the feedback voltage to the fully differential operational amplifier circuit to adjust the tail current to match the load current, so that the common mode output voltage can be stabilized, and a wider swing and a higher gain are provided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic circuit diagram of a common mode feedback circuit of the present invention;
FIG. 2 is a schematic circuit diagram of a fully differential operational amplifier circuit of the present invention;
fig. 3 is a schematic circuit diagram of a signal processing circuit according to the present invention.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Furthermore, the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
The invention provides a common mode feedback circuit and a signal processing circuit, which relate to the field of integrated circuits and are mainly used for stabilizing the current of a fully differential operational amplifier circuit in the signal processing circuit.
As shown in fig. 1, in the first embodiment of the present invention, the common mode feedback circuit includes a current source sub-circuit connected to a power supply AVDD and providing a bias current source for the common mode feedback circuit, a comparison sub-circuit connected to a reference voltage Vcm and a common mode output voltage of the fully differential operational amplifier circuit, and a load sub-circuit connected to the comparison sub-circuit; the current source sub-circuit is connected to the comparison sub-circuit, and the comparison sub-circuit compares the reference voltage Vcm with the common mode output voltage and outputs a feedback voltage Vcmfb to adjust and stabilize the voltage of the fully differential operational amplifier circuit.
Preferably, the current source sub-circuit includes a first field effect transistor M1 and a second field effect transistor M2, both of which have their sources connected to a power supply AVDD and their gates connected to a first bias voltage Vbp1; the drain electrode of the first field effect transistor M1 is connected with the source electrodes of the third field effect transistor M3 and the fourth field effect transistor M4 in the comparison sub-circuit, and the drain electrode of the second field effect transistor M2 is connected with the source electrodes of the fifth field effect transistor M5 and the sixth field effect transistor M6 in the comparison sub-circuit.
Preferably, the gate of the third fet M3 is connected to the first common mode output voltage OUTP, and the drain is connected to the load sub-circuit; the grid electrode of the fourth field effect transistor M4 and the grid electrode of the fifth field effect transistor M5 are connected to the reference voltage Vcm, and the drain electrodes of the fourth field effect transistor M4 and the fifth field effect transistor M5 are connected to the load sub-circuit; the drain electrode of the sixth field effect transistor M6 is connected to the load sub-circuit, and the gate electrode is connected to the second common mode output voltage OUTN.
Preferably, the load sub-circuit is connected to the load of the common mode feedback circuit and comprises a seventh field effect transistor M7 and an eighth field effect transistor M8; the drain electrode and the grid electrode of the seventh field effect transistor M7 are connected with each other, and are connected with the drain electrodes of the third field effect transistor M3 and the sixth field effect transistor M6 at the same time, and the feedback voltage Vcmfb is output to the fully differential operational amplifier circuit; the grid electrode and the drain electrode of the eighth field effect transistor M8 are connected with each other and are connected with the drain electrodes of the fourth field effect transistor M4 and the fifth field effect transistor M5; the sources of the seventh fet M7 and the eighth fet M8 are grounded AGND.
As shown in fig. 2 and 3, in a second embodiment of the present invention, the signal processing circuit includes a fully differential operational amplifier circuit and a common mode feedback circuit in the first embodiment, the fully differential operational amplifier circuit includes a first stage sub-circuit, a second stage sub-circuit connected to the first stage sub-circuit through a first miller (miller) compensation circuit, and a mirror sub-circuit mirror-imaged with the first stage sub-circuit, the first miller compensation circuit, and the second stage sub-circuit; the first stage sub-circuit is connected to the feedback voltage Vcmfb output end of the common mode feedback circuit, and the second stage sub-circuit is connected to the comparison sub-circuit and is used for receiving the first common mode output voltage OUTP output by the common mode feedback circuit.
Preferably, the first stage sub-circuit includes a ninth field effect transistor M9, a tenth field effect transistor M10, an eleventh field effect transistor M11, and a twelfth field effect transistor M12 that are sequentially connected, where the ninth field effect transistor M9 is connected to a power supply AVDD, and the twelfth field effect transistor M12 is grounded AGND;
the source electrode of the ninth field effect transistor M9 is connected with a power supply AVDD, and the drain electrode of the ninth field effect transistor M9 is connected with the source electrode of the tenth field effect transistor M10; the drain electrode of the tenth field effect transistor M10 is connected with the source electrode of the eleventh field effect transistor M11; the source electrode of the twelfth field effect transistor M12 is grounded AGND, the grid electrode is connected with the comparison subcircuit, and the drain electrode is connected with the drain electrode of the eleventh field effect transistor M11;
the first stage subcircuit further comprises a thirteenth field effect transistor M13, a fourteenth field effect transistor M14, a fifteenth field effect transistor M15 and a sixteenth field effect transistor M16; the source electrode of the thirteenth field effect transistor M13 is connected with the power supply AVDD, the grid electrode is connected with the first bias voltage Vbp1, and the drain electrode is connected with the source electrode of the fourteenth field effect transistor M14; the grid electrode of the fourteenth field effect transistor M14 is connected with a second bias voltage Vbn2, and the drain electrode of the fourteenth field effect transistor M15, the first miller compensation circuit and the second-stage sub-circuit are respectively connected with the drain electrode of the fifteenth field effect transistor M; the gate of the fifteenth fet M15 is connected to the third bias voltage Vbn1, the drain is connected to the drain of the fourteenth fet M14, the first miller compensation circuit and the second stage sub-circuit, and the source is connected to the drain of the eleventh fet M11, the drain of the twelfth fet M12 and the drain of the sixteenth fet M16, respectively; the sixteenth fet M16 has a gate connected to the fourth bias voltage Vbn2 and a source grounded AGND.
Preferably, the second stage sub-circuit comprises a seventeenth field effect transistor M17 and an eighteenth field effect transistor M18 which are connected in sequence; the source electrode of the seventeenth field effect transistor M17 is connected with a power supply AVDD, and the grid electrode of the seventeenth field effect transistor M17 is connected with the drain electrode of the fourteenth field effect transistor M14 and the drain electrode of the fifteenth field effect transistor M15; the gate of the eighteenth field effect transistor M18 is connected to the fourth bias voltage Vbn2, and the source is grounded AGND;
the drain electrode of the seventeenth fet M17 and the drain electrode of the eighteenth fet M18 are connected to each other and to the comparing sub-circuit, so as to receive the first common-mode output voltage OUTP output by the common-mode feedback circuit.
Preferably, the first miller compensation circuit includes a first capacitor C1 and a first resistor R1 connected in series, one end of the first capacitor C1 is connected to the drain of the fourteenth fet M14, the drain of the fifteenth fet M15, and the gate of the seventeenth fet M17, the other end of the first capacitor C1 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to the drain of the seventeenth fet M17 and the drain of the eighteenth fet M18.
The mirror sub-circuit that mirrors the first stage sub-circuit, the first miller compensation circuit, and the second stage sub-circuit includes: nineteenth field effect transistor M19, twentieth field effect transistor M20, twenty-first field effect transistor M21, twenty-first field effect transistor M22, twenty-third field effect transistor M23, twenty-fourth field effect transistor M24, twenty-fifth field effect transistor M25, twenty-first field effect transistor M26, and a second miller compensation circuit, the second miller compensation circuit including a second resistor R2 and a second capacitor C2.
The source electrode of the nineteenth field effect transistor M19 is connected to the power supply AVDD, the grid electrode is respectively connected to the grid electrode of the ninth field effect transistor M9 and the first bias voltage Vbp1, and the drain electrode is connected to the source electrode of the twentieth field effect transistor M20; the grid electrode of the twentieth field effect transistor M20 is respectively connected with the grid electrode of the tenth field effect transistor M10 and the second bias voltage Vbn2, and the drain electrode is connected with the drain electrode of the twenty-first field effect transistor M21; the grid electrode of the twenty-first field effect tube M21 is connected with the third bias voltage Vbn1, and the source electrode is respectively connected with the drain electrode of the twenty-second field effect tube M22, the drain electrode of the twenty-third field effect tube M23 and the drain electrode of the twenty-fourth field effect tube M24; the source electrode of the twenty-second field effect transistor M22 is grounded AGND, and the grid electrode is connected to the fourth bias voltage Vbn2; the source electrode of the twenty-third field effect transistor M23 is connected with the drain electrode of the tenth field effect transistor M10 and the source electrode of the eleventh field effect transistor M11; the source electrode of the twenty-fourth field effect tube M24 is grounded AGND, the grid electrode of the twenty-fourth field effect tube M24 and the grid electrode of the twelfth field effect tube M12 are commonly connected to the feedback voltage Vcmfb output by the common mode feedback circuit, and the feedback voltage Vcmfb output by the common mode feedback circuit can adjust the twelfth field effect tube M12 and the twenty-fourth field effect tube M24 of the tail current tube to be matched with the change of load current, so that the common mode output voltage is stabilized, and the normal operation of the operational amplifier is ensured.
The source electrode of the twenty-fifth field effect transistor M25 is connected with the power supply AVDD, and the grid electrode is connected with the drain electrode of the twenty-first field effect transistor M21 and the drain electrode of the twenty-fifth field effect transistor M20; the twenty-sixth field effect transistor M26 has a source grounded AGND and a gate connected to the fourth bias voltage Vbn2. The drain electrode of the twenty-fifth field effect transistor M25 and the drain electrode of the twenty-sixth field effect transistor M26 are connected to each other and to the gate electrode of the sixth field effect transistor M6, so as to receive the second common mode output voltage OUTN output by the common mode feedback circuit.
One end of a second capacitor C2 of the second Miller compensation circuit is connected to the drain electrode of the twentieth field effect transistor M20, the drain electrode of the twenty-first field effect transistor M21 and the grid electrode of the twenty-fifth field effect transistor M25, the other end of the second capacitor C2 is connected to one end of a second resistor R2, and the other end of the second resistor R2 is connected to a second common mode output voltage OUTN end.
In the circuit, a first bias voltage Vbp1 provides bias voltages for a nineteenth field effect transistor M19, a ninth field effect transistor M9, a thirteenth field effect transistor M13, a first field effect transistor M1 and a second field effect transistor M2; the second bias voltage Vbn2 provides bias voltages for the twentieth fet M20, the tenth fet M10, and the fourteenth fet M14; the third bias voltage Vbn1 provides bias voltages for the twenty-first fet M21 and the fifteenth fet M15; the fourth bias voltage Vbn2 provides bias voltages for a twenty-sixth fet M26, a twenty-second fet M22, a twenty-fourth fet M24, a twelfth fet M12, a sixteenth fet M16, an eighteenth fet M18, a seventh fet M7, and an eighth fet M8.
The circuit principle of the invention is as follows: the common mode feedback circuit comprises M1-M8; the fully differential operational amplifier circuit comprises M9-M26, and a first resistor R1, a first capacitor C1, a second resistor R2 and a second capacitor C2 form a Miller compensation circuit of the fully differential operational amplifier circuit, so that the stability of the fully differential operational amplifier circuit can be ensured; the common mode feedback circuit outputs a feedback voltage Vcmfb to adjust the twelfth field effect transistor M12 and the twenty-fourth field effect transistor M24 to match the change of the load current by detecting the first common mode output voltage OUTP and the second common mode output voltage OUTN and comparing the first common mode output voltage OUTP and the second common mode output voltage OUTN with the reference voltage Vcm, so that the common mode output voltage is stabilized, and the normal operation of the fully differential operational amplifier circuit is ensured.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the invention, and all equivalent structural changes made by the description of the present invention and the accompanying drawings or direct/indirect application in other related technical fields are included in the scope of the invention.
Claims (7)
1. The signal processing circuit is characterized by comprising a fully differential operational amplifier circuit and a common mode feedback circuit, wherein the fully differential operational amplifier circuit comprises a first-stage sub-circuit, a second-stage sub-circuit connected with the first-stage sub-circuit through a first miller compensation circuit, and a mirror image sub-circuit mirrored with the first-stage sub-circuit, the first miller compensation circuit and the second-stage sub-circuit;
the first-stage sub-circuit is connected with the feedback voltage output end of the common mode feedback circuit, and the second-stage sub-circuit is connected with the comparison sub-circuit and is used for receiving the first common mode output voltage output by the common mode feedback circuit;
the common mode feedback circuit comprises a current source sub-circuit which is connected with a power supply and provides a bias current source for the common mode feedback circuit, a comparison sub-circuit which is connected with a reference voltage and a common mode output voltage of the fully differential operational amplifier circuit, and a load sub-circuit which is connected with the comparison sub-circuit; the current source sub-circuit is connected with the comparison sub-circuit, and the comparison sub-circuit compares the reference voltage with the common mode output voltage and outputs a feedback voltage to adjust and stabilize the voltage of the fully differential operational amplifier circuit;
the first stage sub-circuit comprises a ninth field effect tube, a tenth field effect tube, an eleventh field effect tube and a twelfth field effect tube which are sequentially connected, wherein the ninth field effect tube is connected with a power supply, and the twelfth field effect tube is grounded;
the source electrode of the ninth field effect transistor is connected with a power supply, and the drain electrode of the ninth field effect transistor is connected with the source electrode of the tenth field effect transistor; the drain electrode of the tenth field effect transistor is connected with the source electrode of the eleventh field effect transistor; the source electrode of the twelfth field effect transistor is grounded, the grid electrode is connected with the comparison subcircuit, and the drain electrode is connected with the drain electrode of the eleventh field effect transistor;
the first stage subcircuit further comprises a thirteenth field effect transistor, a fourteenth field effect transistor, a fifteenth field effect transistor and a sixteenth field effect transistor; the source electrode of the thirteenth field effect transistor is connected with a power supply, the grid electrode of the thirteenth field effect transistor is connected with a first bias voltage, and the drain electrode of the thirteenth field effect transistor is connected with the source electrode of the fourteenth field effect transistor; the grid electrode of the fourteenth field effect transistor is connected with a second bias voltage, and the drain electrode of the fourteenth field effect transistor is respectively connected with the drain electrode of the fifteenth field effect transistor, the first miller compensation circuit and the second-stage sub-circuit; the grid electrode of the fifteenth field effect transistor is connected with a third bias voltage, the drain electrode of the fifteenth field effect transistor is respectively connected with the drain electrode of the fourteenth field effect transistor, the first miller compensation circuit and the second-stage subcircuit, and the source electrode of the fifteenth field effect transistor is respectively connected with the drain electrode of the eleventh field effect transistor, the drain electrode of the twelfth field effect transistor and the drain electrode of the sixteenth field effect transistor; the grid electrode of the sixteenth field effect transistor is connected with the fourth bias voltage, and the source electrode of the sixteenth field effect transistor is grounded;
the fully differential operational amplifier circuit further comprises a nineteenth field effect transistor, a twentieth field effect transistor, a twenty-first field effect transistor, a twenty-second field effect transistor, a twenty-third field effect transistor, a twenty-fourth field effect transistor, a twenty-fifth field effect transistor, a twenty-sixth field effect transistor and a second miller compensation circuit;
the source electrode of the nineteenth field effect transistor is connected with a power supply, the grid electrode of the nineteenth field effect transistor is respectively connected with the grid electrode of the ninth field effect transistor and the first bias voltage, and the drain electrode of the nineteenth field effect transistor is connected with the source electrode of the twentieth field effect transistor; the grid electrode of the twentieth field effect tube is respectively connected with the grid electrode of the tenth field effect tube and the second bias voltage, and the drain electrode of the twentieth field effect tube is connected with the drain electrode of the twenty-first field effect tube; the grid electrode of the twenty-first field effect tube is connected with the third bias voltage, and the source electrode of the twenty-first field effect tube is respectively connected with the drain electrode of the twenty-second field effect tube, the drain electrode of the twenty-third field effect tube and the drain electrode of the twenty-fourth field effect tube; the source electrode of the twelfth field effect transistor is grounded, and the grid electrode is connected with the fourth bias voltage; the source electrode of the twenty-third field effect transistor is connected with the drain electrode of the tenth field effect transistor and the source electrode of the eleventh field effect transistor; the source electrode of the twenty-fourth field effect tube is grounded, and the grid electrode of the twenty-fourth field effect tube and the grid electrode of the twelfth field effect tube are commonly connected with the feedback voltage output by the common mode feedback circuit;
the source electrode of the twenty-fifth field effect transistor is connected with a power supply, and the grid electrode of the twenty-fifth field effect transistor is connected with the drain electrode of the twenty-first field effect transistor and the drain electrode of the twenty-first field effect transistor; the source electrode of the twenty-sixth field effect transistor is grounded, and the grid electrode is connected with the fourth bias voltage; the drain electrode of the twenty-fifth field effect transistor is connected with the drain electrode of the twenty-sixth field effect transistor and is connected with the grid electrode of the sixth field effect transistor, and the drain electrode of the twenty-fifth field effect transistor is used for receiving the second common mode output voltage output by the common mode feedback circuit.
2. The signal processing circuit of claim 1, wherein the second stage sub-circuit comprises a seventeenth field effect transistor and an eighteenth field effect transistor connected in sequence; the source electrode of the seventeenth field effect transistor is connected with a power supply, and the grid electrode of the seventeenth field effect transistor is connected with the drain electrode of the fourteenth field effect transistor and the drain electrode of the fifteenth field effect transistor; the grid electrode of the eighteenth field effect transistor is connected with the fourth bias voltage, and the source electrode is grounded;
the drain electrode of the seventeenth field effect transistor and the drain electrode of the eighteenth field effect transistor are connected with each other and the comparison sub-circuit, so as to receive the first common-mode output voltage output by the common-mode feedback circuit.
3. The signal processing circuit of claim 2, wherein the first miller compensation circuit comprises a first capacitor and a first resistor connected in series, one end of the first capacitor is connected to the drain of the fourteenth field effect transistor, the drain of the fifteenth field effect transistor and the gate of the seventeenth field effect transistor, respectively, the other end of the first capacitor is connected to one end of the first resistor, and the other end of the first resistor is connected to the drain of the seventeenth field effect transistor and the drain of the eighteenth field effect transistor.
4. The signal processing circuit of claim 1, wherein the current source subcircuit comprises a first field effect transistor and a second field effect transistor, both sources are connected to a power source, and gates are connected to a first bias voltage; the drain electrode of the first field effect transistor is connected with the source electrodes of the third field effect transistor and the fourth field effect transistor in the comparison sub-circuit, and the drain electrode of the second field effect transistor is connected with the source electrodes of the fifth field effect transistor and the sixth field effect transistor in the comparison sub-circuit.
5. The signal processing circuit of claim 4, wherein the third fet has a gate connected to a first common mode output voltage and a drain connected to the load sub-circuit; the grid electrode of the fourth field effect tube and the grid electrode of the fifth field effect tube are connected to the reference voltage, and the drain electrodes of the fourth field effect tube and the fifth field effect tube are connected to the load sub-circuit; and the drain electrode of the sixth field effect transistor is connected with the load sub-circuit, and the grid electrode of the sixth field effect transistor is connected with the second common mode output voltage.
6. The signal processing circuit of claim 5, wherein the load sub-circuit is coupled to a load and comprises a seventh field effect transistor and an eighth field effect transistor; the drain electrode and the grid electrode of the seventh field effect transistor are connected with each other, and are connected with the drain electrodes of the third field effect transistor and the sixth field effect transistor at the same time, and feedback voltage is output to the fully differential operational amplifier circuit; the grid electrode and the drain electrode of the eighth field effect transistor are connected with each other and are connected with the drain electrodes of the fourth field effect transistor and the fifth field effect transistor; and the sources of the seventh field effect transistor and the eighth field effect transistor are grounded.
7. The signal processing circuit of claim 1, wherein the second miller compensation circuit comprises a second capacitor and a second resistor, wherein one end of the second capacitor is connected to the drain of the twentieth field effect transistor, the drain of the twenty-first field effect transistor, and the gate of the twenty-fifth field effect transistor, the other end of the second capacitor is connected to one end of the second resistor, and the other end of the second resistor is connected to the second common mode output voltage terminal.
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| CN111446935B (en) * | 2020-05-20 | 2023-10-13 | 苏州纳芯微电子股份有限公司 | Differential signal amplifying circuit, digital isolator and digital receiver |
| CN114448367A (en) * | 2020-11-02 | 2022-05-06 | 圣邦微电子（北京）股份有限公司 | Common mode feedback circuit of fixed potential |
| CN114447898B (en) * | 2022-01-26 | 2023-05-26 | 苏州纳芯微电子股份有限公司 | Current limiting circuit and electric equipment with same |
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| CN201690419U (en) * | 2010-05-12 | 2010-12-29 | 四川和芯微电子股份有限公司 | Common mode feedback circuit |
| JP2013005149A (en) * | 2011-06-15 | 2013-01-07 | Semiconductor Components Industries Llc | Fully differential operational amplifier |
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| CN105846788B (en) * | 2016-03-25 | 2019-05-07 | 南京德睿智芯电子科技有限公司 | A kind of operational amplifier |
| CN207557802U (en) * | 2017-11-29 | 2018-06-29 | 成都锐成芯微科技股份有限公司 | Common mode feedback circuit and signal processing circuit |
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| CN1141698A (en) * | 1994-02-21 | 1997-01-29 | 艾利森电话股份有限公司 | Signal-receiving and signal-processing unit |
| CN103354443A (en) * | 2013-06-20 | 2013-10-16 | 华侨大学 | CTCMFB (continuous time common-mode feedback) circuit applied to high-speed fully differential operational amplifier |
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