JP2013005149A - Fully differential operational amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a fully differential operational amplifier that implements improved operational stability and thus a high speed operation.SOLUTION: A differential amplification section comprises a first differential amplification circuit 1 of a first stage and a second differential amplification circuit 2 of a second stage. A phase compensation circuit 5 is connected between differential input terminals and differential output terminals of the second differential amplification circuit 2. A first CMFB circuit 3 feedback-controls the first differential amplification circuit 1 such that a first common mode voltage VC1 of differential output voltages VP, VN of the first differential amplification circuit 1 of the first stage becomes a first reference voltage. A second CMFB circuit 4 feedback-controls the second differential amplification circuit 2 such that a second common mode voltage VC2 of differential output voltages VOUTP, VOUTN of the second differential amplification circuit 2 becomes a second reference voltage.

Description

  The present invention relates to a fully differential operational amplifier, and more particularly, to a multiple-stage fully differential operational amplifier having a common mode feedback circuit.

  In general, fully differential operational amplifiers have a pair of differential input terminals and a pair of differential output terminals, and have higher noise immunity and higher performance than single-ended output operational amplifiers that have only one output terminal. Is widely used in integrated circuits that require the above. FIG. 13 is a block diagram of a fully differential operational amplifier. The fully differential operational amplifier includes a first differential amplifier circuit 50, a second differential amplifier circuit 51, a common mode feedback circuit (hereinafter referred to as a CMFB circuit) 52, which form a two-stage differential amplifier. The phase compensation circuit 53 is included.

The CMFB circuit 52 is a common-mode voltage (center voltage) of the differential output voltages VOUTP and VOUTN.
Is a circuit for controlling the voltage to a predetermined reference voltage. The phase compensation circuit 53 is connected between the first differential amplifier circuit 50 and the second differential amplifier circuit 51 in order to prevent oscillation of the fully differential operational amplifier. The phase compensation circuit 53 includes phase compensation capacitors CCP and CCN, and as shown in the figure, zero point elimination resistors RZP and RZN for securing a sufficient phase margin are connected in series to the phase compensation capacitors CCP and CCN. Sometimes it is done.

  FIG. 14 is a specific circuit diagram of the fully differential operational amplifier of FIG. The P-channel MOS transistors M1, M2, and M5 and the N-channel MOS transistors M3 and M4 constitute the first differential amplifier circuit 50 in the first stage. The differential output voltages of the first differential amplifier circuit 50 are VP and VN.

  The P-channel MOS transistors M6 and M7 and the N-channel MOS transistors M8 and M9 constitute a second differential amplifier circuit 51 in the second stage. Between the first stage and the second stage, a phase compensation circuit 53 comprising zero point erasing resistors RZP and RZN and phase compensation capacitors CCP and CCN is connected.

  The bias circuit 54 includes a current mirror circuit including P-channel MOS transistors M51, M53, and M55 and N-channel MOS transistors M52, M54, and M56, and a resistor RB1, and when the power-down signal PWDB is at H level, The channel type MOS transistor M52 is turned on, and a bias voltage necessary for the operational amplifier operation is supplied to the P channel type MOS transistors M6 and M7 and the N channel type MOS transistors M3 and M4.

  In general, the two-stage operational amplifier as described above requires the phase compensation circuit 53 for preventing oscillation. However, the first stage can provide a high gain, and the second stage can provide a large amplitude. Can be provided. The two-stage operational amplifier is an effective circuit configuration when the required characteristics cannot be sufficiently satisfied with respect to the gain or output amplitude obtained by the one-stage operational amplifier, and is large in constructing an integrated circuit. It will be a merit.

  In the above-described fully differential operational amplifier, the differential output voltages VOUTP and VOUTN change according to the differential input voltages VINP and VINN input to the pair of differential input terminals of the first differential amplifier circuit 50, respectively. It has a configuration. The CMFB circuit 52 outputs the control voltage VBC so that the common-mode voltage VC of the output voltages VOUTP and VOUTN becomes the reference voltage COMVREF. The control voltage VBC is applied to the gate of a P-channel MOS transistor that is a constant current source of the first differential amplifier circuit 50.

  For example, when the common-mode voltage VC is higher than the reference voltage COMVREF, the control voltage VBC becomes low. When the control voltage VBC decreases, the drain current of the P-channel MOS transistor M5 increases, so that the differential output voltages VP and VN of the first differential amplifier circuit 50 in the first stage increase, and the second Since the drain currents of the N-channel MOS transistors M8 and M9 of the second differential amplifier circuit 51 in the stage are increased, the differential output voltages VOUTP and VOUTN are decreased, and the common-mode voltage VC is also decreased.

  Conversely, when the common-mode voltage VC is lower than the reference voltage COMVREF, the control voltage VBC becomes high. When the control voltage VBC increases, the drain current of the P-channel MOS transistor M5 decreases, so that the differential output voltages VP and VN of the first stage decrease, and accordingly, the N-channel MOS transistors M8, Since the drain current of M9 decreases, the differential output voltages VOUTP and VOUTN increase and the common mode voltage VC also increases.

  As described above, the fully differential operational amplifier controls the voltage VBC applied to the gate of the P-channel MOS transistor M5 so that the common-mode voltage VC of the differential output voltages VOUTP and VOUTN becomes the predetermined reference voltage COMVREF. Is controlled. This type of fully differential operational amplifier is described in Patent Documents 1 and 2.

JP 2002-280877 A JP 2004-297631 A

  In the above-described fully differential operational amplifier, there is only one CMFB circuit 52 for setting the common-mode voltage VC of the differential output voltages VOUTP and VOUTN to the predetermined reference voltage COMVREF. Since the CMFB loop of the CMFB circuit 52 is fed back via the first stage, the second stage, and the phase compensation circuit 53, the CMFB loop cannot sufficiently secure the phase margin and stabilizes the operational amplifier. There was a problem that it was difficult to operate.

  Further, if the frequency characteristic of the CMFB loop is reduced in order to ensure the phase margin of the CMFB control loop, the frequency characteristic of the operational amplifier itself may be reduced. In addition, for stable operation, the circuit scale may increase or the current consumption may increase.

The fully differential operational amplifier according to the present invention is configured such that a plurality of differential amplifier circuits each having a pair of differential input terminals and a pair of differential output terminals constitute a plurality of stages from the first stage to the final stage. A differential amplifying unit connected, and a phase compensation circuit (5) connected between a differential input terminal and a differential output terminal of the differential amplifier circuit (2) of the final stage;
The differential amplification so that the first common-mode voltage (VC1) of the pair of differential output voltages (VP, VN) of the first-stage differential amplification circuit (1) becomes the first reference voltage (VGS1). A first common mode feedback circuit (3) for feedback control of the circuit (1) and a second common-mode voltage (VOUTP, VOUTN) of a pair of differential output voltages (VOUTP, VOUTN) of the final stage differential amplifier circuit (2) And a second common mode feedback circuit (4) that feedback-controls the differential amplifier circuit (2) so that VC2) becomes the second reference voltage (COMVREF). is there.

  The fully differential operational amplifier according to the present invention has a configuration in which a common mode feedback circuit is provided at least in each of the first stage and the final stage, and the differential amplifier circuit in each stage is controlled independently. Therefore, the common mode feedback loop does not pass through the phase compensation circuit, so that the stability of the operation of the entire circuit is improved and high speed operation is possible.

  In addition, the common mode feedback circuit can be simplified and current consumption can be reduced. Therefore, while utilizing the high gain and large amplitude output characteristic of the differential operational amplifier having a plurality of stages, the stability of the circuit operation can be improved, high speed operation can be performed, and the power consumption can be reduced. Furthermore, since the settling time is shortened, this is a great advantage not only for continuous-time circuits but also for applications in discrete-time systems.

1 is a block diagram of a fully differential operational amplifier according to a first embodiment of the present invention. 1 is a detailed block diagram of a fully differential operational amplifier according to a first embodiment of the present invention. 1 is a circuit diagram of a fully differential operational amplifier according to a first embodiment of the present invention. It is a circuit diagram of a switched capacitor type common-mode voltage detection circuit. It is a wave form diagram of a clock used for a switched capacitor type common-mode voltage detection circuit. It is a figure explaining operation | movement of a switched capacitor type common-mode voltage detection circuit. FIG. 2 is a circuit diagram of a control voltage generation circuit in the first embodiment. It is a circuit diagram of a bias circuit. FIG. 5 is a circuit diagram of a fully differential operational amplifier according to a second embodiment. FIG. 6 is a circuit diagram of a control voltage generation circuit according to a second embodiment. It is a circuit diagram of the fully differential operational amplifier in the 3rd Embodiment of this invention. It is a circuit diagram of the switched capacitor integrator to which the fully differential operational amplifier of the present invention is applied. It is a block diagram of a fully differential operational amplifier of a conventional example. It is a circuit diagram of a fully differential operational amplifier of a conventional example.

<< First Embodiment >>
[overall structure]
FIG. 1 is a block diagram of a fully differential operational amplifier 100 according to this embodiment. The fully differential operational amplifier 100 includes a first differential amplifier circuit 1 and a second differential amplifier circuit 2 that form a two-stage differential amplifier section (portion surrounded by a broken line in FIG. 1), The common mode feedback circuit 3 or lower, the first CMFB circuit 3, the second common mode feedback circuit 4 (hereinafter referred to as the second CMFB circuit 4), and the phase compensation circuit 5 are configured.

  The first differential amplifier circuit 1 constitutes a first stage, and is differentially supplied from the pair of differential output terminals according to the differential input voltages VINP and VINN respectively input to the pair of differential input terminals. Output voltages VP and VN are output. The second differential amplifier circuit 2 constitutes a second stage, and the differential output voltages VP and VN of the first differential amplifier circuit 1 are input to a pair of differential input terminals, respectively, and a pair of differential outputs Differential output voltages VOUTP and VOUTN are output from the terminals, respectively.

  The first CMFB circuit 3 has a first difference so that the first common-mode voltage VC1 (intermediate voltage) of the differential output voltages VP and VN of the first differential amplifier circuit 1 becomes the first reference voltage. The dynamic amplification circuit 1 is feedback controlled. The second CMFB circuit 4 performs the second differential amplification so that the in-phase voltage VC2 (intermediate voltage) of the differential output voltages VOUTP and VOUTN of the second differential amplifier circuit 2 becomes the second reference voltage COMVREF. The circuit 2 is feedback controlled.

  The phase compensation circuit 5 is a circuit for preventing oscillation of the fully differential operational amplifier 100, and includes phase compensation capacitors CCP and CCN. The amplifier circuit 2 is connected. That is, the phase compensation capacitors CCP and CCN are respectively connected between the pair of differential input terminals and the pair of differential output terminals of the second differential amplifier circuit 2. In the phase compensation circuit 5, zero point elimination resistors RZP and RZN for ensuring a sufficient phase margin as shown in FIG. 13 may be connected in series to the phase compensation capacitors CCP and CCN.

  According to the fully differential operational amplifier 100 in the present embodiment, the first CMFB circuit 3 and the second CMFB circuit 4 are provided corresponding to the first stage and the second stage, and the first differential amplifier circuit 1 is provided. The second differential amplifier circuit 2 is controlled independently. For this reason, the common mode feedback loop does not pass through the phase compensation circuit 5, so that the stability of the entire circuit is improved and high speed operation is possible.

  In addition, the configuration of the first CMFB circuit 3 and the second CMFB circuit 4 can be simplified, and current consumption can be reduced. Therefore, while taking advantage of the high gain and large amplitude output characteristic of the differential operational amplifier having two stages, it is possible to improve the stability of the circuit operation, enable high-speed operation, and reduce power consumption. Furthermore, since the settling time is shortened, this is a great advantage not only for continuous-time circuits but also for applications in discrete-time systems.

  FIG. 2 is a more detailed block diagram of the fully differential operational amplifier 100. The second CMFB circuit 4 includes a common-mode voltage detection circuit 4A that detects a common-mode voltage VC2 of the differential output voltages VOUTP and VOUTN of the second differential amplifier circuit 2, and control voltages VB4 and VB5 based on the common-mode voltage VC2. A control voltage generation circuit 4B for generating the first differential amplifier circuit 1, the second differential amplifier circuit 2, the first CMFB circuit 3, and the second CMFB circuit 4 for operating the bias voltage VB0, The bias circuit 6 generates VB1 and VB3.

  The first CMFB circuit 3 can be shared by a common circuit voltage detection circuit and a control voltage generation circuit. This is because, generally, an operational amplifier incorporated in an integrated circuit is used with feedback, so that the variation of the differential output voltages VP and VN of the first stage is relatively small depending on the gain of the second stage. .

[Configuration of Differential Amplifier and Common-Mode Voltage Detection Circuit 4A]
FIG. 3 is a specific circuit diagram of the differential amplification unit and the common-mode voltage detection circuit 4A of the fully differential operational amplifier 100 according to the present embodiment. The first differential amplifier circuit 1 in the first stage includes P-channel MOS transistors M1, M2, and M5 and N-channel MOS transistors M3 and M4.

  The P-channel MOS transistors M1 and M2 are differential input transistors and are connected in series to a P-channel MOS transistor M5, which is a constant current source transistor, and differential input voltages VINP and VINN are applied to the respective gates. . Bias voltage VB3 is applied to the gate of P-channel MOS transistor M5. N-channel MOS transistors M3 and M4 are connected in series to P-channel MOS transistors M1 and M2, respectively, and a bias voltage VB0 is applied to their interconnected gates. The power supply voltage VDD is applied to the source of the P-channel MOS transistor M5, and the ground voltage VSS is applied to the sources of the N-channel MOS transistors M3 and M4.

  A differential output voltage VP is output from a connection node between the P-channel MOS transistor M1 and the N-channel MOS transistor M3, and a differential output voltage VN is output from a connection node between the P-channel MOS transistor M2 and the N-channel MOS transistor M4. Is output.

  The second differential amplifier circuit 2 in the second stage is composed of P-channel MOS transistors M9, M10, M13, and M14 and N-channel MOS transistors M11, M12, M15, and M16 that are differential input transistors. Yes.

  The P-channel MOS transistors M9 and M13 form a current mirror, and the control voltage VB4 from the control voltage generation circuit 4B of the second CMFB circuit 4 is applied to their common gate. The P-channel MOS transistors M10 and M14 also form a current mirror, and the control voltage VB5 from the control voltage generation circuit 4B is applied to their common gate.

  The differential output voltage VP is applied to the gates of the N-channel MOS transistors M12 and M15, and the differential output voltage VN is applied to the gates of the N-channel MOS transistors M11 and M16. The power supply voltage VDD is applied to the sources of the P-channel MOS transistors M9, M10, M13, and M14, and the ground voltage VSS is applied to the sources of the channel-type MOS transistors M11, M12, M15, and M16.

  The differential output voltage VOUTP is output from the connection node between the P-channel MOS transistor M13 and the N-channel MOS transistor M15, and the differential output voltage VOUTN is output from the connection node between the P-channel MOS transistor M14 and the N-channel MOS transistor M16. Is output.

  Between the first differential amplifier circuit 1 of the first stage and the second differential amplifier circuit 2 of the second stage, phase compensation capacitors CCP and CCN of the phase compensation circuit 5 are connected. As described above, the zero point erasing resistors RZP and RZN may be connected in series with the phase compensation capacitors CCP and CCN, respectively.

  The first CMFB circuit 3 includes a P-channel MOS transistor M5 and N-channel MOS transistors M6, M7, and M8. N-channel MOS transistors M7 and M8 are connected in series to P-channel MOS transistor M5 via N-channel MOS transistor M6. The gate of the N-channel MOS transistor M7 is connected to the drain of the P-channel MOS transistor M1, and the gate of the N-channel MOS transistor M8 is connected to the drain of the P-channel MOS transistor M2. Bias voltage VB1 is applied to the gate of N-channel MOS transistor M6.

  As described above, the first CMFB circuit 3 combines the common-mode voltage detection circuit and the control voltage generation circuit. Further, the P-channel transistor M5 constituting the first stage constant current source is commonly used as a component of the first CMFB circuit 3.

  As described above, the first stage has a configuration in which the differential output voltages VP and VN change according to the differential input voltages VINP and VINN. The first CMFB circuit 3 passes through the N-channel MOS transistor M6 so that the first common-mode voltage (intermediate voltage) VC1 of the differential output voltages VP and VN of the first stage becomes the first reference voltage. Thus, the control current IBC1 flowing through the N-channel MOS transistors M7 and M8 is controlled.

  For example, the size of the first stage P-channel type MOS transistors M1 and M2, the size of the N-channel type MOS transistors M7 and M8 of the first CMFB circuit 3, and the size of the N-channel type MOS transistors M3 and M4 are equal and the same ON Suppose you have resistance. Also, assuming that the differential input voltages VINP and VINN are equal and have a predetermined operating voltage, the first common-mode voltage VC1 of the differential output voltages VP and VN of the first stage is a preset N-channel type. It becomes equal to the gate-source voltage VGS of the MOS transistors M7 and M8.

  For example, the first reference voltage at that time is VGS1, and the current flowing through the first CMFB circuit 3 is IBC1. When the first common-mode voltage VC1 of the differential output voltages VP and VN of the first stage is higher than the reference voltage VGS1, the control current IBC1 increases. When the control current IBC1 increases, the drain current of the P-channel MOS transistor M5 is constant, so that the drain currents of the P-channel MOS transistors M1 and M2, which are differential input transistors of the first stage, decrease, and the first stage The differential output voltages VP and VN are reduced, and the first common-mode voltage VC1 is also reduced.

  When the first common-mode voltage VC1 of the differential output voltages VP and VN of the first stage is lower than the first reference voltage VGS1, the control current IBC1 decreases. When the control current IBC1 decreases, the drain current of the P-channel MOS transistor M5 is constant, so that the drain currents of the first-stage P-channel MOS transistors M1 and M2 increase, and the first-stage differential outputs VP, VN increases and the first common mode voltage VC1 also increases.

  From another viewpoint, if the drain voltage of the P-channel MOS transistor M5 operating as a constant current source is VBC1, the first common-mode voltage VC1 of the differential output voltages VP and VN of the first stage is the first reference voltage VC1. When it is lower than the voltage VGS1, the drain voltage VBC1 of M5 becomes high. An increase in the drain voltage VBC1 is equivalent to an increase in the gate-source voltage of the P-channel MOS transistors M1 and M2, so that the drain currents of M1 and M2 increase, and the differential output voltage VP of the first stage increases. , VN are increased, and the first common-mode voltage VC1 is also increased.

  In addition, when the first common-mode voltage VC1 of the differential output voltages VP and VN of the first stage is higher than the first reference voltage VGS1, the drain voltage VBC1 of M5 becomes low. Lowering the drain voltage VBC1 is equivalent to lowering the gate-source voltages of the P-channel MOS transistors M1 and M2, so the drain currents of M1 and M2 are reduced, and the differential output voltage VP of the first stage is reduced. , VN become lower and the first common mode voltage VC1 becomes lower. Therefore, it can be said that the first CMFB circuit 3 includes an in-phase voltage detection circuit and a control voltage generation circuit.

  Even when the first common-mode voltage VC1 becomes extremely high or extremely low, current is supplied from the first CMFB circuit 3 to the first differential amplifier circuit 1 of the first stage, or the first Since the current can be absorbed from the first differential amplifier circuit 1 in one stage, abnormal operation can be prevented.

  In any case, the first CMFB circuit 3 is controlled so that the first common-mode voltage VC1 of the differential output voltages VP and VN of the first stage becomes a predetermined reference voltage VGS1. Since the output amplitude of the differential output voltages VP and VN of the first stage is relatively small depending on the gain of the second stage, the common-mode voltage detection circuit and the control power generation circuit can be used together, and the circuit scale is also small. it can. Accordingly, low current consumption and high-speed operation are possible, and the pole generated in the first CMFB circuit 3 has a sufficiently high frequency, so that the frequency characteristics and phase characteristics of the fully differential operational amplifier 100 as a whole are degraded. Stable operation can be realized without any problems.

  The P-channel MOS transistor M6 of the first CMFB circuit 3 is provided to limit the source-drain voltage of the P-channel MOS transistors M7 and M8. The P-channel MOS transistor M7, If the source-drain breakdown voltage of M8 is large, it may be omitted.

  In addition, the common-mode voltage detection circuit 4A that detects the second common-mode voltage VC2 of the differential output voltages VOUTP and VOUTN of the second differential amplification circuit 2 includes the second differential amplification circuit 2 as shown in FIG. The resistors RP and RN are connected in series between the pair of differential output terminals. A detection output of the second common-mode voltage VC2 (intermediate voltage) is obtained from the connection node of the resistors RP and RN. In order to stabilize the second common-mode voltage VC2, it is preferable to connect stabilization capacitors CP and CN in parallel with the resistors RP and RN, respectively.

  For example, if the resistance values of the resistors RP and RN are equal and the capacitance values of the stabilization capacitors CP and CN are also equal, the second common-mode voltage VC2 obtained from the connection node of the resistors RP and RN is the differential output voltage VOUTP, It becomes (VOUTP + VOUTN) / 2 which is exactly in the middle of VOUTN.

  The common-mode voltage detection circuit 4A can generate an equivalent resistance with a switched capacitor configuration instead of the resistors RP and RN. If the second common-mode voltage VC2 has a function to detect, the other circuit configuration May be used.

  FIG. 4 is a circuit diagram of a switched capacitor type common-mode voltage detection circuit 4A. The common-mode voltage detection circuit 4A includes a switching circuit including analog switches ASW1 to ASW8 formed of CMOS transfer gates, a first switching capacitor CP1, a second switching capacitor CN1, a first fixed capacitor CP2, and a second The fixed capacitor CN2 is included.

  The analog switches ASW1, ASW4, ASW6, ASW7 are connected in series between a pair of differential output terminals that output the differential output voltages VOUTN, VOUTP of the second differential amplifier 2 in this order, and the clocks CK1, CK1B Is turned on when CK1 is at the H level (VDD), and is turned off when CK1 is at the L level (VSS). The clock CK1B is an inverted clock of the clock CK1.

  On the other hand, the analog switches ASW2, ASW3, ASW5, and ASW8 are connected in series between a pair of differential output terminals that output the differential output voltages VOUTN and VOUTP in this order, and are on / off controlled by the clocks CK2 and CK2B. , CK2 is turned on when H level (VDD), and turned off when CK2 is L level (VSS). The clock CK2B is an inverted clock of the clock CK2. In this case, the clocks CK1 and CK2 are clocks that repeat H level and L level as shown in FIG.

  The first switching capacitor CP1 is connected between a connection node of the analog switches ASW1 and ASW2 and a connection node of the analog switches ASW7 and ASW8. On the other hand, the second switching capacitor CN1 is connected between the connection node of the analog switches ASW3 and ASW4 and the connection node of the analog switches ASW5 and ASW6. The first fixed capacitor CP2 and the second fixed capacitor CN2 are connected in series between a pair of differential amplification terminals that output the differential output voltages VOUTP and VOUTN.

  From the output terminal OUT drawn out by connecting the connection node of the analog switches ASW2 and ASW3, the connection node of the analog switches ASW6 and ASW7, and the connection node of the first fixed capacitor CP2 and the second fixed capacitor CN2 in common. The voltage VC2 is output.

  FIG. 6 is a diagram for explaining the operation of this switched capacitor type common-mode voltage detection circuit 4A. In the first mode (CK1 = H level, CK2 = L level), the analog switches ASW1, ASW4, ASW6, ASW7 are turned on, and the analog switches ASW2, ASW3, ASW5, ASW8 are turned off. The capacitor CP1 is connected between the differential output terminal that outputs the differential output voltage VOUTN and the output terminal OUT, and the second switching capacitor CN1 is the differential output terminal that outputs the differential output voltage VOUTP and the output terminal. Connected between OUT.

  On the other hand, in the second mode (CK1 = L level, CK2 = H level), on the contrary, the analog switches ASW1, ASW4, ASW6, ASW7 are turned off and the analog switches ASW2, ASW3, ASW5, ASW8 are turned on. The first switching capacitor CP1 is connected between the differential output terminal that outputs the differential output voltage VOUTP and the output terminal OUT, and the second switching capacitor CN1 is the difference that outputs the differential output voltage VOUTN. Connected between the dynamic output terminal and the output terminal OUT.

  By such a switching operation, an equivalent resistance is generated at the pair of differential output terminals that output the differential output voltages VOUTN and VOUTP. The first and second fixed capacitors CP2 and CN2 serve as stabilizing capacitors. The capacitance values of the first and second switching capacitors CP1 and CN1 are set to be equal, and the capacitance values of the first and second fixed capacitors CP2 and CN2 are set to be equal to each other to be obtained from the output terminal OUT. The common-mode voltage VC2 of 2 is (VOUTP + VOUTN) / 2, which is exactly between the differential output voltages VOUTP and VOUTN.

[Configuration of Control Voltage Generation Circuit 4B]
FIG. 7 is a specific circuit diagram of the control voltage generation circuit 4B of the fully differential operational amplifier 100 of the present embodiment. The control voltage generation circuit 4B includes P-channel MOS transistors M31 to M37 and N-channel MOS transistors M38 to M43.

  The P-channel MOS transistor M34 is a current source transistor, and the power supply voltage VDD is applied to the source thereof, and the bias voltage VB3 is applied to the gate thereof. P-channel MOS transistors M31 to M33 are differential input transistors and are connected in series to P-channel MOS transistor M34. The second common-mode voltage VC2 detected by the common-mode voltage detection circuit 4A is applied to the gate of M31, and a predetermined reference voltage COMVREF is applied to the gates of M32 and M33.

  P-channel MOS transistors M35 and M36 form a current mirror, and P-channel MOS transistors M35 and M37 also form a current mirror. N-channel MOS transistors M38 and M41 are connected in series between P-channel MOS transistor M35 and ground. The drain of the P-channel MOS transistor M31 is connected to the connection node of the N-channel MOS transistors M38 and M41.

  N-channel MOS transistors M39 and M42 are connected in series between the P-channel MOS transistor M36 and the ground. The drain of the P-channel MOS transistor M32 is connected to the connection node of the N-channel MOS transistors M39 and M42.

  The N-channel MOS transistors M40 and M43 are connected in series between the P-channel MOS transistor M37 and the ground. The drain of the P-channel MOS transistor M33 is connected to the connection node of the N-channel MOS transistors M40 and M43. A bias voltage VB1 is applied to each gate of the N-channel MOS transistors M38, M39, and M40. A bias voltage VB0 is applied to the gates of the N-channel MOS transistors M41, M42, and M43.

  The control voltage VB4 is output from the drain of the P-channel MOS transistor M36 of the control voltage generation circuit 4B, and the control voltage VB5 is output from the drain of the P-channel MOS transistor M37. The control voltage VB4 is applied to the gates of the P-channel MOS transistors M9 and M13 of the second differential amplifier circuit 2, and the control voltage VB5 is applied to the P-channel MOS transistors M10 and M10 of the second differential amplifier circuit 2. Applied to each gate of M14.

  Next, the operation of the control voltage generation circuit 4B will be described. For example, it is assumed that the size of the P-channel MOS transistor M31 is twice that of M32, and the sizes of M32 and M33 are equal. Further, it is assumed that the size of the P-channel MOS transistor M35 is twice that of M36, and the sizes of M36 and M37 are equal. Similarly, the size ratio of the N-channel MOS transistors M38, M39, and M40 is 2: 1: 1, and the size ratio of the N-channel MOS transistors M41, M42, and M43 is also 2: 1: 1. Thereby, the ON resistance of each transistor becomes this ratio.

  The drain current of the P-channel MOS transistor M35 is IBC20, the drain current of M36 is IBC21, and the drain current of M37 is IBC22. In addition, the sizes of the P-channel MOS transistors M9 and M10 and the sizes of M13 and M14 of the second differential amplifier circuit 2 in the second stage are equal, the sizes of the N-channel MOS transistors M11 and M12, and the sizes of M15 and M16. Are equal and have the same on-resistance.

  (A) When the second common-mode voltage VC2 of the differential output voltages VOUTP and VOUTN of the second stage is equal to the predetermined reference voltage COMVREF, the relationship of IBC20 = IBC21 + IBC22 is established, and the relationship of IBC21 = IBC22 is established.

  The gate voltages of the second stage P-channel MOS transistors M9 and M13 are VB4, the gate voltages of the P-channel MOS transistors M10 and M14 are VB5, and the relationship of VB4 = VB5 is established. At this time, no current is exchanged between the control voltage generation circuit 4B and the second differential amplifier circuit 2.

  (B) When the second common-mode voltage VC2 of the differential output voltages VOUTP and VOUTN of the second stage is higher than the reference voltage COMVREF, the control voltages VB4 and VB5 are the second common-mode voltage VC2 and the predetermined reference voltage COMVREF. It becomes higher than the case where it is equal to. When the control voltages VB4 and VB5 increase, the drain currents of the P-channel MOS transistors M13 and M14 decrease, the differential output voltages VOUTP and VOUTN decrease, and the second common-mode voltage VC2 also decreases.

  (C) When the second common-mode voltage VC2 of the differential output voltages VOUTP and VOUTN of the second stage is lower than the reference voltage COMVREF, the control voltages VB4 and VB5 are the second common-mode voltage VC2 and the predetermined reference voltage COMVREF. The control voltages VB4 and VB5 are lower than in the case equal to. When the control voltages VB4 and VB5 are lowered, the drain currents of the P-channel MOS transistors M13 and M14 are increased, the differential output voltages VOUTP and VOUTN are increased, and the second common-mode voltage VC2 is also increased.

  Thus, the second differential amplifier circuit 2 of the second stage is controlled so that the second common-mode voltage VC2 of the differential output voltages VOUTP and VOUTN of the second stage becomes the predetermined reference voltage COMVREF. . Even when the second common-mode voltage VC2 becomes extremely high or extremely low, a current is supplied from the control voltage generation circuit 4B to the second differential amplifier circuit 2 of the second stage, or the second Since the current can be absorbed from the second differential amplifier circuit 2 of the stage, abnormal operation can be prevented.

  Furthermore, the control voltages VB4 and VB5 output from the control voltage generation circuit 4B are set equal to the gate voltages of the P-channel MOS transistors M13 and M14 that control the upper limit of the output voltage range of the second stage. By using a folded cascode circuit that can set a relatively wide range, the degree of freedom for setting the output voltage range of the fully differential operational amplifier 100 is expanded. Further, the circuit scale is reduced, high speed operation is possible, and current consumption can be reduced.

  Furthermore, the P-channel MOS transistors M31 to M33, which are differential input transistors of the control voltage generation circuit 4B, are P-channel MOS transistors M1, M1, which are differential input transistors of the first differential amplifier circuit 1 in FIG. It is the same conductive channel type as M2. When the P channel type MOS transistors M1 and M2 are changed to the N channel type, the P channel type MOS transistors M31 to M33 are also changed to the N channel type. As a result, the influence on the circuit characteristics due to variations in process parameters tends to be the same, and the frequency characteristics and settling characteristics of the fully differential operational amplifier 100 are stabilized.

[Configuration of Bias Circuit 6]
FIG. 8 is a specific circuit diagram of the bias circuit 6. The bias circuit 6 supplies bias voltages VB0, VB1, and VB3 for proper operation of each circuit. The bias circuit 6 has a start-up circuit unit 6A for smooth start-up after canceling the power-down and causing the fully differential operational amplifier 100 to operate stably, and a constant Gm-type bias circuit unit for generating bias voltages VB0, VB1, and VB3. 6B. Gm is an abbreviation for transconductance.

  The start-up circuit unit 6A operates in response to the power-down signal PWDB, and includes inverters IV1 and IV2, P-channel MOS transistors MSTP1 to MSTP4, N-channel MOS transistors MSTN1 to MSTN3, and a capacitor CST.

  The constant Gm type bias circuit section 6B includes P channel type MOS transistors M51, M52, M55, M56, M59, M60, M63, M64, M67, M68, MVB2, M80, M81, M82, N channel type MOS transistors M53, It consists of M54, M57, M58, M61, M62, M65, M66, M69, M70, MVB1, M83, M84, and M85.

  As described above, the first CMFB circuit 3 and the second CMFB circuit 4 are provided in each stage of the fully differential operational amplifier 100 having two stages, and the first differential amplifier circuit 1 and the second difference are provided. The dynamic amplifier circuit 2 is controlled independently. Therefore, the common mode feedback loop does not go through the phase compensation circuit, so that the stability of the entire circuit is improved and high speed operation is possible. In addition, the common mode feedback circuit can be simplified and current consumption can be reduced.

  The fully differential operational amplifier 100 according to the present embodiment improves the stability of circuit operation without degrading the characteristics while utilizing the high gain and large amplitude output characteristic of the differential operational amplifier having a plurality of stages. It has features that enable high-speed operation and reduce power consumption.

  In the present embodiment, the output of the control voltage generation circuit 4B of the second CMFB circuit 4 is two control voltages VB4 and VB5, but there may be one output depending on the circuit configuration. Further, the size of the MOS transistor mentioned as an example can be arbitrarily set without being limited to this. In the first differential amplifier circuit 1, the P-channel MOS transistor is a differential input transistor, but an N-channel MOS transistor may be a differential input transistor.

  The present invention can be applied to all fully differential operational amplifiers having a plurality of stages when the common mode feedback loop is configured without going through the phase compensation circuit 5.

  The present invention can also be applied to a conventional fully differential type operational amplifier of FIG. In this case, the first CMFB circuit 3 is provided in the first stage instead of the CMFB circuit 52, and the second CMFB circuit 4 is provided in the second stage. Instead of the bias voltage from the bias circuit 54, the control voltages VB4 and VB5 of the control voltage generation circuit 4B of the second CMFB circuit 4 are applied to the gates of the second stage P-channel MOS transistors M6 and M7, respectively. The In this configuration, since the bias voltage is common, there may be only one control voltage.

<< Second Embodiment >>
FIG. 9 is a circuit diagram of a fully differential operational amplifier 100A in the second embodiment. In the first embodiment, the fully differential operational amplifier 100A changes the P-channel MOS transistors M1 and M2, which are differential input transistors of the first differential amplifier circuit 1, to cascode connection circuits, The N-channel MOS transistors M11, M12, M15, and M16 of the differential amplifier circuit 2 are also changed to cascode connection circuits. Thereby, the gain characteristic and frequency characteristic of a fully differential operational amplifier can be improved.

  That is, a P-channel MOS transistor M91 is connected in series to the drain side of the P-channel MOS transistor M1, and a P-channel MOS transistor M92 is connected in series to the drain side of the P-channel MOS transistor M2. A bias voltage generated by the P-channel MOS transistor M93 and the P-channel MOS transistor M94 is commonly applied to the gates of M91 and M92. The P-channel MOS transistor M93 and the PN-channel MOS transistor M94 are connected in series between the drain of the P-channel MOS transistor M5 that is a current source transistor and the ground. A bias voltage VB0 is applied to the gate of M94.

  Further, N-channel MOS transistors M95, M96, M97, and M98 are connected in series to the source sides of the N-channel MOS transistors M11, M12, M15, and M16 of the second differential amplifier circuit 2, respectively. A common bias voltage VB1 is applied to the gates of the N-channel MOS transistors M95, M96, M97, and M98.

  FIG. 10 is a circuit diagram of the control voltage generation circuit 4B in the present embodiment. In this circuit, in the control voltage generation circuit 4B (FIG. 7) of the first embodiment, P-channel MOS transistors M31 to M33, which are differential input transistors, are connected to a cascode connection circuit in order to improve gain characteristics and frequency characteristics. It has been changed to.

  That is, P-channel MOS transistors M101, M102, and M103 are connected in series to the drain sides of M31, M32, and M33, respectively. The ground potential VSS is applied to the gates of the P-channel MOS transistors M101, M102, and M103 via the N-channel MOS transistor M104. That is, when the gate signal RP of M104 is at H level, M104 is turned on. Then, the ground potential VSS is applied to the gates of the P-channel MOS transistors M101, M102, and M103, and M101, M102, and M103 are turned on.

<< Third Embodiment >>
FIG. 11 is a block diagram of a fully differential operational amplifier 100B in the third embodiment. The fully-differential operational amplifier 100B has a three-stage differential amplifying unit including a first differential amplifying circuit 1, a second differential amplifying circuit 2A, and a third differential amplifying circuit 7. The first differential amplifier circuit 1 is the same as that of the first embodiment, and includes P-channel MOS transistors M1, M2, and M5 and N-channel MOS transistors M3 and M4.

  The second differential amplifier circuit 2A is composed of P-channel MOS transistors M109 and M110 and N-channel MOS transistors M111 and M112. The differential output voltages VP and VN of the first differential amplifier circuit 1 are applied to the gates of M111 and M112, respectively. The third differential amplifier circuit 7 in the third stage is composed of P-channel MOS transistors M115, M116, M119, and M120 and N-channel MOS transistors M113, M114, M117, M118, M121, and M122. Differential output voltages VOUTP and VOUTN are output from the third differential amplifier circuit 7 in the third stage.

  The first stage is provided with the first CMFB circuit 3 of the first embodiment, and the third stage is provided with the second CMFB circuit 4 of the first embodiment. The first CMFB circuit 3 includes N-channel MOS transistors M6, M7, and M8. Similar to the first embodiment, the second CMFB circuit 4 includes a common-mode voltage detection circuit 4A and a control voltage generation circuit 4B. The common-mode voltage detection circuit 4A includes the third differential signal of the third stage. The amplifier circuit 7 is connected between a pair of differential output terminals. The control voltage VB4 of the control voltage generation circuit 4B is applied to the gates of the P-channel MOS transistors M115 and M119 forming the current mirror, and the control voltage VB5 of the control voltage generation circuit 4B forms the current mirror. Applied to the gates of the P-channel MOS transistors M116 and M120.

  As described above, the first CMFB circuit 3 and the second CMFB circuit 4 are provided in the first stage and the final stage of the fully differential operational amplifier 100B having three stages, respectively. 3 differential amplifier circuit 7 is controlled independently. Therefore, as in the first embodiment, the common mode feedback loop does not go through the phase compensation circuit, so that the stability of the entire circuit is improved and high-speed operation is possible. Similar effects can be obtained.

  When generalization is performed based on the first and second embodiments, in the fully differential operational amplifier having a plurality of stages, at least the first CMFB circuit 3 and the second CMFB circuit are provided in the first stage and the final stage, respectively. The same effect can be obtained by providing the first stage differential amplifier circuit and the final stage differential amplifier circuit independently of each other.

<< Application circuit example of fully differential operational amplifier >>
The fully differential operational amplifiers 100, 100A, 100B of the first, second, and third embodiments described above and the fully differential operational amplifier of the generalized form receive a continuous signal and use the output as a continuous signal. It can be suitably applied to a continuous-time circuit that is handled. Further, these fully differential operational amplifiers can be suitably applied to a discrete time system (sampling data system).

  Examples of the discrete system (sampling data system) include a filter, a comparator, an A / D (analog / digital) converter, a D / A (digital / analog) converter, and the operational amplifier is widely used. For example, the example applied to the switched capacitor circuit which is a circuit element common to a discrete time system is given.

  FIG. 12A shows a switched capacitor integrator known as a representative example of a switched capacitor circuit. As shown in FIG. 12A, the switched capacitor integrator includes fully differential operational amplifiers 100, 100A, and 100B, capacitors CAP1 to CAP4, and switches SW1 to SW8.

  The switches SW1 and SW2 are switches for applying the differential input voltages VINP and VINN to the capacitors CAP1 and CAP2. The switches SW3, SW4, SW5 and SW6 are switches for applying the reference voltage VREF. The switches SW7 and SW8 are This is a switch for transferring the charges accumulated in the capacitors CAP1 and CAP2 to the capacitors CAP3 and CAP4. The capacitor CAP3 is connected between the inverting input terminal (−) and the non-inverting output terminal (+) of the fully differential operational amplifiers 100, 100A, and 100B. The capacitor CAP4 is connected between the non-inverting input terminal (+) and the inverting output terminal (−) of the fully differential operational amplifiers 100, 100A, 100B.

FIG. 12B shows a timing chart at which the switched capacitor integrator operates. When the clock signal CLOCK is at a high level, the switches SW1, SW2, SW5, and SW6 are turned on, the switches SW3, SW4, SW7, and SW8 are turned off, and the differential input voltages VINP and VINN are sampled on the capacitors CAP1 and CAP2, respectively. The (Sampling mode)
When the clock signal CLOCK is at a low level, the switches SW3, SW4, SW7, SW8 are turned on, the switches SW1, SW2, SW5, SW6 are turned off, and the charges sampled in the capacitors CAP1, CAP2 are respectively transferred to the capacitors. Integration is performed by accumulating in CAP3 and CAP4. (Integration mode)

DESCRIPTION OF SYMBOLS 1 1st differential amplifier circuit 2 2nd differential amplifier circuit 3 1st CMFB circuit 4 2nd CMFB circuit 4A In-phase voltage detection circuit 4B Control voltage generation circuit 5 Phase compensation circuit 6 Bias circuit 6A Startup circuit part 6B Constant Gm type bias circuit section 7 Third differential amplifier circuit 100, 100A, 100B Fully differential operational amplifier

Claims (10)

A differential amplifying unit in which a plurality of differential amplifier circuits each having a pair of differential input terminals and a pair of differential output terminals are connected to each other so as to form a plurality of stages from the first stage to the final stage;
A phase compensation circuit (5) connected between the differential input terminal and the differential output terminal of the differential amplifier circuit (2) of the final stage;
The differential amplification so that the first common-mode voltage (VC1) of the pair of differential output voltages (VP, VN) of the first-stage differential amplification circuit (1) becomes the first reference voltage (VGS1). A first common mode feedback circuit (3) for feedback control of the circuit (1);
The differential amplifier circuit so that the second common-mode voltage (VC2) of the pair of differential output voltages (VOUTP, VOUTN) of the differential amplifier circuit (2) at the final stage becomes the second reference voltage (COMVREF). And a second common mode feedback circuit (4) for feedback control of (2). The differential amplifier circuit (1) of the first stage includes a first constant current source transistor (M5) and a first differential transistor (M5) connected in series to the first constant current source transistor (M5). M1) and a second differential transistor (M2) connected in series to the constant current source transistor (M5) and connected in parallel to the first differential transistor (M1),
The first common mode feedback circuit (3) is connected in series to the first constant current source transistor (M5), and its gate is connected to the drain of the first differential transistor (M1). A second control transistor (M8) connected in series to the first control transistor (M7) and the constant current source transistor (M5) and having its gate connected to the drain of the second differential transistor (M2). The fully differential operational amplifier according to claim 1, further comprising: The differential amplifier circuit (1) of the first stage includes a first constant current source transistor (M5) and a first differential transistor (M5) connected in series to the first constant current source transistor (M5). M1), a second differential transistor (M2) connected in series to the constant current source transistor (M5) and connected in parallel to the first differential transistor (M1),
A first cascode transistor (M91) connected in series to the first differential transistor (M1) and forming a first cascode connection circuit together with the first differential transistor (M1); A second cascode transistor (M92) connected in series to the differential transistor (M2) and forming a second cascode connection circuit together with the second differential transistor (M2),
The first common mode feedback circuit (3) is connected in series to the first constant current source transistor (M5), and its gate is connected to the drain of the first cascode transistor (M91). One control transistor (M7) and a second control transistor (M8) connected in series to the constant current source transistor (M5) and having the gate connected to the drain of the second cascode transistor (M92). The fully differential operational amplifier according to claim 1, further comprising: The second common mode feedback circuit (4) includes a common-mode voltage detection circuit (4A) for detecting the second common-mode voltage (VC2) of the differential amplifier circuit (2) in the final stage;
Based on the second common-mode voltage (VC2) detected by the common-mode voltage detection circuit (4A), a first control voltage (VB4) for controlling the differential amplifier circuit (2) of the final stage, and The fully differential operational amplifier according to any one of claims 1 to 3, further comprising a control voltage generation circuit (4B) that generates a second control voltage (VB5). The final stage differential amplifier circuit (2) is connected in series to a second constant current source transistor (M13) and the second constant current source transistor (M13), and the first stage differential amplifier circuit (2). The third differential transistor (M15) to which the first differential output voltage (VP) of the circuit (2) is applied, the third constant current source transistor (M14), and the second constant current source transistor A fourth differential transistor (M16) connected in series to (M14) and applied with the second differential output voltage (VN) of the differential amplifier circuit (2) of the first stage,
The first control voltage (VB4) is applied to the gate of the second constant current source transistor (M13), and the second control voltage (VB5) is applied to the gate of the third constant current source transistor (M14). The fully differential operational amplifier according to claim 4, wherein: is applied.   The common-mode voltage detection circuit (4A) includes a first resistor (RP) and a second resistor (RN) connected in series between a pair of differential output terminals of the differential amplifier circuit (2) of the final stage. The second common-mode voltage (VC2) is obtained from a connection point of the first resistor (RP) and the second resistor (RN). Differential operational amplifier.   A first stabilization capacitor (CP) and a second stabilization capacitor (CN) are connected in parallel to the first resistor (RP) and the second resistor (RN), respectively. Item 7. A fully differential operational amplifier according to Item 6. The common-mode voltage detection circuit (4A) includes a first switching capacitor (CP1), a second switching capacitor (CN1), an output terminal (OUT), and the first switching capacitor in a first mode. A capacitor (CP1) is connected between the first differential output terminal of the final stage differential amplifier circuit (2) and the output terminal (VOUT), and the second capacitor (CN1) is connected to the final stage. Connected between the second differential output terminal of the differential amplifier circuit (2) and the output terminal,
In the second mode, the first switching capacitor (CP1) is connected between the second differential output terminal and the output terminal of the differential amplifier circuit (2) of the final stage, and the second A switching circuit for switching the switching capacitor (CN1) to be connected between the first differential output terminal and the output terminal of the differential amplifier circuit (2) of the final stage. The fully differential operational amplifier according to claim 4 or 5.   The fully differential operational amplifier according to claim 8, wherein a capacitance value of the first capacitor (CP1) and a capacitance value of the second capacitor (CN1) are equal. The control voltage generation circuit (4B) has a third differential input transistor (M31) to which the second common-mode voltage (VC2) is applied to the gate, and the second reference voltage (COMVREF) to the gate. And fourth and fifth differential input transistors (M32, M33),
The first and second differential transistors (M1, M2) and the third, fourth, and fifth differential input transistors (M31, M32, M33) of the first stage differential amplifier circuit (1). 5. The fully differential operational amplifier according to claim 4, wherein the same conductive channel type is used.

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