CN107765751A - Common mode feedback circuit and signal processing circuit - Google Patents
Common mode feedback circuit and signal processing circuit Download PDFInfo
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- CN107765751A CN107765751A CN201711225331.5A CN201711225331A CN107765751A CN 107765751 A CN107765751 A CN 107765751A CN 201711225331 A CN201711225331 A CN 201711225331A CN 107765751 A CN107765751 A CN 107765751A
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Abstract
The invention discloses a kind of common mode feedback circuit and signal processing circuit, it is related to technical field of integrated circuits.The common mode feedback circuit includes being connected to power supply and the current source sub-circuit of bias current sources is provided for common mode feedback circuit, the comparison sub-circuit of reference voltage and Differential OPAMP circuit common mode output voltage is connected to, is connected to the load sub-circuit of the relatively sub-circuit；The current source sub-circuit is connected to the relatively sub-circuit, relatively the sub-circuit reference voltage and the common mode output voltage, and exports feedback voltage and stablize the voltage of the Differential OPAMP circuit to adjust.Technical solution of the present invention passes through the comparison sub-circuit comparison reference voltage and common mode output voltage in common mode feedback circuit, output feedback voltage makes its matched load electric current to Differential OPAMP circuit to adjust tail current, common mode output voltage can be stablized simultaneously, there is provided the wider amplitude of oscillation and higher gain.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly to a kind of common mode feedback circuit and signal processing circuit.
Background technology
With the development of Analogous Integrated Electronic Circuits technology, high speed, high-precision operational amplifier are used widely.Fully differential
Operational amplifier is in output voltage swing, out-put dynamic range, PSRR（Power Supply Rejection Ratio,
PSRR）Etc., have great advantage compared with Single-end output amplifier.But Differential OPAMP has that output common mode level is unstable to ask
Topic, the negative-feedback of differential signal can not stable DC operating point.Therefore need to design common mode feedback circuit（Common-
Mode-feedback, CMFB）To ensure amplifier normal work, amplifier is set to be improved while stabilizing circuit dc point defeated
Go out the amplitude of oscillation.
The content of the invention
The main object of the present invention is to provide a kind of common mode feedback circuit and signal processing circuit, it is intended to makes operational amplifier
Output voltage swing is improved while stabilizing circuit dc point.
To achieve the above object, the present invention provides a kind of common mode feedback circuit, including is connected to power supply and is common-mode feedback
Circuit provides the current source sub-circuit of bias current sources, is connected to reference voltage and Differential OPAMP circuit common mode output voltage
Compare sub-circuit, be connected to the load sub-circuit of the relatively sub-circuit；It is sub that the current source sub-circuit is connected to the comparison
Circuit, relatively the sub-circuit reference voltage and the common mode output voltage, and it is steady to adjust to export feedback voltage
The voltage of the fixed Differential OPAMP circuit.
Preferably, the current source sub-circuit includes the first FET and the second FET, and both source electrodes connect
It is connected to power supply, grid is all connected to the first bias voltage；The drain electrode of first FET is connected to the relatively sub-circuit
In the 3rd FET and the 4th FET source electrode, the drain electrode of second FET is connected to the sub- electricity of the comparison
The source electrode of the 5th FET and the 6th FET in road.
Preferably, the grid of the 3rd FET is connected to the first common mode output voltage, and drain electrode is connected to described negative
Carrier circuit；The grid of 4th FET is connected to the reference voltage with the grid of the 5th FET, institute
The drain electrode for stating the 4th FET and the 5th FET is connected to the load sub-circuit；6th FET
Drain electrode is connected to load sub-circuit, and grid is connected to the second common mode output voltage.
Preferably, the load sub-circuit is connected to the load of the common mode feedback circuit, including the 7th FET and
8th FET；The drain electrode of 7th FET is connected with each other with grid, at the same with the 3rd FET and the
The drain electrode connection of six FETs, and to the Differential OPAMP circuit output feedback voltage；The grid of 8th FET
Pole and drain electrode are connected with each other, and are connected to the drain electrode of the 4th FET and the 5th FET；Described 7th
The source ground of effect pipe and the 8th FET.
The present invention also provides a kind of signal processing circuit, including Differential OPAMP circuit and common-mode feedback as described above electricity
Road, the Differential OPAMP circuit include first order sub-circuit, are connected by the first Miller's compensating circuit with first order sub-circuit
Second level sub-circuit, and with the mirror image of first order sub-circuit, the first Miller's compensating circuit and second level sub-circuit mirror image
Circuit；
The first order sub-circuit is connected to the feedback voltage output end of the common mode feedback circuit, and the second level sub-circuit connects
The relatively sub-circuit is connected to, to receive the first common mode output voltage of the common mode feedback circuit output.
Preferably, the first order sub-circuit include be sequentially connected the 9th FET, the tenth FET, the 11st
FET and the 12nd FET, the 9th FET connect power supply, the 12nd FET ground connection；
The 9th FET source electrode connects power supply, and drain electrode is connected to the source electrode of the tenth FET；Described ten effect
Should the drain electrode of pipe be connected to the source electrode of the 11st FET；The source ground of 12nd FET, grid connect
The relatively sub-circuit is connected to, drain electrode is connected to the drain electrode of the 11st FET；
The first order sub-circuit also includes the 13rd FET, the 14th FET, the 15th FET and the tenth
Six FETs；The 13rd FET source electrode is connected to power supply, grid is connected to the first bias voltage, drain electrode is connected to
The source electrode of 14th FET；14th fet gate is connected to the second bias voltage, and drain electrode is connected to
The draining of 15th FET, first Miller's compensating circuit and the second level sub-circuit；Described 15th
Effect tube grid is connected to the 3rd bias voltage, and drain electrode is connected to the draining of the 14th FET, described first
Miller's compensating circuit and the second level sub-circuit, source electrode are connected to the drain electrode of the 11st FET, the 12nd
The drain electrode of FET and the drain electrode of the 16th FET；16th fet gate is connected to the 4th biased electrical
Pressure, source ground.
Preferably, the second level sub-circuit includes the 17th FET and the 18th FET being sequentially connected；
The source electrode of 17th FET connects power supply, grid is connected to the drain electrode of the 14th FET and the 15th imitates
Should pipe drain electrode；The grid of 18th FET is connected to the 4th bias voltage, source ground；
The drain electrode of 17th FET and the drain electrode of the 18th FET are connected with each other, and it is sub to be connected to the comparison
Circuit, to receive the first common mode output voltage of the common mode feedback circuit output.
Preferably, first Miller's compensating circuit includes the first electric capacity and first resistor of series connection, first electric capacity
One end be connected to the draining of the 14th FET, the 15th FET drain and the 17th effect
Tube grid is answered, the other end of first electric capacity is connected to one end of the first resistor, and the other end of the first resistor connects
It is connected to the drain electrode of the 17th FET and the drain electrode of the 18th FET.
Technical solution of the present invention by the comparison sub-circuit comparison reference voltage and common mode output voltage in common mode feedback circuit,
Output feedback voltage makes its matched load electric current to Differential OPAMP circuit to adjust tail current, while can stable common mode output electricity
Pressure, there is provided the wider amplitude of oscillation and higher gain.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Structure according to these accompanying drawings obtains other accompanying drawings.
Fig. 1 is the circuit theory diagrams of common mode feedback circuit of the present invention；
Fig. 2 is the circuit theory diagrams of Differential OPAMP circuit of the present invention；
Fig. 3 is the circuit theory diagrams of signal processing circuit of the present invention.
The realization, functional characteristics and advantage of the object of the invention will be described further referring to the drawings in conjunction with the embodiments.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only the part of the embodiment of the present invention, rather than whole embodiments.Base
Embodiment in the present invention, those of ordinary skill in the art obtained under the premise of creative work is not made it is all its
His embodiment, belongs to the scope of protection of the invention.
In addition, the description for being related to " first ", " second " etc. in the present invention is only used for describing purpose, and it is not intended that referring to
Show or imply its relative importance or imply the quantity of the technical characteristic indicated by indicating.Thus, " first ", " are defined
At least one this feature can be expressed or be implicitly included to two " feature.In addition, the technical scheme between each embodiment can
To be combined with each other, but must can be implemented as basis with those of ordinary skill in the art, when the combination of technical scheme occurs
It is conflicting or will be understood that the combination of this technical scheme is not present when can not realize, also not in the protection model of application claims
Within enclosing.
The present invention proposes a kind of common mode feedback circuit and signal processing circuit, is related to integrated circuit fields, common-mode feedback electricity
Road is mainly used in the electric current of Differential OPAMP circuit in stabilization signal process circuit.
As shown in figure 1, in the first embodiment of the invention, common mode feedback circuit is including being connected to power supply AVDD and being common mode
Feedback circuit provides the current source sub-circuit of bias current sources, is connected to reference voltage Vcm and Differential OPAMP circuit common mode is defeated
Go out the comparison sub-circuit of voltage, be connected to the load sub-circuit of the relatively sub-circuit；The current source sub-circuit is connected to institute
State and compare sub-circuit, relatively the sub-circuit reference voltage Vcm and the common mode output voltage, and export feedback electricity
Pressure Vcmfb stablizes the voltage of the Differential OPAMP circuit to adjust.
Preferably, the current source sub-circuit includes the first FET M1 and the second FET M2, both source electrodes
It is all connected to power supply AVDD, grid is all connected to the first bias voltage Vbp1；The drain electrode of the first FET M1 is connected to
The source electrode of the 3rd FET M3 and the 4th FET M4 in the relatively sub-circuit, the leakage of the second FET M2
Pole is connected to the source electrode of the 5th FET M5 and the 6th FET M6 in the relatively sub-circuit.
Preferably, the grid of the 3rd FET M3 is connected to the first common mode output voltage OUTP, and drain electrode is connected to
The load sub-circuit；The grid of the 4th FET M4 is connected to the ginseng with the grid of the 5th FET M5
Voltage Vcm is examined, the 4th FET M4 and the 5th FET M5 drain electrode are connected to the load sub-circuit；Institute
The drain electrode for stating the 6th FET M6 is connected to load sub-circuit, and grid is connected to the second common mode output voltage OUTN.
Preferably, the load sub-circuit is connected to the load of the common mode feedback circuit, including the 7th FET M7
With the 8th FET M8；The drain electrode of the 7th FET M7 is connected with each other with grid, at the same with the 3rd field-effect
Pipe M3 and the 6th FET M6 drain electrode connection, and to the Differential OPAMP circuit output feedback voltage V cmfb；Described
Eight FET M8 grid and drain electrode are connected with each other, and are connected to the 4th FET M4 and the 5th FET
M5 drain electrode；The 7th FET M7 and the 8th FET M8 source ground AGND.
As shown in Figure 2 and Figure 3, in second embodiment of the invention, signal processing circuit includes Differential OPAMP circuit and the
Common mode feedback circuit in one embodiment, the Differential OPAMP circuit include first order sub-circuit, pass through the first Miller
（miller）The second level sub-circuit that compensation circuit is connected with first order sub-circuit, and with first order sub-circuit, the first Miller
The mirror image sub-circuit of compensation circuit and second level sub-circuit mirror image；The first order sub-circuit is connected to the common mode feedback circuit
Feedback voltage V cmfb output ends, the second level sub-circuit be connected to it is described relatively sub-circuit, it is anti-to receive the common mode
First common mode output voltage OUTP of current feed circuit output.
Preferably, the first order sub-circuit include be sequentially connected the 9th FET M9, the tenth FET M10,
11st FET M11 and the 12nd FET M12, the 9th FET M9 connections power supply AVDD, the described tenth
Two FET M12 are grounded AGND；
The 9th FET M9 source electrodes meet power supply AVDD, and drain electrode is connected to the source electrode of the tenth FET M10；It is described
Tenth FET M10 drain electrode is connected to the source electrode of the 11st FET M11；The 12nd FET M12
Source ground AGND, grid is connected to the relatively sub-circuit, and drain electrode is connected to the 11st FET M11 drain electrode；
The first order sub-circuit also includes the 13rd FET M13, the 14th FET M14, the 15th FET
M15 and the 16th FET M16；The 13rd FET M13 source electrodes are connected to power supply AVDD, grid is connected to first
Bias voltage Vbp1, drain electrode are connected to the 14th FET M14 source electrode；The 14th FET M14 grids connection
In the second bias voltage Vbn2, drain electrode is connected to the draining of the 15th FET M15, first miller compensation
Circuit and the second level sub-circuit；The 15th FET M15 grids are connected to the 3rd bias voltage Vbn1, drain electrode point
The draining of the 14th FET M14, first Miller's compensating circuit and the second level sub-circuit, source are not connected to
Pole is connected to the drain electrode of the 11st FET M11, the 12nd FET M12 drain electrode and the 16th field-effect
Pipe M16 drain electrode；The 16th FET M16 grids are connected to the 4th bias voltage Vbn2, source ground AGND.
Preferably, the second level sub-circuit includes the 17th FET M17 and the 18th field-effect being sequentially connected
Pipe M18；The source electrode of the 17th FET M17 meets power supply AVDD, grid is connected to the 14th FET M14's
Drain electrode and the 15th FET M15 drain electrode；18th FET M18 grid is connected to the 4th bias voltage Vbn2,
Source ground AGND；
The drain electrode of the 17th FET M17 and the 18th FET M18 drain electrode are connected with each other, and are connected to described
Compare sub-circuit, to receive the first common mode output voltage OUTP of the common mode feedback circuit output.
Preferably, first Miller's compensating circuit includes the first electric capacity C1 and first resistor R1 of series connection, and described first
Electric capacity C1 one end be connected to the draining of the 14th FET M14, the 15th FET M15 drain electrodes with
And the 17th FET M17 grid, the other end of the first electric capacity C1 is connected to one end of the first resistor R1, described
The first resistor R1 other end is connected to the drain electrode of the 17th FET M17 with the 18th FET M18's
Drain electrode.
Include with the mirror image sub-circuit of first order sub-circuit, the first Miller's compensating circuit and second level sub-circuit mirror image：The
19 FET M19, the 20th FET M20, the 21st FET M21, the 22nd FET M22,
23 FET M23, the 24th FET M24, the 25th FET M25, the 26th FET M26
With the second Miller's compensating circuit, the second Miller's compensating circuit includes second resistance R2 and the second electric capacity C2.
19th FET M19 source electrode is connected to power supply AVDD, and grid is connected to the 9th FET M9's
Grid and the first bias voltage Vbp1, drain electrode are connected to the 20th FET M20 source electrode；20th FET M20's
Grid is connected to the tenth FET M10 grid and the second bias voltage Vbn2, and drain electrode is connected to the 21st effect
Should pipe M21 drain electrode；21st FET M21 grid is connected to the 3rd bias voltage Vbn1, and source electrode is connected to
22nd FET M22 drain electrode, the 23rd FET M23 drain electrode and the 24th FET M24 leakage
Pole；22nd FET M22 source ground AGND, grid are connected to the 4th bias voltage Vbn2；23rd field-effect
Pipe M23 source electrodes are connected to the tenth FET M10 drain electrodes and the 11st FET M11 source electrode；24th FET
M24 source ground AGND, the 24th FET M24 grid are connected jointly with the 12nd FET M12 grid
Tail electricity is can adjust in the feedback voltage V cmfb of common mode feedback circuit output, the feedback voltage V cmfb of common mode feedback circuit output
The FET M12 of flow tube the 12nd and the 24th FET M24, make the change of its matched load electric current, so as to stable common
Mould output voltage, ensure the normal work of amplifier.
25th FET M25 source electrodes are connected to power supply AVDD, and grid is connected to the 20th FET M20 leakage
Pole and the 21st FET M21 drain electrode；26th FET M26 source ground AGND, grid are connected to
4th bias voltage Vbn2.25th FET M25 drain electrode is connected and connected with the 26th FET M26 drain electrode
The 6th FET M6 grid is connected to, to receive the second common mode output voltage OUTN of common mode feedback circuit output.
Second electric capacity C2 of the second Miller's compensating circuit one end is connected to the 20th FET M20 drain electrode, second
11 FET M21 drain electrode and the 25th FET M25 grid, the second electric capacity C2 other end are connected to second
Resistance R2 one end, the second resistance R2 other end are connected to the second common mode output voltage OUTN ends.
In circuit of the present invention, the first bias voltage Vbp1 is the 19th FET M19, the 9th FET M9, the tenth
Three FET M13, the first FET M1 and the second FET M2 provide bias voltage；Second bias voltage Vbn2 is the
20 FET M20, the tenth FET M10, the 14th FET M14 provide bias voltage；3rd bias voltage
Vbn1 is that the 21st FET M21 and the 15th FET M15 provide bias voltage；4th bias voltage Vbn2 is the
26 FET M26, the 22nd FET M22, the 24th FET M24, the 12nd FET M12,
16th FET M16, the 18th FET M18, the 7th FET M7 and the 8th FET M8 provide biased electrical
Pressure.
The present invention circuit theory be：Common mode feedback circuit includes M1 ~ M8；Differential OPAMP circuit includes M9 ~ M26, the
One resistance R1 and the first electric capacity C1, second resistance R2 and the second electric capacity C2 form the Miller's compensating circuit of Differential OPAMP circuit,
The stabilization of Differential OPAMP circuit can be ensured；Common mode feedback circuit is by detecting the first common mode output voltage OUTP, the second common mode
Output voltage OUTN, and compared with reference voltage Vcm after, feedback voltage V cmfb is to adjust the 12nd FET for output
M12 and the 24th FET M24, makes the change of its matched load electric current, and so as to stablize common mode output voltage, it is complete poor to ensure
Divide the normal work of discharge circuit.
The preferred embodiments of the present invention are the foregoing is only, are not intended to limit the scope of the invention, it is every at this
Under the inventive concept of invention, the equivalent structure transformation made using description of the invention and accompanying drawing content, or directly/use indirectly
It is included in other related technical areas in the scope of patent protection of the present invention.
Claims (8)
1. a kind of common mode feedback circuit, it is characterised in that including being connected to power supply and providing bias current for common mode feedback circuit
The current source sub-circuit in source, the comparison sub-circuit of reference voltage and Differential OPAMP circuit common mode output voltage is connected to, connected
In the load sub-circuit of the relatively sub-circuit；It is sub that the current source sub-circuit is connected to relatively sub-circuit, the comparison
The circuit reference voltage and the common mode output voltage, and export feedback voltage and stablize the Differential OPAMP to adjust
The voltage of circuit.
2. signal processing circuit according to claim 1, it is characterised in that the current source sub-circuit includes first effect
Should manage with the second FET, both source electrodes are all connected to power supply, grid is all connected to the first bias voltage；Described first
The drain electrode of effect pipe is connected to the source electrode of the 3rd FET relatively in sub-circuit and the 4th FET, and described second
The drain electrode of FET is connected to the source electrode of the 5th FET and the 6th FET in the relatively sub-circuit.
3. signal processing circuit according to claim 2, it is characterised in that the grid of the 3rd FET is connected to
First common mode output voltage, drain electrode are connected to the load sub-circuit；The grid of 4th FET with described 5th
The grid of effect pipe is connected to the reference voltage, and the drain electrode of the 4th FET and the 5th FET is connected to
The load sub-circuit；The drain electrode of 6th FET is connected to load sub-circuit, and grid is connected to the output of the second common mode
Voltage.
4. signal processing circuit according to claim 3, it is characterised in that the load sub-circuit is connected to load, wraps
Include the 7th FET and the 8th FET；The drain electrode of 7th FET is connected with each other with grid, at the same with it is described
The drain electrode connection of 3rd FET and the 6th FET, and to the Differential OPAMP circuit output feedback voltage；It is described
The grid of 8th FET and drain electrode are connected with each other, and are connected to the 4th FET and the 5th FET
Drain electrode；The source ground of 7th FET and the 8th FET.
5. a kind of signal processing circuit, it is characterised in that including any in Differential OPAMP circuit and such as Claims 1-4 item
Common mode feedback circuit described in, the Differential OPAMP circuit include first order sub-circuit, pass through the first Miller's compensating circuit
The second level sub-circuit being connected with first order sub-circuit, and with first order sub-circuit, the first Miller's compensating circuit and the second level
The mirror image sub-circuit of sub-circuit mirror image；
The first order sub-circuit is connected to the feedback voltage output end of the common mode feedback circuit, and the second level sub-circuit connects
The relatively sub-circuit is connected to, to receive the first common mode output voltage of the common mode feedback circuit output.
6. signal processing circuit according to claim 5, it is characterised in that the first order sub-circuit includes being sequentially connected
The 9th FET, the tenth FET, the 11st FET and the 12nd FET, the 9th FET connects
Connect power supply, the 12nd FET ground connection；
The 9th FET source electrode connects power supply, and drain electrode is connected to the source electrode of the tenth FET；Described ten effect
Should the drain electrode of pipe be connected to the source electrode of the 11st FET；The source ground of 12nd FET, grid connect
The relatively sub-circuit is connected to, drain electrode is connected to the drain electrode of the 11st FET；
The first order sub-circuit also includes the 13rd FET, the 14th FET, the 15th FET and the tenth
Six FETs；The 13rd FET source electrode is connected to power supply, grid is connected to the first bias voltage, drain electrode is connected to
The source electrode of 14th FET；14th fet gate is connected to the second bias voltage, and drain electrode is connected to
The draining of 15th FET, first Miller's compensating circuit and the second level sub-circuit；Described 15th
Effect tube grid is connected to the 3rd bias voltage, and drain electrode is connected to the draining of the 14th FET, described first
Miller's compensating circuit and the second level sub-circuit, source electrode are connected to the drain electrode of the 11st FET, the 12nd
The drain electrode of FET and the drain electrode of the 16th FET；16th fet gate is connected to the 4th biased electrical
Pressure, source ground.
7. signal processing circuit according to claim 6, it is characterised in that the second level sub-circuit includes being sequentially connected
The 17th FET and the 18th FET；The source electrode of 17th FET connects power supply, grid is connected to institute
State the drain electrode of the 14th FET and the drain electrode of the 15th FET；It is inclined that the grid of 18th FET is connected to the 4th
Put voltage, source ground；
The drain electrode of 17th FET and the drain electrode of the 18th FET are connected with each other, and it is sub to be connected to the comparison
Circuit, to receive the first common mode output voltage of the common mode feedback circuit output.
8. signal processing circuit according to claim 7, it is characterised in that first Miller's compensating circuit includes series connection
The first electric capacity and first resistor, one end of first electric capacity be connected to the drain electrode of the 14th FET, institute
The 15th FET drain and the 17th fet gate are stated, the other end of first electric capacity is connected to described first
One end of resistance, the other end of the first resistor are connected to the drain electrode of the 17th FET and the 18th effect
Should pipe drain electrode.
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| CN201711225331.5A CN107765751B (en) | 2017-11-29 | 2017-11-29 | Common mode feedback circuit and signal processing circuit |
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| CN201711225331.5A CN107765751B (en) | 2017-11-29 | 2017-11-29 | Common mode feedback circuit and signal processing circuit |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111446935A (en) * | 2020-05-20 | 2020-07-24 | 苏州纳芯微电子股份有限公司 | Differential signal amplifying circuit, digital isolator and digital receiver |
| CN114448367A (en) * | 2020-11-02 | 2022-05-06 | 圣邦微电子（北京）股份有限公司 | Common mode feedback circuit of fixed potential |
| CN114447898A (en) * | 2022-01-26 | 2022-05-06 | 苏州纳芯微电子股份有限公司 | Current limiting circuit and electric equipment with same |
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| CN111446935A (en) * | 2020-05-20 | 2020-07-24 | 苏州纳芯微电子股份有限公司 | Differential signal amplifying circuit, digital isolator and digital receiver |
| WO2021232861A1 (en) * | 2020-05-20 | 2021-11-25 | 苏州纳芯微电子股份有限公司 | Differential signal amplification circuit, digital isolator, and receiver |
| CN111446935B (en) * | 2020-05-20 | 2023-10-13 | 苏州纳芯微电子股份有限公司 | Differential signal amplifying circuit, digital isolator and digital receiver |
| CN114448367A (en) * | 2020-11-02 | 2022-05-06 | 圣邦微电子（北京）股份有限公司 | Common mode feedback circuit of fixed potential |
| CN114447898A (en) * | 2022-01-26 | 2022-05-06 | 苏州纳芯微电子股份有限公司 | Current limiting circuit and electric equipment with same |
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