CN108880488A - The protection circuit of differential pair tube - Google Patents
The protection circuit of differential pair tube Download PDFInfo
- Publication number
- CN108880488A CN108880488A CN201810695577.7A CN201810695577A CN108880488A CN 108880488 A CN108880488 A CN 108880488A CN 201810695577 A CN201810695577 A CN 201810695577A CN 108880488 A CN108880488 A CN 108880488A
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- China
- Prior art keywords
- tube
- nmos
- pmos
- pmos tube
- grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/52—Circuit arrangements for protecting such amplifiers
- H03F1/523—Circuit arrangements for protecting such amplifiers for amplifiers using field-effect devices
Abstract
Present invention discloses a kind of protection circuits of differential pair tube; related differential pair tube has two kinds of standards of CMOS technology; it is formed it is characterized in that the protection circuit is connected in foreign peoples's type pipe between current source and differential pair tube by the total grid of clamp circuit and two, wherein clamp circuit is from the conducting that NMOS tube or PMOS tube are constituted to the circuit of reciprocal coupling；And selective combined resistance in protection circuit, further promote the performance of protection circuit.Circuit is protected using the present invention, is connected and composed by clamp circuit in improvement differential pair tube protective circuit, in CMOS technology, reduces the area of clamp circuit；Furthermore it is preferred that input can be offset to pipe technique change with differential pair tube same type device, inhibit to input the electric leakage to pipe with the sensitivity of technique.
Description
Technical field
The present invention relates to a kind of protection circuits of differential pair tube.
Background technique
Differential pair tube is in operational amplifier（OPAMP）And comparator（Comparator）In be widely used, and in CMOS
And Bipolar（BJT）Can all it be related in technique, and some semiconductor technologies determine Vin+And Vin-Between voltage difference cannot be too
Greatly.
Differential pair tube usually connects a current source by pairs of PMOS tube or NMOS tube common source and constitutes, and tradition is common
Circuit is protected, is made of two resistance and two diodes.When the voltage difference of Vin+ and Vin- is more than diode valve threshold voltage,
Diode just opens conducting, and current flowing resistance forms voltage drop.Even if Vin+ and Vin- voltage difference in this way is larger, differential pair tube
Pressure difference between two grids also can guarantee smaller, to play the role of protecting differential pair tube, certain each diode can also be by
Multiple Diode series substitutions, to improve the threshold voltage opened.
Existing patent（ZL 2015103146512）Disclose a kind of protection circuit of differential pair tube.In normal work,
The voltage of Vin+ and Vin- is very close to two NMOS tubes are in linear condition, are equivalent to two resistance.When Vin+ and Vin- voltage
When differing larger, the Vgs of one of NMOS tube declines, and is in by state, is equivalent to resistance and becomes larger, preferably protect difference
Divide to pipe.
However, these previous protection circuits, mostly break through water conservancy diversion using diode threshold values and form voltage drop, reduce
Pressure difference between Vin+ and Vin-.However diode area is larger, and pressure difference is limited to diode between differential pair tube grid
Threshold values can not further promote the sensitivity of protection circuit.
Summary of the invention
In view of the problems of the above-mentioned prior art, the purpose of the present invention is to propose to a kind of protection circuits of differential pair tube.
In order to achieve the above object, the technical scheme adopted by the invention is as follows：The protection circuit of differential pair tube, it is related
Differential pair tube has the first PMOS tube, the second PMOS tube and current source, and the common source of two PMOS tube is connected on current source
Node A, it is characterised in that：The protection circuit is made of the NMOS tube that clamp circuit and two total grid are connected in node A, wherein
The source electrode of first NMOS tube is mutually coupled with the grid of the first PMOS tube, one end of clamp circuit, and the drain electrode of the first NMOS tube with
Vin+ is connected；The source electrode of second NMOS tube is mutually coupled with the grid of the second PMOS tube, the other end of clamp circuit, and the 2nd NMOS
The drain electrode of pipe is connected with Vin-.
Further, the clamp circuit is to be connected from third PMOS tube and the 4th PMOS tube to reciprocal coupling to constitute,
The source electrode and the drain electrode of the 4th PMOS tube, grid of middle third PMOS tube are coupled to one end of clamp circuit, the source of the 4th PMOS tube altogether
The drain electrode of pole and third PMOS tube, grid are coupled to the other end of clamp circuit altogether.
Further, branch where third PMOS tube contains n concatenated PMOS tube in the clamp circuit, and the 4th
Branch where PMOS tube contains n concatenated PMOS tube, and n is the positive integer greater than 1.
Further, resistance R1 is equipped between first PMOS tube and the common source and node A of the second PMOS tube.
Further, resistance R2, institute are equipped between the source electrode of first NMOS tube and the grid of the first PMOS tube
It states and is equipped with resistance R3 between the source electrode of the second NMOS tube and the grid of the second PMOS tube.
Further, the clamp circuit is to constitute from third NMOS tube and the 4th NMOS transistor conduction to reciprocal coupling,
The source electrode and the drain electrode of the 4th NMOS tube, grid of middle third NMOS tube are coupled to one end of clamp circuit, the source of the 4th NMOS tube altogether
The drain electrode of pole and third NMOS tube, grid are coupled to the other end of clamp circuit altogether.
Another technical solution of the present invention is：The protection circuit of differential pair tube, related differential pair tube have
5th NMOS tube, the 6th NMOS tube and current source, and the common source of two NMOS tubes and current source are connected on node A, feature
It is：The protection circuit is made of the PMOS tube that clamp circuit and two total grid are connected in node A, wherein the 5th PMOS tube
Source electrode is mutually coupled with the grid of the 5th NMOS tube, one end of clamp circuit, and the drain electrode of the 5th PMOS tube is connected with Vin+；6th
The source electrode of PMOS tube is mutually coupled with the grid of the 6th NMOS tube, the other end of clamp circuit, and the drain electrode of the 6th PMOS tube with
Vin- is connected.
Further, the clamp circuit is to constitute from the 7th NMOS tube and the 8th NMOS transistor conduction to reciprocal coupling,
In the 7th NMOS tube source electrode and the drain electrode of the 8th NMOS tube, grid be coupled to one end of clamp circuit, the source of the 8th NMOS tube altogether
The drain electrode of pole and the 7th NMOS tube, grid are coupled to the other end of clamp circuit altogether.
Further, branch where the 7th NMOS tube contains n concatenated NMOS tubes in the clamp circuit, and the 8th
Branch where NMOS tube contains n concatenated NMOS tubes, and n is the positive integer greater than 1.
Further, the clamp circuit is to be connected from the 7th PMOS tube and the 8th PMOS tube to reciprocal coupling to constitute,
In the 7th PMOS tube source electrode and the drain electrode of the 8th PMOS tube, grid be coupled to one end of clamp circuit, the source of the 8th PMOS tube altogether
The drain electrode of pole and the 7th PMOS tube, grid are coupled to the other end of clamp circuit altogether.
The present invention protects the application of circuit, has substantive distinguishing features outstanding and significant progress：By improveing difference
Clamp circuit in tube protective circuit is connected and composed, in CMOS technology, reduces the area of clamp circuit, furthermore it is preferred that
With differential pair tube same type device, input can be offset to pipe technique change, inhibit to input the electric leakage to pipe with the sensitivity of technique
Degree.
Detailed description of the invention
Fig. 1 is a kind of general introduction structural schematic diagram of differential pair tube protective circuit of the present invention.
Fig. 2 is that the present invention is based on the structural schematic diagrams of Fig. 1 first embodiment.
Fig. 3 is that the present invention is based on the structural schematic diagrams of mono- preferred embodiment of Fig. 2.
Fig. 4 is that the present invention is based on the structural schematic diagrams of another preferred embodiment of Fig. 2.
Fig. 5 is that the present invention is based on the structural schematic diagrams of Fig. 2 another preferred embodiment.
Fig. 6 is that the present invention is based on the structural schematic diagrams of Fig. 1 second embodiment.
Fig. 7 is the general introduction structural schematic diagram of another differential pair tube protective circuit of the invention.
Specific embodiment
Differential pair tube in the present invention includes PMOS differential pair pipe and NMOS differential to pipe, following embodiment differential pair tube
Protection circuit respectively corresponds PMOS differential pair pipe or NMOS differential to pipe.
It is the protection circuit for PMOS differential pair pipe first.The present invention is to the input to protection circuit such as Fig. 1 institute of pipe
Show.From the point of view of the basis of the differential pair tube constitutes general introduction, there are the first PMOS tube, the second PMOS tube and current source, and two
The common source of PMOS tube connects with current source, the grid of two PMOS tube connects with Vin- and Vin+ respectively.Particularly, of the invention
The innovation of circuit is protected to be made of the NMOS tube that clamp circuit and two total grid are connected in node A, wherein the source of the first NMOS tube
Pole is mutually coupled with the grid of the first PMOS tube, one end of clamp circuit, and the drain electrode of the first NMOS tube is connected with Vin+；Second
The source electrode of NMOS tube is mutually coupled with the grid of the second PMOS tube, the other end of clamp circuit, and the drain electrode of the second NMOS tube with
Vin- is connected, which is to have CMOS technology that resulting be connected to reciprocal coupling unit is made.In normal work,
The voltage of Vin+ and Vin- is very close to two NMOS tubes are in linear condition, are equivalent to two resistance.When Vin+ and Vin- voltage
When differing larger, clamp circuit is started working, and the pressure difference between V1 and V2 is allowed to be clamped in normal value, and protection input PMOS is poor
Divide to pipe.
As shown in Fig. 2, being that the present invention is based on the structural schematic diagrams of Fig. 1 first embodiment.From diagram as it can be seen that the clamp circuit
It is constituted to be connected from third PMOS tube and the 4th PMOS tube to reciprocal coupling, wherein the source electrode of third PMOS tube and the 4th PMOS tube
Drain electrode, grid be coupled to one end of clamp circuit altogether, the source electrode and the drain electrode of third PMOS tube, grid of the 4th PMOS tube are coupled to altogether
The other end of clamp circuit.It is smaller different from the size of the clamping action of conventional diode, two PMOS tube, be conducive to reduce
The area of integral device, and be all the device of PMOS tube type to pipe with input, technique change is identical.Input pair can be offset
Pipe technique change allows input insensitive with technique to the electric leakage of pipe.
As shown in figure 3, being that the present invention is based on the structural schematic diagrams of mono- preferred embodiment of Fig. 2.From diagram as it can be seen that clamp circuit
Branch where middle third PMOS tube contains n concatenated PMOS tube, and branch where the 4th PMOS tube contains n concatenated PMOS
Pipe, n are the positive integer greater than 1.As optimization, multiple PMOS tube are connected this improvement, the electric leakage of differential pair tube can be dropped
It is lower.
As shown in figure 4, being that the present invention is based on the structural schematic diagrams of another preferred embodiment of Fig. 2.From diagram as it can be seen that this first
Resistance R1 is equipped between PMOS tube and the common source and node A of the second PMOS tube.The voltage of resistance R1 can make two NMOS tubes
It is preferably connected in normal work, resistance is smaller.
As shown in figure 5, for the present invention is based on the structural schematic diagrams of Fig. 2 another preferred embodiment.From diagram as it can be seen that this first
Resistance R2, the source electrode and the 2nd PMOS of second NMOS tube are equipped between the source electrode of NMOS tube and the grid of the first PMOS tube
Resistance R3 is equipped between the grid of pipe.Can allowing two NMOS tubes, resistance variations are slower when off.
As shown in fig. 6, being that the present invention is based on the structural schematic diagrams of Fig. 1 second embodiment.It is visible compared to Fig. 2 from illustrating,
PMOS tube in clamp circuit is replaced for NMOS tube；Specifically from third NMOS tube and the 4th NMOS transistor conduction to reciprocal coupling
It constitutes, wherein the drain electrode of the source electrode of third NMOS tube and the 4th NMOS tube, grid are coupled to one end of clamp circuit, the 4th NMOS altogether
The source electrode and the drain electrode of third NMOS tube, grid of pipe are coupled to the other end of clamp circuit altogether.For principle based on clamper, not
It is only limitted to the advantages of PMOS tube is used in embodiment illustrated in fig. 2, NMOS tube is also ideal feasible in practical application.
Followed by for NMOS differential to the protection circuit of pipe.Similarly with aforesaid plurality of embodiment.
As shown in fig. 7, being the general introduction structural schematic diagram of another differential pair tube protective circuit of the invention.The guarantor of differential pair tube
Protection circuit, related differential pair tube have the 5th NMOS tube, the 6th NMOS tube and current source, and the common source of two NMOS tubes
Node A is connected on current source.The protection circuit is connected in node A's by clamp circuit and two total grid from the point of view of the feature book
PMOS tube composition, wherein the source electrode of the 5th PMOS tube is mutually coupled with the grid of the 5th NMOS tube, one end of clamp circuit, and the 5th
The drain electrode of PMOS tube is connected with Vin+；The source electrode of 6th PMOS tube and the grid of the 6th NMOS tube, the other end phase of clamp circuit
Coupling, and the drain electrode of the 6th PMOS tube is connected with Vin-.In normal work, the voltage of Vin+ and Vin- is very close to two
PMOS tube is in linear condition, is equivalent to two resistance.When Vin+ and Vin- voltage phase difference is larger, clamp circuit starts to act as
With, allow the pressure difference between V1 and V2 to be clamped in normal value, protection input NMOS differential to pipe.
Wherein clamp circuit is to constitute from the 7th NMOS tube and the 8th NMOS transistor conduction to reciprocal coupling, wherein the 7th NMOS
The drain electrode of the source electrode of pipe and the 8th NMOS tube, grid are coupled to one end of clamp circuit, the source electrode and the 7th of the 8th NMOS tube altogether
The drain electrode of NMOS tube, grid are coupled to the other end of clamp circuit altogether.
Similarly, branch where the 7th NMOS tube contains n concatenated NMOS tubes in the clamp circuit of above-described embodiment, and the 8th
Branch where NMOS tube contains n concatenated NMOS tubes, and n is the positive integer greater than 1.
As optional embodiment, which is similarly from the 7th PMOS tube and the 8th PMOS tube and is connected to reciprocal
Coupling is constituted, wherein the source electrode and the drain electrode of the 8th PMOS tube, grid of the 7th PMOS tube are coupled to one end of clamp circuit altogether, the 8th
The drain electrode of the source electrode of PMOS tube and the 7th PMOS tube, grid are coupled to the other end of clamp circuit altogether.
To sum up multiple embodiments combine the elaborating as it can be seen that using protection circuit of the invention of diagram, poor by improveing
Divide and clamp circuit in tube protective circuit is connected and composed, in CMOS technology, the area of clamp circuit is reduced, in addition, excellent
Choosing and differential pair tube same type device can offset input to pipe technique change, inhibit input to the electric leakage of pipe with the quick of technique
Sense degree.
In addition to the implementation, the present invention can also have other embodiment, all to use equivalent substitution or equivalent transformation shape
At technical solution, be all fallen within scope of the present invention.
Claims (10)
1. the protection circuit of differential pair tube, related differential pair tube has the first PMOS tube, the second PMOS tube and current source, and
The common source and current source of two PMOS tube are connected on node A, it is characterised in that：The protection circuit is by clamp circuit and two
Altogether grid are connected in the NMOS tube composition of node A, wherein the source electrode of the first NMOS tube and the grid of the first PMOS tube, clamp circuit
One end mutually couples, and the drain electrode of the first NMOS tube is connected with Vin+；The source electrode of second NMOS tube and the grid of the second PMOS tube, pincers
The other end of position circuit mutually couples, and the drain electrode of the second NMOS tube is connected with Vin-.
2. the protection circuit of differential pair tube according to claim 1, it is characterised in that：The clamp circuit is by third PMOS
Pipe and the 4th PMOS tube are connected to reciprocal coupling and constitute, the wherein drain electrode of the source electrode of third PMOS tube and the 4th PMOS tube, grid
It is coupled to one end of clamp circuit altogether, the source electrode and the drain electrode of third PMOS tube, grid of the 4th PMOS tube are coupled to clamp circuit altogether
The other end.
3. the protection circuit of differential pair tube according to claim 2, it is characterised in that：Third PMOS tube in the clamp circuit
Place branch contains n concatenated PMOS tube, and branch where the 4th PMOS tube contains n concatenated PMOS tube, and n is greater than 1
Positive integer.
4. the protection circuit of differential pair tube according to claim 1, it is characterised in that：First PMOS tube and the 2nd PMOS
Resistance R1 is equipped between the common source and node A of pipe.
5. the protection circuit of differential pair tube according to claim 4, it is characterised in that：The source electrode of first NMOS tube and
It is equipped with resistance R2 between the grid of one PMOS tube, the source electrode of the second NMOS tube and grid of the second PMOS tube is sets indirectly
There is resistance R3.
6. the protection circuit of differential pair tube according to claim 1, it is characterised in that：The clamp circuit is by third NMOS
Pipe and the 4th NMOS transistor conduction are constituted to reciprocal coupling, the wherein drain electrode of the source electrode of third NMOS tube and the 4th NMOS tube, grid
It is coupled to one end of clamp circuit altogether, the source electrode and the drain electrode of third NMOS tube, grid of the 4th NMOS tube are coupled to clamp circuit altogether
The other end.
7. the protection circuit of differential pair tube, related differential pair tube has the 5th NMOS tube, the 6th NMOS tube and current source, and
The common source and current source of two NMOS tubes are connected on node A, it is characterised in that：The protection circuit is by clamp circuit and two
Altogether grid are connected in the PMOS tube composition of node A, wherein the source electrode of the 5th PMOS tube and the grid of the 5th NMOS tube, clamp circuit
One end mutually couples, and the drain electrode of the 5th PMOS tube is connected with Vin+；The source electrode of 6th PMOS tube and grid, the pincers of the 6th NMOS tube
The other end of position circuit mutually couples, and the drain electrode of the 6th PMOS tube is connected with Vin-.
8. the protection circuit of differential pair tube according to claim 7, it is characterised in that：The clamp circuit is by the 7th NMOS
Pipe and the 8th NMOS transistor conduction are constituted to reciprocal coupling, wherein drain electrode, the grid of the source electrode of the 7th NMOS tube and the 8th NMOS tube
It is coupled to one end of clamp circuit altogether, the source electrode and the drain electrode of the 7th NMOS tube, grid of the 8th NMOS tube are coupled to clamp circuit altogether
The other end.
9. the protection circuit of differential pair tube according to claim 8, it is characterised in that：7th NMOS tube in the clamp circuit
Place branch contains n concatenated NMOS tubes, and branch where the 8th NMOS tube contains n concatenated NMOS tubes, and n is greater than 1
Positive integer.
10. the protection circuit of differential pair tube according to claim 7, it is characterised in that：The clamp circuit is by the 7th
PMOS tube and the 8th PMOS tube are connected to reciprocal coupling and constitute, wherein the drain electrode of the source electrode of the 7th PMOS tube and the 8th PMOS tube,
Grid is coupled to one end of clamp circuit altogether, and the source electrode and the drain electrode of the 7th PMOS tube, grid of the 8th PMOS tube are coupled to clamper electricity altogether
The other end on road.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810695577.7A CN108880488A (en) | 2018-06-29 | 2018-06-29 | The protection circuit of differential pair tube |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810695577.7A CN108880488A (en) | 2018-06-29 | 2018-06-29 | The protection circuit of differential pair tube |
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| Publication Number | Publication Date |
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| CN108880488A true CN108880488A (en) | 2018-11-23 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810695577.7A Pending CN108880488A (en) | 2018-06-29 | 2018-06-29 | The protection circuit of differential pair tube |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110166009A (en) * | 2019-04-30 | 2019-08-23 | 思瑞浦微电子科技（苏州）股份有限公司 | Input voltage-withstanding protection architecture |
| CN112825477A (en) * | 2019-11-20 | 2021-05-21 | 圣邦微电子（北京）股份有限公司 | High-voltage operational amplifier and input stage circuit thereof |
| US20210384870A1 (en) * | 2020-06-05 | 2021-12-09 | Analog Devices, Inc. | Apparatus and methods for amplifier input-overvoltage protection with low leakage current |
| CN115664356A (en) * | 2022-12-08 | 2023-01-31 | 江苏润石科技有限公司 | High-voltage input stage differential pair transistor protection circuit |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050052800A1 (en) * | 2003-09-10 | 2005-03-10 | Rohm Co., Ltd. | Semiconductor integrated circuit device |
| CN103646668A (en) * | 2013-12-26 | 2014-03-19 | 中国科学院上海微系统与信息技术研究所 | Disposable programmable memory as well as programming method and reading method of memory |
| CN105024658A (en) * | 2015-06-10 | 2015-11-04 | 思瑞浦微电子科技（苏州）有限公司 | Protection circuit of differential pair transistors |
| CN106066419A (en) * | 2015-04-20 | 2016-11-02 | 精工半导体有限公司 | Current detection circuit |
-
2018
- 2018-06-29 CN CN201810695577.7A patent/CN108880488A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050052800A1 (en) * | 2003-09-10 | 2005-03-10 | Rohm Co., Ltd. | Semiconductor integrated circuit device |
| CN103646668A (en) * | 2013-12-26 | 2014-03-19 | 中国科学院上海微系统与信息技术研究所 | Disposable programmable memory as well as programming method and reading method of memory |
| CN106066419A (en) * | 2015-04-20 | 2016-11-02 | 精工半导体有限公司 | Current detection circuit |
| CN105024658A (en) * | 2015-06-10 | 2015-11-04 | 思瑞浦微电子科技（苏州）有限公司 | Protection circuit of differential pair transistors |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110166009A (en) * | 2019-04-30 | 2019-08-23 | 思瑞浦微电子科技（苏州）股份有限公司 | Input voltage-withstanding protection architecture |
| WO2020220682A1 (en) * | 2019-04-30 | 2020-11-05 | 思瑞浦微电子科技（苏州）股份有限公司 | Input withstand voltage protection architecture |
| US11316483B2 (en) | 2019-04-30 | 2022-04-26 | 3Peak Inc. | Input voltage endurance protection architecture |
| CN110166009B (en) * | 2019-04-30 | 2022-05-13 | 思瑞浦微电子科技（苏州）股份有限公司 | Input voltage-withstanding protection framework |
| CN112825477A (en) * | 2019-11-20 | 2021-05-21 | 圣邦微电子（北京）股份有限公司 | High-voltage operational amplifier and input stage circuit thereof |
| US20210384870A1 (en) * | 2020-06-05 | 2021-12-09 | Analog Devices, Inc. | Apparatus and methods for amplifier input-overvoltage protection with low leakage current |
| CN115664356A (en) * | 2022-12-08 | 2023-01-31 | 江苏润石科技有限公司 | High-voltage input stage differential pair transistor protection circuit |
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Application publication date: 20181123 |