CN202652172U - Analog switch circuit structure - Google Patents
Analog switch circuit structure Download PDFInfo
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- CN202652172U CN202652172U CN 201120521164 CN201120521164U CN202652172U CN 202652172 U CN202652172 U CN 202652172U CN 201120521164 CN201120521164 CN 201120521164 CN 201120521164 U CN201120521164 U CN 201120521164U CN 202652172 U CN202652172 U CN 202652172U
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Abstract
The utility model relates to an analog switch circuit structure comprising an inverter circuit module, a channel pair tube circuit module and a breakpoint protection circuit module. An input terminal of the inverter circuit module is connected with a control signal input terminal (CRT). A channel pair tube circuit is connected between a signal input terminal (IN) and a signal output terminal (OUT). The channel pair tube circuit comprises a third PMOS field effect transistor (P3). An output terminal of the inverter circuit module is connected to a grid electrode of the third PMOS field effect transistor (P3). A substrate of the third PMOS field effect transistor (P3) is connected with a power supply (VDD) or the signal input terminal (IN) through the breakpoint protection circuit module. By employing the analog switch circuit structure with the above structure, leakage of an input signal to the VDD through a parasitic diode between a field effect transistor source electrode and the substrate is avoided, normal turn-off of an analog switch in the condition of power failure is realized, leakage current from the input terminal to the power supply is effectively prevented, and the analog switch circuit structure has the advantages of simple and practical structure, stable and reliable working performance, and a wide application range.
Description
Technical field
The utility model relates to the semiconductor integrated circuit design field, and particularly analog switch technical field in the semiconductor integrated circuit specifically refers to a kind of analog switching circuit structure.
Background technology
Analog switch is widely used in transmission and the selection of analog signal at present.The video of various high definitions, the transmission of audio signal have proposed more and more higher requirement to the performance of analog switch.
Traditional analog switching circuit is in order to transmit the voltage near power supply (VDD), and transmission channel adopts PMOS to be connected the symmetrical mode that connects with NMOS.The substrate of PMOS (B end) meets VDD, forms a parasitic diode between the S of PMOS and the B.When the VDD outage, when input has signal, can cause input to the electric leakage of the parasitic diode of VDD, this signal can be leaked to output simultaneously, thus analog switch can't normal turn-off.
The analog switching circuit that some are novel, CN200810203211.X is described such as Chinese patent.In order to reduce the conducting resistance of circuit, the substrate of passage PMOS is connected to input when the conducting, this analog switch the phenomenon that input signal is leaked to output can occur equally when outage.
See also shown in Fig. 1 a and Fig. 1 b, it is traditional analog switching circuit, wherein:
The supply voltage of VDD indication circuit, the ground of GND indication circuit, IN represents signal input part, OUT represents the output of signal, Vthp represents the cut-in voltage of PMOS pipe, and Vthd represents the forward conduction voltage of PMOS parasitic diode, and VGS represents that the gate source voltage of metal-oxide-semiconductor is poor.P1～Pn is the PMOS field effect transistor, and N1～Nn is the NMOS field effect transistor.S is the source electrode of metal-oxide-semiconductor field effect transistor, and B is the substrate of metal-oxide-semiconductor field effect transistor, and G is the grid of metal-oxide-semiconductor field effect transistor, and D is the drain electrode of metal-oxide-semiconductor field effect transistor.
Circuit connecting relation is as follows:
The P1 source electrode connects that IN, grid meet CP, drain electrode meets OUT; The N1 source electrode connects that IN, grid meet CN, drain electrode meets OUT; P2 and N2 form inverter, and input is connected to CN, and output is connected to CP; The substrate of all PMOS pipes meets VDD, and the substrate of all NMOS pipes meets GND.Form the parasitic diode D1 of a forward between the S of P1 and the B.
The circuit working principle is as follows:
P1 and N1 form passage to pipe.VDD is high level (supply voltage) during the circuit normal operation, and such as the need switch conduction, it is VDD that CN then is set, thereby CP is the GND(low level), P1 and N1 open, and signal is inputted from IN, exports from OUT.Such as the need stopcock, it is GND that CN then is set, thereby CP is VDD, and passage turn-offs, and signal is blocked.Form the forward diode of a parasitism between the source electrode of P1 and the substrate.When VDD did not have voltage, CP, CN were low level.At this moment, IN has signal input, and when input signal during greater than Vthd, the D1 forward conduction forms IN to the leakage current of VDD; When input signal greater than | during Vthp|, P1's | VGS|＞| Vthp|, P1 open, and input signal is leaked to output.
The utility model content
The purpose of this utility model is to have overcome above-mentioned shortcoming of the prior art, provides a kind of can guarantee the normal turn-off of analog switch in the situation that power supply is not powered, effectively prevents that input is to the leakage current of power supply, simple and practical, stable and reliable working performance, scope of application analog switching circuit structure comparatively widely.
In order to realize above-mentioned purpose, analog switching circuit structure of the present utility model has following formation:
This analog switching circuit structure; comprise that inverter circuit module and passage are to the pipe circuit module; the input of described inverter circuit module is connected with control signal input CRT; described passage is connected between signal input part IN and the signal output part OUT the pipe circuit; its main feature is; described circuit structure also comprises breakpoint protective circuit module; described passage is to comprising the 3rd PMOS field effect transistor P3 in the pipe circuit; the output of described inverter circuit module is connected with the grid of the 3rd PMOS field effect transistor P3, and the substrate of the 3rd PMOS field effect transistor P3 is connected with power vd D or signal input part IN by described breakpoint protective circuit module.
Inverter circuit module in this analog switching circuit structure comprises the first inverter and the second inverter, the input of described the first inverter is connected with control signal input CRT, and the output CN of this first inverter is connected with the input of the second inverter, and the output CP of described the second inverter is connected with the grid of described the 3rd PMOS field effect transistor P3.
The first inverter in this analog switching circuit structure comprises the 5th PMOS field effect transistor P5 and the 5th NMOS field effect transistor N5, the grid of the grid of described the 5th PMOS field effect transistor P5 and the 5th NMOS field effect transistor N5 all is connected with described control signal input CRT, the source electrode of the 5th PMOS field effect transistor P5 all is connected with power vd D with substrate, the drain electrode of the 5th PMOS field effect transistor P5 is connected with the output CN of this first inverter and the drain electrode of described the 5th NMOS field effect transistor N5 respectively, and substrate and the source grounding of the 5th NMOS field effect transistor N5.
The second inverter in this analog switching circuit structure can comprise the 4th PMOS field effect transistor P4 and the 4th NMOS field effect transistor N4, the grid of the grid of described the 4th PMOS field effect transistor P4 and the 4th NMOS field effect transistor N4 all is connected with the output CN of described the first inverter, the source electrode of the 4th PMOS field effect transistor P4 all is connected with the substrate of described the 3rd PMOS field effect transistor P3 with substrate, the drain electrode of the 4th PMOS field effect transistor P4 is connected with the output CP of this second inverter and the drain electrode of described the 4th NMOS field effect transistor N4 respectively, and substrate and the source grounding of the 4th NMOS field effect transistor N4.
Breakpoint protective circuit module in this analog switching circuit structure can comprise the 6th PMOS field effect transistor P6 and the 7th PMOS field effect transistor P7, the source electrode of described the 6th PMOS field effect transistor P6 is connected with described signal input part IN, the drain electrode of the 6th PMOS field effect transistor P6 all is connected with the substrate of described the 3rd PMOS field effect transistor P3 with substrate, and the grid of the 6th PMOS field effect transistor P6 is connected with power vd D; The source electrode of described the 7th PMOS field effect transistor P7 is connected with power vd D, the drain electrode of the 7th PMOS field effect transistor P7 all is connected with the substrate of described the 3rd PMOS field effect transistor P3 with substrate, and the grid of the 7th PMOS field effect transistor P7 is connected with the output CP of described the second inverter.
Breakpoint protective circuit module in this analog switching circuit structure also can comprise the 16 PMOS field effect transistor P16 and the 17 PMOS field effect transistor P17, the source electrode of described the 16 PMOS field effect transistor P16 is connected with described signal input part IN, the drain electrode of the 16 PMOS field effect transistor P16 all is connected with the substrate of described the 3rd PMOS field effect transistor P3 with substrate, and the grid of the 16 PMOS field effect transistor P16 is connected with power vd D; The source electrode of described the 17 PMOS field effect transistor P17 is connected with described signal input part IN, the drain electrode of the 17 PMOS field effect transistor P17 all is connected with the substrate of described the 3rd PMOS field effect transistor P3 with substrate, and the grid of the 17 PMOS field effect transistor P17 is connected with the output CP of described the second inverter.
The second inverter in this analog switching circuit structure also can comprise the 9th PMOS field effect transistor P9 and the 9th NMOS field effect transistor N9, the grid of the grid of described the 9th PMOS field effect transistor P9 and the 9th NMOS field effect transistor N9 all is connected with the output CN of described the first inverter, the source electrode of the 9th PMOS field effect transistor P9 all is connected with power vd D with substrate, the drain electrode of the 9th PMOS field effect transistor P9 is connected with the output CP of this second inverter and the drain electrode of described the 9th NMOS field effect transistor N9 respectively, and substrate and the source grounding of the 9th NMOS field effect transistor N9.
Breakpoint protective circuit module in this analog switching circuit structure can comprise the 11 PMOS field effect transistor P11 and the 12 PMOS field effect transistor P12 accordingly, the source electrode of described the 11 PMOS field effect transistor P11 is connected with described signal input part IN, the drain electrode of the 11 PMOS field effect transistor P11 all is connected with the substrate of described the 3rd PMOS field effect transistor P3 with substrate, and the grid of the 11 PMOS field effect transistor P11 is connected with the output CP of described the second inverter; The source electrode of described the 12 PMOS field effect transistor P12 all is connected with power vd D with substrate, the drain electrode of the 12 PMOS field effect transistor P12 is connected with the substrate of described the 3rd PMOS field effect transistor P3, and the grid of the 12 PMOS field effect transistor P12 is connected with the output CN of described the first inverter.
Passage in this analog switching circuit structure also comprises the 3rd NMOS field effect transistor N3 to the pipe circuit module, the source electrode of the source electrode of described the 3rd PMOS field effect transistor P3 and the 3rd NMOS field effect transistor N3 all is connected with described signal input part IN, the drain electrode of the drain electrode of the 3rd PMOS field effect transistor P3 and the 3rd NMOS field effect transistor N3 all is connected with described signal output part OUT, the grid of the 3rd NMOS field effect transistor N3 is connected with the output CN of described the first inverter, and the substrate ground connection of the 3rd NMOS field effect transistor N3.
Adopted the analog switching circuit structure of this utility model, owing to wherein directly the substrate of passage PMOS field effect transistor is not connected to power vd D, thereby has effectively avoided input signal to leak electricity to VDD by the parasitic diode between passage PMOS field effect transistor S and the B; And the grid control level of passage PMOS field effect transistor changed by input signal control, after supply voltage cuts off, when input signal is arranged, assurance passage PMOS field effect transistor can not opened, thereby realize the normal turn-off of the analog switch in the power cut-off situation, effectively prevented the leakage current of input to power supply, simple and practical, stable and reliable working performance, the scope of application are comparatively extensive.
Description of drawings
Fig. 1 a and 1b are analog switching circuit schematic diagram of the prior art.
Fig. 2 a and 2b are the first execution mode circuit theory diagrams of analog switching circuit structure of the present utility model.
Fig. 3 a and 3b are the second execution mode circuit theory diagrams of analog switching circuit structure of the present utility model.
Fig. 4 a and 4b are the third execution mode circuit theory diagrams of analog switching circuit structure of the present utility model.
Embodiment
In order more clearly to understand technology contents of the present utility model, describe in detail especially exemplified by following examples.
See also Fig. 2 a; 2b to Fig. 4 a; shown in the 4b; this analog switching circuit structure; comprise that inverter circuit module and passage are to the pipe circuit module; the input of described inverter circuit module is connected with control signal input CRT; described passage is connected between signal input part IN and the signal output part OUT the pipe circuit; wherein; described circuit structure also comprises breakpoint protective circuit module; described passage is to comprising the 3rd PMOS field effect transistor P3 in the pipe circuit; the output of described inverter circuit module is connected with the grid of the 3rd PMOS field effect transistor P3, and the substrate of the 3rd PMOS field effect transistor P3 is connected with power vd D or signal input part IN by described breakpoint protective circuit module.
Wherein, described inverter circuit module comprises the first inverter and the second inverter, the input of described the first inverter is connected with control signal input CRT, and the output CN of this first inverter is connected with the input of the second inverter, and the output CP of described the second inverter is connected with the grid of described the 3rd PMOS field effect transistor P3.
Described the first inverter comprises the 5th PMOS field effect transistor P5 and the 5th NMOS field effect transistor N5, the grid of the grid of described the 5th PMOS field effect transistor P5 and the 5th NMOS field effect transistor N5 all is connected with described control signal input CRT, the source electrode of the 5th PMOS field effect transistor P5 all is connected with power vd D with substrate, the drain electrode of the 5th PMOS field effect transistor P5 is connected with the output CN of this first inverter and the drain electrode of described the 5th NMOS field effect transistor N5 respectively, and substrate and the source grounding of the 5th NMOS field effect transistor N5.
As the first execution mode of the present utility model, the second inverter in this analog switching circuit structure can comprise the 4th PMOS field effect transistor P4 and the 4th NMOS field effect transistor N4, the grid of the grid of described the 4th PMOS field effect transistor P4 and the 4th NMOS field effect transistor N4 all is connected with the output CN of described the first inverter, the source electrode of the 4th PMOS field effect transistor P4 all is connected with the substrate of described the 3rd PMOS field effect transistor P3 with substrate, the drain electrode of the 4th PMOS field effect transistor P4 is connected with the output CP of this second inverter and the drain electrode of described the 4th NMOS field effect transistor N4 respectively, and substrate and the source grounding of the 4th NMOS field effect transistor N4.
Simultaneously, described breakpoint protective circuit module can comprise the 6th PMOS field effect transistor P6 and the 7th PMOS field effect transistor P7, the source electrode of described the 6th PMOS field effect transistor P6 is connected with described signal input part IN, the drain electrode of the 6th PMOS field effect transistor P6 all is connected with the substrate of described the 3rd PMOS field effect transistor P3 with substrate, and the grid of the 6th PMOS field effect transistor P6 is connected with power vd D; The source electrode of described the 7th PMOS field effect transistor P7 is connected with power vd D, the drain electrode of the 7th PMOS field effect transistor P7 all is connected with the substrate of described the 3rd PMOS field effect transistor P3 with substrate, and the grid of the 7th PMOS field effect transistor P7 is connected with the output CP of described the second inverter.
As the second execution mode of the present utility model, the second inverter in this analog switching circuit structure also can comprise the 9th PMOS field effect transistor P9 and the 9th NMOS field effect transistor N9, the grid of the grid of described the 9th PMOS field effect transistor P9 and the 9th NMOS field effect transistor N9 all is connected with the output CN of described the first inverter, the source electrode of the 9th PMOS field effect transistor P9 all is connected with power vd D with substrate, the drain electrode of the 9th PMOS field effect transistor P9 is connected with the output CP of this second inverter and the drain electrode of described the 9th NMOS field effect transistor N9 respectively, and substrate and the source grounding of the 9th NMOS field effect transistor N9.
Wherein, described breakpoint protective circuit module can comprise the 11 PMOS field effect transistor P11 and the 12 PMOS field effect transistor P12 accordingly, the source electrode of described the 11 PMOS field effect transistor P11 is connected with described signal input part IN, the drain electrode of the 11 PMOS field effect transistor P11 all is connected with the substrate of described the 3rd PMOS field effect transistor P3 with substrate, and the grid of the 11 PMOS field effect transistor P11 is connected with the output CP of described the second inverter; The source electrode of described the 12 PMOS field effect transistor P12 all is connected with power vd D with substrate, the drain electrode of the 12 PMOS field effect transistor P12 is connected with the substrate of described the 3rd PMOS field effect transistor P3, and the grid of the 12 PMOS field effect transistor P12 is connected with the output CN of described the first inverter.
As the third execution mode of the present utility model, the second inverter in this analog switching circuit structure can comprise the 4th PMOS field effect transistor P4 and the 4th NMOS field effect transistor N4, the grid of the grid of described the 4th PMOS field effect transistor P4 and the 4th NMOS field effect transistor N4 all is connected with the output CN of described the first inverter, the source electrode of the 4th PMOS field effect transistor P4 all is connected with the substrate of described the 3rd PMOS field effect transistor P3 with substrate, the drain electrode of the 4th PMOS field effect transistor P4 is connected with the output CP of this second inverter and the drain electrode of described the 4th NMOS field effect transistor N4 respectively, and substrate and the source grounding of the 4th NMOS field effect transistor N4.
Described breakpoint protective circuit module also can comprise the 16 PMOS field effect transistor P16 and the 17 PMOS field effect transistor P17 accordingly, the source electrode of described the 16 PMOS field effect transistor P16 is connected with described signal input part IN, the drain electrode of the 16 PMOS field effect transistor P16 all is connected with the substrate of described the 3rd PMOS field effect transistor P3 with substrate, and the grid of the 16 PMOS field effect transistor P16 is connected with power vd D; The source electrode of described the 17 PMOS field effect transistor P17 is connected with described signal input part IN, the drain electrode of the 17 PMOS field effect transistor P17 all is connected with the substrate of described the 3rd PMOS field effect transistor P3 with substrate, and the grid of the 17 PMOS field effect transistor P17 is connected with the output CP of described the second inverter.
Moreover, passage in this analog switching circuit structure also comprises the 3rd NMOS field effect transistor N3 to the pipe circuit module, the source electrode of the source electrode of described the 3rd PMOS field effect transistor P3 and the 3rd NMOS field effect transistor N3 all is connected with described signal input part IN, the drain electrode of the drain electrode of the 3rd PMOS field effect transistor P3 and the 3rd NMOS field effect transistor N3 all is connected with described signal output part OUT, the grid of the 3rd NMOS field effect transistor N3 is connected with the output CN of described the first inverter, and the substrate ground connection of the 3rd NMOS field effect transistor N3.
In the middle of reality is used, see also shown in Fig. 2 a, the 2b, it is the circuit way of realization of the first embodiment of the present utility model.
Its circuit connecting relation is as follows:
P5 and N5 form inverter, and input connects CTR, and output connects CN; P4 and N4 form inverter, and input connects CN, and output connects CP, and the substrate of P4 is connected B2 with source electrode; P3 is connected source electrode and is connected IN with N3, drain electrode connects OUT, and the substrate of P3 connects B2, and grid connects CP, and the substrate of N3 connects GND, and grid connects CN; The source electrode of P6 meets IN, and drain electrode and substrate meet B2, and grid meets VDD; The source electrode of P7 meets VDD, and drain electrode and substrate meet B2, and grid meets CP.Form the parasitic diode D2 of a forward between the S of P3 and the B.
The circuit working principle is as follows:
P3 and N3 form passage to pipe.During the circuit normal operation, VDD is high level.Such as the need switch conduction, it is GND that CTR then is set, thereby CN is VDD, and CP is GND, and P3 and N3 open, and signal is inputted from IN, exports from OUT.
When the needs stopcock, it is VDD that CTR is set, thereby CN is GND, and N3 turn-offs.Form the parasitic diode of forward between the S of P7, P6 and the B, its forward conduction voltage is Vthd.
(1) when | Vthp|＞Vthd, B2=VDD-Vthd, thus P4 opens CP=B2.Input signal IN maximum is VDD, thus the VGS maximum of P3 be CP-IN=Vthd＜| Vthp|, P3 turn-off, and analog switch turn-offs;
(2) when | Vthp|＜Vthd, B2=VDD-Vthd=CP, this moment P7 | VGS|=Vthd＞| Vthp|, so P7 opens, B2 voltage raises, CP raises with B2 voltage, until B2=CP＜VDD-Vthp, P7 turn-offs, so P3 | the VGS| maximum be CP-IN＜| VDD-Vthp-VDD|=|Vthp|, P3 turn-offs, and analog switch turn-offs.
Work as power cut-off, during VDD=0, CN=0V.If this moment, the IN end had the signal input.
(1) input signal IN＜| Vthp|, then P3 | VGS|=IN-CP＜| Vthp|, P3 turn-offs, analog switch turn-offs;
(2) when input signal IN＞| Vthp|, thus P6 opens, B2=IN, thus P4 opens, CP=B2, the VGS=CP-IN=0V of P3, P3 is turned off, analog switch turn-offs.Simultaneously because CP=B2, the VGS=0V of P7, P7 turn-offs, and input signal can not form the electric leakage to VDD.
See also shown in Fig. 3 a and the 3b, it is the second execution mode of the present utility model again, also is the analog switching circuit of low on-resistance.
Circuit connecting relation is as follows:
P9 and N9 form inverter, and input connects CN, and output connects CP; P10 and N10 form inverter, and input connects CTR, and output connects CN; P8 is connected source electrode and is connected IN with N8, drain electrode connects OUT, and the substrate of P8 connects B3, and grid connects CP, and the substrate of N8 connects GND, and grid connects CN; The source electrode of P11 meets IN, and drain electrode and substrate meet B3, and grid meets CP; The drain electrode of P12 meets B3, and source electrode and substrate meet VDD, and grid meets CN.
The circuit working principle is as follows:
P8 and N8 form passage to pipe.During the circuit normal operation, VDD is high level, and such as the need switch conduction, it is GND that CTR is set, thereby CN is VDD, and CP is GND, and P8, P11, N8 open, and P12 closes, and signal is inputted from IN, exports from OUT.The substrate of P8 is received IN by P11, and conducting resistance is reduced.Turn-off such as the need switch, it is VDD that CTR then is set, thereby CN is GND, and P12 opens, and P11, N9 turn-off.Because CN is GND, so CP is VDD, P11 turn-offs, and the substrate of P8 is connected to VDD, and P8 turn-offs.Analog switch turn-offs, and signal is blocked.
When power cut-off, CTR=CN=CP=GND=VDD, in case IN has the signal input, then P11 opens, B3=IN.Thereby P8 opens, and leakage signal is to output OUT.Simultaneously, P12 opens, and input signal forms the leakage current to VDD.
See also shown in Fig. 4 a and the 4b, it is the third execution mode of the present utility model again, has wherein also realized a kind of analog switching circuit of low on-resistance.
Circuit connecting relation is as follows:
P15 and N15 form inverter, and input connects CTR, and output connects CN; P14 and N14 form inverter, and input connects CN, and output connects CP, and the substrate of P14 is connected B2 with source electrode; P13 is connected source electrode and is connected IN with N13, drain electrode connects OUT, and the substrate of P13 connects B4, and grid connects CP, and the substrate of N13 connects GND, and grid connects CN; The source electrode of P16 meets IN, and drain electrode and substrate meet B4, and grid meets VDD; The source electrode of P17 meets VDD, and drain electrode and substrate meet B4, and grid meets CP.
The circuit working principle is as follows:
P13 and N13 form passage to pipe.During the circuit normal operation, VDD is high level.Such as the need switch conduction, it is GND that CTR then is set, thereby CN is VDD, and CP is GND, and P13, P17, N13 open, and signal is inputted from IN, exports from OUT.At this moment, the substrate of P13 is connected to IN by P17, has reduced conducting resistance.
When the needs stopcock, it is VDD that CTR is set, thereby CN is GND, and N13 turn-offs.
Form the parasitic diode of forward between the S of P17, P16 and the B, its forward conduction voltage is Vthd.
(1) input signal IN＜| during Vthp|, P13's | VGS|=|IN-CP|＜| Vthp|, P13 turn-off, and analog switch turn-offs.
(2) when input signal IN＞| Vthp|, | during Vthp|＞Vthd, P13's | the maximum of VGS| is IN-CP=VDD-CP.If VDD-CP＜| Vthp|, then P13 turn-offs, and analog switch turn-offs.If VDD-CP＞| Vthp|, P17 opens, and B4 voltage raises, and P14 opens, CP=B4, until VDD-CP＜| Vthp|, P17 turn-offs.Thereby P13's | VGS|＜| Vthp|, P13 turn-offs, and analog switch turn-offs.
(3) when input signal IN＞| Vthp|, | during Vthp|＜Vthd, P17, P14 open, B4=CP=IN, this moment P13 VGS=IN-CP=0, P13 turn-offs, analog switch turn-offs.
Work as power cut-off, during VDD=0, CTR=CN=0V.If this moment, the IN end had the signal input.
(1) input signal IN＜| during Vthp|, P13 then | VGS|=IN-CP＜| Vthp|, P13 turn-offs, analog switch turn-offs, and can not form IN to the electric leakage of VDD simultaneously;
(2) when input signal IN＞| during Vthp|, P16 opens, B4=IN, thereby P4 opens, CP=B2=IN, thereby the VGS=CP-IN=0V of P13, P13 is turned off, analog switch turn-offs.Simultaneously can not form IN to the electric leakage of VDD.
In analog switching circuit of the present utility model, can realize the normal turn-off of switch in the power cut-off situation, and prevent that input is to the leakage current of power supply.
Basic practice wherein is directly the substrate of passage PMOS pipe not to be connected to power supply, by a power-off protection structure its substrate is connected to power supply, to prevent under the powering-off state that input signal is to the electric leakage of power supply.
Wherein, the G of passage PMOS pipe end control level and underlayer voltage are changed by input signal control.When the supply voltage outage, when input has signal, assurance passage PMOS pipe | VGS| is less than its cut-in voltage, to realize the normal turn-off of the analog switch in the power cut-off situation.
Under the normal operation, the substrate of passage PMOS pipe is connected to power supply (having disclosed a kind of circuit implementation of employing PMOS as switch such as Fig. 2 a and 2b) by a switch.In the power cut-off situation, substrate and power supply disconnection with passage PMOS prevent that input signal is to the electric leakage of power supply.
Under the normal operation, also the substrate of passage PMOS can be connected to input by a construction of switch (having disclosed wherein a kind of circuit implementation such as Fig. 4 a and 4b), to reduce conducting resistance.In the power cut-off situation, owing to do not exist input to the circuit path of power supply, can not form input to the leakage current of VDD.
Adopted above-mentioned analog switching circuit structure, owing to wherein directly the substrate of passage PMOS field effect transistor is not connected to power vd D, thus effectively avoided input signal to leak electricity to VDD by the parasitic diode between passage PMOS field effect transistor S and the B; And the grid control level of passage PMOS field effect transistor changed by input signal control, after supply voltage cuts off, when input signal is arranged, assurance passage PMOS field effect transistor can not opened, thereby realize the normal turn-off of the analog switch in the power cut-off situation, effectively prevented the leakage current of input to power supply, simple and practical, stable and reliable working performance, the scope of application are comparatively extensive.
In this specification, the utility model is described with reference to its specific embodiment.But, still can make various modifications and conversion obviously and not deviate from spirit and scope of the present utility model.Therefore, specification and accompanying drawing are regarded in an illustrative, rather than a restrictive.
Claims (9)
1. analog switching circuit structure; comprise that inverter circuit module and passage are to the pipe circuit module; the input of described inverter circuit module is connected with control signal input (CRT); described passage is connected between signal input part (IN) and the signal output part (OUT) the pipe circuit; it is characterized in that; described circuit structure also comprises breakpoint protective circuit module; described passage is to comprising the 3rd PMOS field effect transistor (P3) in the pipe circuit; the output of described inverter circuit module is connected with the grid of the 3rd PMOS field effect transistor (P3), and the substrate of the 3rd PMOS field effect transistor (P3) is connected with power supply (VDD) or signal input part (IN) by described breakpoint protective circuit module.
2. analog switching circuit structure according to claim 1, it is characterized in that, described inverter circuit module comprises the first inverter and the second inverter, the input of described the first inverter is connected with control signal input (CRT), and the output of this first inverter (CN) is connected with the input of the second inverter, and the output of described the second inverter (CP) is connected with the grid of described the 3rd PMOS field effect transistor (P3).
3. analog switching circuit structure according to claim 2, it is characterized in that, described the first inverter comprises the 5th PMOS field effect transistor (P5) and the 5th NMOS field effect transistor (N5), the grid of the grid of described the 5th PMOS field effect transistor (P5) and the 5th NMOS field effect transistor (N5) all is connected with described control signal input (CRT), the source electrode of the 5th PMOS field effect transistor (P5) all is connected with power supply (VDD) with substrate, the drain electrode of the 5th PMOS field effect transistor (P5) is connected with the output (CN) of this first inverter and the drain electrode of described the 5th NMOS field effect transistor (N5) respectively, and substrate and the source grounding of the 5th NMOS field effect transistor (N5).
4. analog switching circuit structure according to claim 2, it is characterized in that, described the second inverter comprises the 4th PMOS field effect transistor (P4) and the 4th NMOS field effect transistor (N4), the grid of the grid of described the 4th PMOS field effect transistor (P4) and the 4th NMOS field effect transistor (N4) all is connected with the output (CN) of described the first inverter, the source electrode of the 4th PMOS field effect transistor (P4) all is connected with the substrate of described the 3rd PMOS field effect transistor (P3) with substrate, the drain electrode of the 4th PMOS field effect transistor (P4) is connected with the output (CP) of this second inverter and the drain electrode of described the 4th NMOS field effect transistor (N4) respectively, and substrate and the source grounding of the 4th NMOS field effect transistor (N4).
5. analog switching circuit structure according to claim 4, it is characterized in that, described breakpoint protective circuit module comprises the 6th PMOS field effect transistor (P6) and the 7th PMOS field effect transistor (P7), the source electrode of described the 6th PMOS field effect transistor (P6) is connected with described signal input part (IN), the drain electrode of the 6th PMOS field effect transistor (P6) all is connected with the substrate of described the 3rd PMOS field effect transistor (P3) with substrate, and the grid of the 6th PMOS field effect transistor (P6) is connected with power supply (VDD); The source electrode of described the 7th PMOS field effect transistor (P7) is connected with power supply (VDD), the drain electrode of the 7th PMOS field effect transistor (P7) all is connected with the substrate of described the 3rd PMOS field effect transistor (P3) with substrate, and the grid of the 7th PMOS field effect transistor (P7) is connected with the output (CP) of described the second inverter.
6. analog switching circuit structure according to claim 4, it is characterized in that, described breakpoint protective circuit module comprises the 16 PMOS field effect transistor (P16) and the 17 PMOS field effect transistor (P17), the source electrode of described the 16 PMOS field effect transistor (P16) is connected with described signal input part (IN), the drain electrode of the 16 PMOS field effect transistor (P16) all is connected with the substrate of described the 3rd PMOS field effect transistor (P3) with substrate, and the grid of the 16 PMOS field effect transistor (P16) is connected with power supply (VDD); The source electrode of described the 17 PMOS field effect transistor (P17) is connected with described signal input part (IN), the drain electrode of the 17 PMOS field effect transistor (P17) all is connected with the substrate of described the 3rd PMOS field effect transistor (P3) with substrate, and the grid of the 17 PMOS field effect transistor (P17) is connected with the output (CP) of described the second inverter.
7. analog switching circuit structure according to claim 2, it is characterized in that, described the second inverter comprises the 9th PMOS field effect transistor (P9) and the 9th NMOS field effect transistor (N9), the grid of the grid of described the 9th PMOS field effect transistor (P9) and the 9th NMOS field effect transistor (N9) all is connected with the output (CN) of described the first inverter, the source electrode of the 9th PMOS field effect transistor (P9) all is connected with power supply (VDD) with substrate, the drain electrode of the 9th PMOS field effect transistor (P9) is connected with the output (CP) of this second inverter and the drain electrode of described the 9th NMOS field effect transistor (N9) respectively, and substrate and the source grounding of the 9th NMOS field effect transistor (N9).
8. analog switching circuit structure according to claim 7, it is characterized in that, described breakpoint protective circuit module comprises the 11 PMOS field effect transistor (P11) and the 12 PMOS field effect transistor (P12), the source electrode of described the 11 PMOS field effect transistor (P11) is connected with described signal input part (IN), the drain electrode of the 11 PMOS field effect transistor (P11) all is connected with the substrate of described the 3rd PMOS field effect transistor (P3) with substrate, and the grid of the 11 PMOS field effect transistor (P11) is connected with the output (CP) of described the second inverter; The source electrode of described the 12 PMOS field effect transistor (P12) all is connected with power supply (VDD) with substrate, the drain electrode of the 12 PMOS field effect transistor (P12) is connected with the substrate of described the 3rd PMOS field effect transistor (P3), and the grid of the 12 PMOS field effect transistor (P12) is connected with the output (CN) of described the first inverter.
9. each described analog switching circuit structure in 8 according to claim 2, it is characterized in that, described passage also comprises the 3rd NMOS field effect transistor (N3) to the pipe circuit module, the source electrode of the source electrode of described the 3rd PMOS field effect transistor (P3) and the 3rd NMOS field effect transistor (N3) all is connected with described signal input part (IN), the drain electrode of the drain electrode of the 3rd PMOS field effect transistor (P3) and the 3rd NMOS field effect transistor (N3) all is connected with described signal output part (OUT), the grid of the 3rd NMOS field effect transistor (N3) is connected with the output (CN) of described the first inverter, and the substrate ground connection of the 3rd NMOS field effect transistor (N3).
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120521164 CN202652172U (en) | 2011-12-13 | 2011-12-13 | Analog switch circuit structure |
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| CN 201120521164 CN202652172U (en) | 2011-12-13 | 2011-12-13 | Analog switch circuit structure |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103166616A (en) * | 2011-12-13 | 2013-06-19 | 无锡华润矽科微电子有限公司 | Simulative switch circuit structure |
| CN105700610A (en) * | 2016-01-29 | 2016-06-22 | 上海华虹宏力半导体制造有限公司 | Ldo circuit |
| CN107094013A (en) * | 2017-04-17 | 2017-08-25 | 电子科技大学 | A kind of transmission gate circuit |
| CN110232040A (en) * | 2019-05-23 | 2019-09-13 | 上海艾为电子技术股份有限公司 | Analog switch and electronic equipment |
| CN112003594A (en) * | 2020-08-26 | 2020-11-27 | 电子科技大学 | Low-power-consumption dynamic comparator circuit |
-
2011
- 2011-12-13 CN CN 201120521164 patent/CN202652172U/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103166616A (en) * | 2011-12-13 | 2013-06-19 | 无锡华润矽科微电子有限公司 | Simulative switch circuit structure |
| CN103166616B (en) * | 2011-12-13 | 2016-09-14 | 无锡华润矽科微电子有限公司 | Analog switching circuit structure |
| CN105700610A (en) * | 2016-01-29 | 2016-06-22 | 上海华虹宏力半导体制造有限公司 | Ldo circuit |
| CN107094013A (en) * | 2017-04-17 | 2017-08-25 | 电子科技大学 | A kind of transmission gate circuit |
| CN110232040A (en) * | 2019-05-23 | 2019-09-13 | 上海艾为电子技术股份有限公司 | Analog switch and electronic equipment |
| CN112003594A (en) * | 2020-08-26 | 2020-11-27 | 电子科技大学 | Low-power-consumption dynamic comparator circuit |
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Address after: 214135 -6, Linghu Avenue, Wuxi Taihu international science and Technology Park, Wuxi, Jiangsu, China, 180 Patentee after: China Resources micro integrated circuit (Wuxi) Co., Ltd Address before: No.180-22, Linghu Avenue, Wuxi, Jiangsu 214000 Patentee before: WUXI CHINA RESOURCES SEMICO Co.,Ltd. |
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