CN201185410Y

CN201185410Y - Control circuit for analog switch in a chip

Info

Publication number: CN201185410Y
Application number: CNU2008200564502U
Authority: CN
Inventors: 戴忠伟
Original assignee: BROADCHIP TECHNOLOGY GROUP Ltd
Current assignee: Core electronic technology (Shanghai) Limited by Share Ltd
Priority date: 2008-03-21
Filing date: 2008-03-21
Publication date: 2009-01-21
Anticipated expiration: 2018-03-21

Abstract

The utility model relates to an analog switch control circuit in a chip, which consists of a first NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube; wherein, grid electrodes of the second PMOS tube and the third PMOS tube is connected with a grid electrode of the first PMOS tube; source electrodes of the second PMOS tube and the third PMOS tube are connected with a substrate, and are connected with a substrate of the first PMOS tube and a drain electrode of the fourth PMOS tube; drain electrodes of the second PMOS tube and the third PMOS tube are connected respectively with a source electrode and a drain electrode of the PMOS tube; a source electrode of the fourth PMOS tube is connected with a VDD. Compared with the prior technology, the analog switch control circuit has the advantages that the drain circuit is reduced to the minimum after the switch is cut off, the on-resistance is reduced to the minimum after the switch is turned on, and the flatness of the resistor is achieved to the optimum.

Description

Analog switch control circuit in the chip

Technical field

The utility model relates to a kind of chip, relates in particular to ON-OFF control circuit in this chip.

Background technology

As seen from Figure 1: cmos switch is made up of two parts in the prior art, and NMOS pipe N1 and PMOS pipe P1, the switch of NMOS are that the voltage by grid 2 just determines.NMOS pipe N1 grid 2 is moved high level VDD in the work, and NMOS pipe N1 opens, and grid 2 is moved low level GND to, and NMOS turn-offs, and the grid 5 of PMOS pipe P1 is moved low level GND to, and PMOS pipe P1 opens, and grid 5 is moved high level VDD to, and PMOS manages shutoff.

Owing to adopt P ^-The CMOS technology of substrate is so the substrate of NMOS pipe is P ^-4 ground connection GND and the substrate 6 of PMOS pipe is the N trap all the time, its voltage floats. and general design at present is source 3 ends that meet VDD or connect it; If connect its source end, the cut-in voltage VTP of PMOS pipe can reduce, the leading resistance and can diminish of corresponding PMOS pipe, and this is favourable to switch conduction; Like this connection also brings a problem. switch when turn-offing (5 meet VDD) because 1.3 terminal voltages uncertain, just might cause 1 end than 3 terminal voltage height, to be 1 end will conducting form path to the diode of N trap 6 ends to such result, and switch just can't turn-off; If terminate to 1 end with 6, also have same situation and take place.Another line construction connects N trap 6 VDD (Fig. 2) exactly, just above leaky can not occur like this when turn-offing.But may directly can produce another bad effect like this: when switch conduction (5 meet GND), because N trap 6 meets VDD, the voltage of 1 pin and 3 pin can change to VDD from GND, the cut-in voltage VTP that will make the PMOS pipe like this is owing to body effect increases, thereby the conducting resistance that makes the PMOS pipe becomes big, and the conducting resistance excursion also becomes greatly, thereby influences the flatness of resistance.

Summary of the invention

The utility model technical issues that need to address have provided analog switch control circuit in a kind of chip, are intended to address the above problem;

In order to solve the problems of the technologies described above, the utility model is achieved through the following technical solutions:

The utility model comprises: NMOS pipe, PMOS pipe; Also comprise: the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe; Described the 2nd PMOS pipe and the grid of the 3rd PMOS pipe and the grid of a PMOS pipe join, and described the 2nd PMOS pipe links to each other with substrate with the source electrode of the 3rd PMOS pipe, and joins with the substrate of a PMOS pipe and the drain electrode of the 4th PMOS pipe; The drain electrode of the 2nd PMOS pipe and the 3rd PMOS pipe links to each other with drain electrode with the source electrode of a PMOS pipe respectively; The source electrode and the VDD of the 4th PMOS pipe join.

Compared with prior art, the beneficial effects of the utility model are: the drain circuit that switch is closed have no progeny has eased down to minimum, makes the conducting resistance minimum after the switch opens, and the flatness of resistance is best.

Description of drawings

Fig. 1 is existing a kind of conspectus of analog switch;

Fig. 2 is the another kind of conspectus of existing analog switch;

Fig. 3 is a conspectus of the present utility model;

Embodiment

Below in conjunction with accompanying drawing and embodiment the utility model is described in further detail:

As seen from Figure 3: the utility model comprises: NMOS pipe, PMOS pipe; Also comprise: the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe; Described the 2nd PMOS pipe and the grid of the 3rd PMOS pipe and the grid of a PMOS pipe join, and described the 2nd PMOS pipe links to each other with substrate with the source electrode of the 3rd PMOS pipe, and joins with the substrate of a PMOS pipe and the drain electrode of the 4th PMOS pipe; The drain electrode of the 2nd PMOS pipe and the 3rd PMOS pipe links to each other with drain electrode with the source electrode of a PMOS pipe respectively; The source electrode and the VDD of the 4th PMOS pipe join.

The utility model has increased by two PMOS pipes (P2.P3) between the source of the substrate 6 of PMOS pipe P1 and PMOS, leakage (1.3). connects together by another one PMOS pipe P4 between simultaneously with substrate and VDD.

Operation principle of the present utility model: when grid 5 meets low-voltage GND when PMOS pipe P1 opens. P2 and P3 also open simultaneously. the source of the substrate of P1 and P1 like this, leak (1.3) thus connect together. eliminated body effect. conducting resistance is reduced, and improved the flatness of conducting resistance, when switch turn-offs, be that the grid 5 of PMOS pipe P1 is when meeting high level VDD, P1, P2, P3 turn-offs, P4 opens simultaneously, the N trap substrate of P1 is pulled to VDD by P4 like this, like this when the voltage of 1.3 pin when GND changes between VDD, the substrate of P1 meets high voltage VDD all the time, so just avoided the leakage current of PMOS pipe P1 substrate, made switch close the drain circuit of having no progeny and eased down to minimum.

Claims

1. analog switch control circuit in the chip comprises: NMOS pipe, PMOS pipe; Also comprise: the 2nd PMOS pipe, the 3rd PMOS pipe, the 4th PMOS pipe; It is characterized in that: described the 2nd PMOS pipe and the grid of the 3rd PMOS pipe and the grid of a PMOS pipe join, and described the 2nd PMOS pipe links to each other with substrate with the source electrode of the 3rd PMOS pipe, and joins with the substrate of a PMOS pipe and the drain electrode of the 4th PMOS pipe; The drain electrode of the 2nd PMOS pipe and the 3rd PMOS pipe links to each other with drain electrode with the source electrode of a PMOS pipe respectively; The source electrode and the VDD of the 4th PMOS pipe join.