CN112838855A - Self-switching well switching circuit - Google Patents
Self-switching well switching circuit Download PDFInfo
- Publication number
- CN112838855A CN112838855A CN202110209632.9A CN202110209632A CN112838855A CN 112838855 A CN112838855 A CN 112838855A CN 202110209632 A CN202110209632 A CN 202110209632A CN 112838855 A CN112838855 A CN 112838855A
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- voltage pmos
- pmos tube
- voltage
- switching
- tube
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
Abstract
The invention discloses a self-switching trap switch circuit which comprises a first high-voltage PMOS (P-channel metal oxide semiconductor) tube, wherein the first high-voltage PMOS tube is connected with an ISW (integrated circuit) signal interface in series, the first high-voltage PMOS tube is connected with a second high-voltage PMOS tube and a third high-voltage PMOS tube in parallel, and the second high-voltage PMOS tube is connected with an INP signal interface in series. Compared with a high-side switch which is started by common current, the high-side switch can be started by only one switching tube, the same on-resistance can be achieved by only 1/4 switching tube areas, meanwhile, the switch can automatically complete the switching of the well potential, namely, the well potential can follow the higher voltage in input/output without turn-off leakage current, and the circuit can be started by VGS equal proportion of the current control type switch, so that the channel matching performance and the temperature characteristic of each path of current control type switch are improved, the structure is simple, and the manufacturing cost is reduced.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a self-switching trap switch circuit.
Background
With the rapid development of science and technology, various industries in China have great progress, and the requirements for various industries are more and more strict, wherein for the use of a power management chip, a high-side switch is sometimes needed, the switch can be used for transmitting a high-voltage signal and can also be used as a switch tube to control a circuit, the requirement for the high-side switch needs to have a backflow prevention function, and because the voltage at two ends of the switch is uncertain, the high-side switch is required not to have electric leakage when the voltages at two ends are inconsistent. A typical application is a switching tube in Boost, whose well potential is switchable to prevent the generation of leakage.
Although the existing switch can realize the function of a high-side switch, the existing switch has the defects that if the area of a single tube with the same on-resistance needs to be four times that of the same on-resistance if the same on-resistance is realized, if the common-mode voltage of the high-side switch is very high, the four-time area is very considerable, the area of a chip is greatly increased, and the cost is improved.
Disclosure of Invention
It is an object of the present invention to provide a self-switching well switch circuit to solve the above problems in the prior art.
In order to solve the technical problems, the invention provides the following technical scheme: the utility model provides a from switching over trap switch circuit, includes first high-pressure PMOS pipe, first high-pressure PMOS pipe is established ties with ISW signal interface, first high-pressure PMOS pipe grid is parallelly connected with first resistance, first high-pressure PMOS pipe is parallelly connected with second high-pressure PMOS pipe and third high-pressure PMOS pipe, second high-pressure PMOS pipe with third high-pressure PMOS pipe establishes ties, second high-pressure PMOS pipe is parallelly connected with first diode, second high-pressure PMOS pipe grid is established ties with third resistance, third resistance with third high-pressure PMOS pipe establishes ties, second high-pressure PMOS pipe is established ties with INP signal interface, third high-pressure PMOS pipe is parallelly connected with the second diode, third high-pressure PMOS pipe is established ties with second resistance, the second resistance with second high-pressure PMOS pipe establishes ties, high-pressure PMOS pipe and INN signal interface establish ties.
Further, the first high-voltage PMOS transistor is a high-voltage PMOS transistor with a symmetrical structure, which is an MOS transistor capable of carrying current through the flow of holes.
Further, the second high-voltage PMOS transistor is an asymmetric high-voltage PMOS transistor, which is an MOS transistor capable of carrying current through the flow of holes.
Further, the third high voltage PMOS transistor is an asymmetric high voltage PMOS transistor, which is an MOS transistor capable of carrying current through the flow of holes.
Further, the first diode is a body diode of the second high-voltage PMOS transistor, before the second high-voltage PMOS transistor is damaged by VDD overvoltage, the first diode breaks down in a reverse direction to provide bias voltage for the P1 body, ISW draws a constant current to ground without a large current, and the ISW current biases the gate voltage of P1 to ensure that P1 is turned on.
Further, the second diode is a body diode of the third high-voltage PMOS transistor, before the VDD overvoltage damages the third high-voltage PMOS transistor, the second diode breaks down in a reverse direction to provide a bias voltage for the body of P2, ISW draws a constant current to ground without a large current, and the gate voltage of P2 is biased by the ISW current to ensure that P2 is turned on.
Further, the first high-voltage PMOS transistor is P1, the second high-voltage PMOS transistor is P2, the third high-voltage PMOS transistor is P3, the first resistor is R1, the second resistor is R2, the first diode is DP2, and the second diode is DP 3.
Compared with the prior art, the invention has the following beneficial effects:
1. compared with a high-side switch which is started by common current, the high-side switch can be started by only one switching tube, the same on-resistance can be achieved by only 1/4 switching tube areas, meanwhile, the switch can automatically complete the switching of the well potential, namely, the well potential can follow the higher voltage in input/output without turn-off leakage current, and the circuit can be started by VGS equal proportion of the current control type switch, so that the channel matching performance and the temperature characteristic of each path of current control type switch are improved, the structure is simple, and the manufacturing cost is reduced.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a block diagram of the circuit array of the present invention as a whole;
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, the present invention provides a technical solution: the utility model provides a from switching over trap switch circuit, includes first high-pressure PMOS pipe, first high-pressure PMOS pipe is established ties with ISW signal interface, first high-pressure PMOS pipe grid is parallelly connected with first resistance, first high-pressure PMOS pipe is parallelly connected with second high-pressure PMOS pipe and third high-pressure PMOS pipe, second high-pressure PMOS pipe with third high-pressure PMOS pipe establishes ties, second high-pressure PMOS pipe is parallelly connected with first diode, second high-pressure PMOS pipe grid is established ties with third resistance, third resistance with third high-pressure PMOS pipe establishes ties, second high-pressure PMOS pipe is established ties with INP signal interface, third high-pressure PMOS pipe is parallelly connected with the second diode, third high-pressure PMOS pipe is established ties with second resistance, the second resistance with second high-pressure PMOS pipe establishes ties, high-pressure PMOS pipe and INN signal interface establish ties.
The first high-voltage PMOS tube is a high-voltage PMOS tube with a symmetrical structure, and is an MOS tube capable of conveying current through the flow of holes.
The second high-voltage PMOS tube is an asymmetric high-voltage PMOS tube and is an MOS tube capable of conveying current through the flow of holes.
The third high-voltage PMOS tube is an asymmetric high-voltage PMOS tube and is an MOS tube capable of carrying current through the flow of holes.
The first diode is a body diode of the second high-voltage PMOS tube, before the second high-voltage PMOS tube is damaged by VDD overvoltage, the first diode is in reverse breakdown firstly to provide bias voltage for a P1 body, ISW pumps a constant current to the ground without large current, and the gate voltage of P1 is biased by the ISW current to ensure that P1 is started.
The second diode is a body diode of the third high-voltage PMOS tube, before the third high-voltage PMOS tube is damaged by VDD overvoltage, the second diode breaks down in the reverse direction to provide bias voltage for a P2 body, ISW draws constant current to the ground without large current, and the gate voltage of P2 is biased by the ISW current to ensure that P2 is started.
The first high-voltage PMOS tube is P1, the second high-voltage PMOS tube is P2, the third high-voltage PMOS tube is P3, the first resistor is R1, the second resistor is R2, the first diode is DP2, the second diode is DP 3.
The specific implementation mode is as follows: when the switch is used, because P1, P2 and P3 are all thin gate oxide tubes and the voltages of INP and INN are uncertain, the switch is opened by adopting a current starting mode, the current ISW flows through R1 to form voltage drop, P1 is opened, and then the switch is switched on, firstly, the voltage of INP is supposed to be higher than that of INN, at the moment, because a P2 body diode exists, the voltage of a node N1 is close to that of INP, at the moment, if ISW does not have current, the body voltage of a P1 tube is INP, at the moment, because ISW current does not exist, the source end voltage and the gate end voltage of P1 are equal to the body voltage, and P1 is switched off, and no leakage current is generated; when the switching tube needs to be opened, the ISW draws a current ISW, the ISW flows through R1 to form a voltage drop, the voltage of an N1 node is INP, the grid voltage of a P2 tube is INN voltage, when the voltage difference between the INP and the INN is large, the P2 is in a linear opening state, the ISW current flows through a channel of the P2 from the INP and then flows through R1 to form a voltage drop VON, the resistance value of R1 and the value of the ISW current are adjusted, and when the VON is larger than the opening voltage of P1, the P1 is conducted; on the contrary, when INN is higher than INP, at this time, because a P3 body diode exists, the voltage of the node N1 is close to the voltage of INN, at this time, if ISW has no current, the bulk voltage of the P1 tube is INN, at this time, because there is no ISW current, the source end voltage and the gate end voltage of P1 are equal to the bulk voltage, P1 is turned off, and no leakage current is generated; when the switching tube needs to be opened, the ISW draws a current ISW, the ISW flows through R1 to form a voltage drop, the voltage of an N1 node is INN, the grid voltage of a P3 tube is INP voltage, when the voltage difference between the INN and the INP is large, the P3 is in a linear opening state, the ISW current flows through a channel of the P3 from the INN and then flows through R1 to form a voltage drop VON, the resistance value of R1 and the value of the ISW current are adjusted, and when the VON is larger than the opening voltage of P1, the P1 is conducted; when the switching is carried out, stable switching-off can be ensured without electric leakage, and the change process is described by taking the example that INP is higher than INN first and then INN is higher than INP; when INP is higher than INN, the voltage of a node N1 is INP voltage, one end of INP is a source of P1, the anode of a parasitic diode is INN, the cathode of the parasitic diode is connected with INP, P1 is turned off, the diode is in a reverse bias state because INP is higher than INN, no electric leakage is generated, then INP and INN are exchanged, INN is higher than INP, a little electric leakage is generated because the parasitic diode cannot be in reverse direction immediately, but the voltage of N1 is still the voltage INP 'before INP because INP is still the voltage of P3, the voltage of INP on the grid voltage of P3 is already lower than INP', so that P3 tube is turned on, the voltage of N1 node is rapidly changed into the voltage of INN, P1 tube also completes automatic switching of well potential, the anode of the parasitic diode is connected with INP, the cathode of the parasitic diode is connected with INN, the cathode of the parasitic diode is higher than INP to form a reverse bias diode, the switching state is stable, no electric leakage is generated, and the circuit can be turned on by using only one switch at, compared with a high-side switch started by common current, the switching tube area of which the same on-resistance is only required to be 1/4 is achieved, meanwhile, the switch can automatically complete the switching of the trap potential, namely the trap potential can follow the higher voltage in input/output without turning off leakage current, the circuit can be started in proportion of VGS (voltage gradient switching) of the current control type switch, the channel matching performance and the temperature characteristic of each current control type switch are improved, the structure is simple, and the manufacturing cost is reduced.
The working principle of the invention is as follows:
referring to the attached figure 1 of the specification, the high-side switch can be turned on only by using one switching tube, compared with a high-side switch turned on by common current, the high-side switch achieves the same on-resistance by only 1/4 areas of the switching tube, meanwhile, the switch can automatically complete the switching of the well potential, namely the well potential can follow the higher voltage in input/output without turn-off leakage current, and the circuit can be turned on in a VGS equal proportion by realizing the current control type switch, so that the channel matching performance and the temperature characteristic of each current control type switch are improved, the structure is simple, and the manufacturing cost is reduced.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described above, or some features may be substituted for the embodiments described above. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. The utility model provides a from switching trap switch circuit, includes first high pressure PMOS pipe, its characterized in that: the first high-voltage PMOS tube is connected in series with an ISW signal interface, a grid electrode of the first high-voltage PMOS tube is connected in parallel with a first resistor, the first high-voltage PMOS tube is connected in parallel with a second high-voltage PMOS tube and a third high-voltage PMOS tube, the second high-voltage PMOS tube is connected in series with a third high-voltage PMOS tube, the second high-voltage PMOS tube is connected in parallel with a first diode, a grid electrode of the second high-voltage PMOS tube is connected in series with a third resistor, the third resistor is connected in series with the third high-voltage PMOS tube, the second high-voltage PMOS tube is connected in series with an INP signal interface, the third high-voltage PMOS tube is connected in parallel with a second diode, the third high-voltage PMOS tube is connected in series with a second resistor, the second resistor is connected in series with the second high-voltage PMOS tube, and the high-voltage PMOS tube is connected in series with.
2. The self-switching well switch circuit of claim 1, wherein: the first high-voltage PMOS tube is a high-voltage PMOS tube with a symmetrical structure.
3. The self-switching well switch circuit of claim 1, wherein: the second high-voltage PMOS tube is a high-voltage PMOS tube with an asymmetric structure.
4. The self-switching well switch circuit of claim 1, wherein: the third high-voltage PMOS tube is a high-voltage PMOS tube with an asymmetric structure.
5. The self-switching well switch circuit of claim 1, wherein: the first diode is a body diode of the second high-voltage PMOS tube.
6. The self-switching well switch circuit of claim 1, wherein: the second diode is a body diode of the third high-voltage PMOS tube.
7. The self-switching well switch circuit of claim 1, wherein: the first high-voltage PMOS tube is P1, the second high-voltage PMOS tube is P2, the third high-voltage PMOS tube is P3, the first resistor is R1, the second resistor is R2, the first diode is DP2, the second diode is DP 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110209632.9A CN112838855A (en) | 2021-02-24 | 2021-02-24 | Self-switching well switching circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110209632.9A CN112838855A (en) | 2021-02-24 | 2021-02-24 | Self-switching well switching circuit |
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| CN112838855A true CN112838855A (en) | 2021-05-25 |
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| CN202110209632.9A Pending CN112838855A (en) | 2021-02-24 | 2021-02-24 | Self-switching well switching circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115001463A (en) * | 2022-05-27 | 2022-09-02 | 南京金阵微电子技术有限公司 | PMOS (P-channel metal oxide semiconductor) switching circuit, chip and electronic equipment |
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2021
- 2021-02-24 CN CN202110209632.9A patent/CN112838855A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115001463A (en) * | 2022-05-27 | 2022-09-02 | 南京金阵微电子技术有限公司 | PMOS (P-channel metal oxide semiconductor) switching circuit, chip and electronic equipment |
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Effective date of registration: 20230512 Address after: Unit 604, 6th Floor, Building 7, Zone A, Hantian Science and Technology City, No. 17 Shenhai Road, Guicheng Street, Nanhai District, Foshan City, Guangdong Province, 528253 Applicant after: FOSHAN SIFIRST TECHNOLOGIES Ltd. Address before: 200120 building C, No.888, Huanhu West 2nd Road, Nanhui new town, Pudong New Area, Shanghai Applicant before: Shanghai kunzhen integrated circuit Co.,Ltd. |