CN103165584B

CN103165584B - Reverse current of interconnection line produces circuit

Info

Publication number: CN103165584B
Application number: CN201110427581.3A
Authority: CN
Inventors: 冯军宏; 甘正浩
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2011-12-19
Filing date: 2011-12-19
Publication date: 2015-09-16
Anticipated expiration: 2031-12-19
Also published as: CN103165584A

Abstract

The invention discloses the circuit that a kind of integrated circuit metal interconnection line can produce reverse current automatically, comprise first to fourth switching circuit; Two control ends of the first switching circuit connect the control pole of higher level's circuit output mos FET and subordinate circuit input MOSFET respectively, and input connects Vss, output connected node A; Two control ends of second switch circuit connect the control pole of output mos FET and input MOSFET respectively, and input connects Vdd, output connected node A; The input of the 3rd switching circuit connects interconnection line near one end of the output stage of output mos FET, and output connects Vss, control end connected node A; The input of the 4th switching circuit connects Vdd, and output connects interconnection line one end near the input pole of input MOSFET, control end connected node A.When the closedown of upper and lower level circuit and vacant time this circuit can produce the electric current contrary with running current in interconnection line, inhibit the electromigration effect that in metal interconnecting wires, single direction electric current causes, improve the reliability of interconnection line, extend the useful life of integrated circuit.

Description

Reverse current of interconnection line produces circuit

Technical field

The present invention relates to semiconductor fabrication, particularly a kind of reverse current of interconnection line produces circuit.

Background technology

Electromigration (EM, ElectroMigration) phenomenon is the diffusion phenomena produced because of electric field influence.In integrated circuit (IC), metal interconnecting wires (interconnect) is connected to each logical circuit, voltage difference is produced because voltage is different between each logical circuit, thus in metal interconnecting wires generation current, there is electromigration, and then generation operating current, integrated circuit is normally worked.

In actual applications, under integrated circuit normally works shape body, the sense of current in most of interconnection line is all single.Such as, as shown in Figure 1, in integrated circuits, higher level's circuit is connected by interconnection line with subordinate circuit, as output mos FET (the Metallic Oxide SemiconductorField EffectTransistor in higher level's circuit, mos field effect transistor), as exported PMOS (P-Metal-Oxide-Semiconductor, P-type mos) or export NMOS (N-Metal-Oxide-Semiconductor, N-type metal-oxide semiconductor (MOS)), output stage (as source electrode) be connected with the first end of metal interconnecting wires, input MOSFET in subordinate's circuit, as inputted PMOS or input NMOS, input pole (as drain electrode) be connected with the second end of metal interconnecting wires.Under integrated circuit normal operating conditions, the sense of current in interconnection line between higher level's circuit and subordinate's circuit is all from higher level's circuit to subordinate's circuit all the time, namely the sense of current from the output stage (as source electrode) of the output mos FET higher level's circuit through as described in metal interconnecting wires flow to the input pole (as drain electrode) of the input MOSFET in subordinate's circuit.

The unidirectional current that metal interconnecting wires is medium-term and long-term, can make interconnect resistance increase along with the increase of service time, and then cause aging of integrated circuit to lose efficacy.Particularly after integrated circuit semiconductor apparatus size develops to sub-micron, deep sub-micron level, the width of metal interconnecting wires is also constantly reducing, and current density constantly increases, and this accelerates the aging speed of integrated circuit more.

Therefore, need a kind of means to reduce between higher level's circuit and subordinate's circuit in metal interconnecting wires single direction electric current to the impact of aging of integrated circuit.

Summary of the invention

In view of this, the invention provides a kind of circuit of automatic generation reverse current of interconnection line, to prevent the electric current of single direction in metal interconnecting wires between higher level's circuit and subordinate's circuit from causing the aging of integrated circuit, extend the useful life of integrated circuit.

Technical scheme of the present invention is achieved in that

A kind of reverse current of interconnection line produces circuit:

Comprise the first switching circuit, second switch circuit, the 3rd switching circuit and the 4th switching circuit;

Contact in first control end of described first switching circuit and the control pole of higher level's circuit output mos FET, the control pole that second control end and subordinate circuit input MOSFET is electrically connected, input is electrically connected with the first supply voltage, and output is electrically connected with the output of second switch circuit;

First control end of described second switch circuit is electrically connected with the control pole of higher level's circuit output mos FET, the control pole that second control end and subordinate circuit input MOSFET is electrically connected, input is electrically connected with second source voltage, and output is electrically connected with the output of the first switching circuit;

Unique control end of described 3rd switching circuit is electrically connected with the output of first, second switching circuit, and input is electrically connected with the first supply voltage, and output is electrically connected with described interconnection line one end near the output stage of higher level's circuit output mos FET;

Unique control end of described 4th switching circuit is electrically connected with the output of first, second switching circuit, and input is electrically connected with second source voltage; Output and described interconnection line input the input pole of MOSFET one end near subordinate's circuit is electrically connected;

The control end of the output of described first switching circuit, the output of second switch circuit, the 3rd switching circuit and the control end of the 4th switching circuit are electrically connected on node A;

Described second source voltage is higher than the first supply voltage;

When described higher level's circuit and subordinate's circuit working, the first switching circuit is opened, second switch circuit is closed, the 3rd switching circuit cuts out, the 4th switching circuit cuts out;

When described higher level's circuit and subordinate's circuit are closed, the first switching circuit cuts out, second switch circuit is opened, the 3rd switching circuit is opened, the 4th switching circuit is opened.

Further:

Described higher level's circuit output mos FET is the control very grid of PMOS, this PMOS, exports very source electrode;

Described subordinate circuit input MOSFET is the control very grid of PMOS, this PMOS, and input very drains;

Described first switching circuit comprises PMOS A and PMOS B, the source electrode of this PMOS A and the drain electrode electrical connection of PMOSB, first control end of the first switching circuit is the grid of this PMOS A, second control end is the grid of this PMOS B, input is the drain electrode of this PMOS A, and output is the source electrode of this PMOS B; The grid of described PMOS A is electrically connected with the grid of higher level's circuit output mos FET, and the grid that the grid of described PMOS B and subordinate circuit input MOSFET is electrically connected, and the drain electrode of described PMOS A is electrically connected with described first supply voltage;

Described second switch circuit comprises NMOS A ' and NMOS B ', the drain electrode of this NMOS A ' and the source electrode electrical connection of NMOS B ', first control end of second switch circuit is the grid of this NMOS A ', second control end is the grid of this NMOS B ', output is the source electrode of this NMOS A ', and input is the drain electrode of this NMOS B '; The grid of described NMOS A ' is electrically connected with the grid of higher level's circuit output mos FET, and the grid that the grid of described NMOS B ' and subordinate circuit input MOSFET is electrically connected, and the drain electrode of described NMOS B ' is electrically connected with described second source voltage;

Described 3rd switching circuit comprises driving N MOS A, and the input of described 3rd switching circuit is the drain electrode of this driving N MOS A, and output is the source electrode of this driving N MOS A, and unique control end is the grid of this driving N MOS A; The drain electrode of described driving N MOS A is electrically connected with described interconnection line one end near the source electrode of higher level's circuit output mos FET, and the source electrode of described driving N MOS A is electrically connected with the first supply voltage;

Described 4th switching circuit comprises driving N MOS B, the input of described 4th switching circuit is the drain electrode of this driving N MOS B, output is the source electrode of this driving N MOS B, unique control end is the grid of this driving N MOS B, the drain electrode of described driving N MOS B is electrically connected with second source voltage, and the source electrode of described driving N MOS B and described interconnection line input the drain electrode of MOSFET one end near subordinate's circuit is electrically connected;

The source electrode of described PMOS B, the source electrode of NMOS A ', the grid of driving N MOS A and the grid of driving N MOS B are electrically connected on node A.

Further:

Described first switching circuit comprises NMOS A and NMOS B, the source electrode of this NMOS A and the drain electrode electrical connection of NMOS B, first control end of the first switching circuit is the grid of this NMOS A, second control end is the grid of this NMOS B, input is the drain electrode of this NMOS A, and output is the source electrode of this NMOS B; The grid of described NMOS A is electrically connected with the grid of higher level's circuit output mos FET, and the grid that the grid of described NMOS B and subordinate circuit input MOSFET is electrically connected, and the drain electrode of described NMOS A is electrically connected with described first supply voltage;

Described second switch circuit comprises PMOS A ' and PMOS B ', the drain electrode of this PMOS A ' and the source electrode electrical connection of PMOS B ', first control end of second switch circuit is the grid of this PMOS A ', second control end is the grid of this PMOS B ', output is the source electrode of this PMOS A ', and input is the drain electrode of this PMOS B '; The grid of described PMOS A ' is electrically connected with the grid of higher level's circuit output mos FET, and the grid that the grid of described PMOS B ' and subordinate circuit input MOSFET is electrically connected, and the drain electrode of described PMOS B ' is electrically connected with described second source voltage;

Described 3rd switching circuit comprises driving PMOS A, and the input of described 3rd switching circuit is the drain electrode of this driving PMOS A, and output is the source electrode of this driving PMOS A, and unique control end is the grid of this driving PMOS A; The drain electrode of described driving PMOS A is electrically connected with described interconnection line one end near the source electrode of higher level's circuit output mos FET, and the source electrode of described driving PMOS A is electrically connected with the first supply voltage;

Described 4th switching circuit comprises driving PMOS B, the input of described 4th switching circuit is the drain electrode of this driving PMOS B, output is the source electrode of this driving PMOS B, unique control end is the grid of this driving PMOS B, the drain electrode of described driving PMOS B is electrically connected with second source voltage, and described one end driving the source electrode of PMOS B and described interconnection line to input the drain electrode of MOSFET near subordinate's circuit is electrically connected;

The grid of the source electrode of described NMOS B, the source electrode of PMOS A ', driving PMOS A and the grid of driving PMOS B are electrically connected on node A.

Further:

Described subordinate circuit input MOSFET is the control very grid of NMOS, this NMOS, and input very drains;

Described first switching circuit comprises PMOS A and NMOS B, the source electrode of this PMOS A and the drain electrode electrical connection of NMOS B, first control end of the first switching circuit is the grid of this PMOS A, second control end is the grid of this NMOS B, input is the drain electrode of this PMOS A, and output is the source electrode of this NMOS B; The grid of described PMOS A is electrically connected with the grid of higher level's circuit output mos FET, and the grid that the grid of described NMOS B and subordinate circuit input MOSFET is electrically connected, and the drain electrode of described PMOS A is electrically connected with described first supply voltage;

Described second switch circuit comprises NMOS A ' and PMOS B ', the drain electrode of this NMOS A ' and the source electrode electrical connection of PMOS B ', first control end of second switch circuit is the grid of this NMOS A ', second control end is the grid of this PMOS B ', output is the source electrode of this NMOS A ', and input is the drain electrode of this PMOS B '; The grid of described NMOS A ' is electrically connected with the grid of higher level's circuit output mos FET, and the grid that the grid of described PMOS B ' and subordinate circuit input MOSFET is electrically connected, and the drain electrode of described PMOS B ' is electrically connected with described second source voltage;

The source electrode of described NMOS B, the source electrode of NMOS A ', the grid of driving N MOS A and the grid of driving N MOS B are electrically connected on node A.

Further:

Described first switching circuit comprises NMOS A and PMOS B, the source electrode of this NMOS A and the drain electrode electrical connection of PMOS B, first control end of the first switching circuit is the grid of this NMOS A, second control end is the grid of this PMOS B, input is the drain electrode of this NMOS A, and output is the source electrode of this PMOS B; The grid of described NMOS A is electrically connected with the grid of higher level's circuit output mos FET, and the grid that the grid of described PMOS B and subordinate circuit input MOSFET is electrically connected, and the drain electrode of described NMOS A is electrically connected with described first supply voltage;

Described second switch circuit comprises PMOS A ' and NMOS B ', the drain electrode of this PMOS A ' and the source electrode electrical connection of NMOS B ', first control end of second switch circuit is the grid of this PMOS A ', second control end is the grid of this NMOS B ', output is the source electrode of this PMOS A ', and input is the drain electrode of this NMOS B '; The grid of described PMOS A ' is electrically connected with the grid of higher level's circuit output mos FET, and the grid that the grid of described NMOS B ' and subordinate circuit input MOSFET is electrically connected, and the drain electrode of described NMOS B ' is electrically connected with described second source voltage;

The grid of the source electrode of described PMOS B, the source electrode of PMOS A ', driving PMOS A and the grid of driving PMOS B are electrically connected on node A.

Further:

Described higher level's circuit output mos FET is the control very grid of NMOS, this NMOS, exports very source electrode;

The source electrode of described PMOS B, the source electrode of PMOS A ', the grid of driving N MOS A and the grid of driving N MOS B are electrically connected on node A.

Further:

The grid of the source electrode of described NMOS B, the source electrode of NMOS A ', driving PMOS A and the grid of driving PMOS B are electrically connected on node A.

Further:

The source electrode of described NMOS B, the source electrode of PMOS A ', the grid of driving N MOS A and the grid of driving N MOS B are electrically connected on node A.

Further:

The grid of the source electrode of described PMOS B, the source electrode of NMOS A ', driving PMOS A and the grid of driving PMOS B are electrically connected on node A.

Further, described first supply voltage is Vss voltage, and described second source voltage is Vdd voltage.

As can be seen from such scheme: reverse current of interconnection line of the present invention produces circuit, when higher level's circuit and subordinate's circuit normally work, first switching circuit is opened, second switch circuit is closed, the 3rd switching circuit cuts out, the 4th switching circuit cuts out, therefore be closed condition through the 4th switching circuit, interconnection line, the 3rd switching circuit to the circuit of the first supply voltage from second source voltage, from higher level's circuit to the forward operating current of subordinate's circuit when only having higher level's circuit and subordinate's circuit normally to work in interconnection line, when higher level's circuit and subordinate's circuit closedown and vacant time, first switching circuit cuts out, second switch circuit is opened, 3rd switching circuit is opened, 4th switching circuit is opened, therefore from second source voltage through the 4th switching circuit, interconnection line, 3rd switching circuit is opening to the circuit of the first supply voltage, the reverse-biased electric field from subordinate's circuit to higher level's circuit direction is created in interconnection line, and then produce the reverse current contrary with running current, this reverse current is mutually complementary with the forward operating current in higher level's circuit and subordinate's circuit normal mutual when working line, inhibit the electromigration effect that in metal interconnecting wires, single direction electric current causes, improve the reliability of interconnection line, extend the useful life of integrated circuit.

Accompanying drawing explanation

Fig. 1 is the schematic diagram that in integrated circuit, interconnection line connects higher level's circuit and subordinate's circuit;

Fig. 2 is the structure chart that reverse current of interconnection line of the present invention produces circuit;

Fig. 3 a and Fig. 3 b is the circuit diagram that reverse current of interconnection line of the present invention produces circuit embodiments 1;

Fig. 4 a and Fig. 4 b is the circuit diagram that reverse current of interconnection line of the present invention produces circuit embodiments 2;

Fig. 5 a and Fig. 5 b is the circuit diagram that reverse current of interconnection line of the present invention produces circuit embodiments 3;

Fig. 6 a and Fig. 6 b is the circuit diagram that reverse current of interconnection line of the present invention produces circuit embodiments 4;

Fig. 7 a and Fig. 7 b is the circuit diagram that reverse current of interconnection line of the present invention produces circuit embodiments 5;

Fig. 8 a and Fig. 8 b is the circuit diagram that reverse current of interconnection line of the present invention produces circuit embodiments 6;

Fig. 9 a and Fig. 9 b is the circuit diagram that reverse current of interconnection line of the present invention produces circuit embodiments 7;

Figure 10 a and Figure 10 b is the circuit diagram that reverse current of interconnection line of the present invention produces circuit embodiments 8.

In accompanying drawing, the title representated by each label is as follows:

1, the first switching circuit, 2, second switch circuit, the 3, the 3rd switching circuit, the 4, the 4th switching circuit, 5, interconnection line

Embodiment

For making object of the present invention, technical scheme and advantage clearly understand, to develop simultaneously embodiment referring to accompanying drawing, the present invention is described in further detail.

As shown in Figure 2, reverse current of interconnection line generation circuit provided by the invention comprises: the first switching circuit 1, second switch circuit 2, the 3rd switching circuit 3 and the 4th switching circuit 4; First control end of the first switching circuit 1 is electrically connected with the control pole of higher level's circuit output mos FET, and the control pole that the second control end and subordinate circuit input MOSFET is electrically connected, and input is electrically connected with the first supply voltage; Output is electrically connected with the output of second switch circuit.First control end of second switch circuit 2 is electrically connected with the control pole of higher level's circuit output mos FET, the control pole that second control end and subordinate circuit input MOSFET is electrically connected, input is electrically connected with second source voltage, and output is electrically connected with the output of the first switching circuit.Unique control end of the 3rd switching circuit 3 is electrically connected with the output of first, second switching circuit 1,2, and input is electrically connected with the first supply voltage, and output is electrically connected with interconnection line 5 one end near the output stage of higher level's circuit output mos FET.Unique control end of the 4th switching circuit 4 is electrically connected with the output of first, second switching circuit 1,2, and input is electrically connected with second source voltage, and output and interconnection line 5 input the input pole of MOSFET one end near subordinate's circuit is electrically connected.The control end of the output of the first switching circuit 1, the output of second switch circuit 2, the 3rd switching circuit 3 and the control end of the 4th switching circuit 4 are electrically connected on node A.Second source voltage is higher than the first supply voltage.In circuit shown in Fig. 2, when higher level's circuit and subordinate's circuit working, first switching circuit 1 is opened, second switch circuit 2 is closed, the 3rd switching circuit 3 cuts out, the 4th switching circuit cuts out 4, and now in interconnection line 5, the sense of current is from higher level's circuit output mos FET to subordinate's circuit input MOSFET (hereinafter referred to as forward current), when higher level's circuit and subordinate's circuit closedown and vacant time, first switching circuit 1 cuts out, second switch circuit 2 is opened, 3rd switching circuit 3 is opened, 4th switching circuit 4 is opened, now there is one from second source voltage through the 4th switching circuit 4, interconnection line 5, the path of the 3rd switching circuit 3 to the first supply voltage, just the electric current (hereinafter referred to as reverse current) from subordinate's circuit to higher level's circuit direction is created in interconnection line 5, this electric current is contrary with the direction of the forward current of electric current in higher level's circuit and subordinate's circuit normal mutual when working line 5, mutually complementary with forward current for this reverse current of interconnection line 5, thus inhibit the electromigration effect that in metal interconnecting wires 5, single direction electric current causes, improve the reliability of interconnection line 5, extend the useful life of integrated circuit.

Particularly, reverse current of interconnection line of the present invention produces in circuit:

First supply voltage is Vss voltage, and second source voltage is Vdd voltage.First switching circuit 1 is made up of transistor MOS A and MOS B, the source electrode of MOS A and the drain electrode electrical connection of MOS B, the first control end of the first switching circuit 1 is the grid of MOS A, and the second control end is the grid of MOS B, input is the drain electrode of MOS A, and output is the source electrode of MOS B; The grid of MOS A is electrically connected with the grid of higher level's circuit output mos FET, and the grid that the grid of MOS B and subordinate circuit input MOSFET is electrically connected, and the source electrode of MOS A is electrically connected with Vss.Second switch circuit 2 is made up of MOS A ' and NMOS B ', the drain electrode of MOS A ' and the source electrode electrical connection of NMOS B ', first control end of second switch circuit 2 is the grid of MOS A ', second control end is the grid of MOS B ', output is the source electrode of MOS A ', and input is the drain electrode of MOS B '; The grid of MOS A ' is electrically connected with the grid of higher level's circuit output mos FET, and the grid that the grid of MOS B ' and subordinate circuit input MOSFET is electrically connected, and the drain electrode of MOS B ' is electrically connected with Vdd.3rd switching circuit 3 is made up of driving (force) MOS A, and the input of the 3rd switching circuit 3 is the drain electrode of driven MOS A, and output is the source electrode of driven MOS A, and unique control end is the grid of driving N MOS A; The drain electrode of driven MOS A is electrically connected with interconnection line 5 one end near the source electrode of higher level's circuit output mos FET, and source electrode is electrically connected with Vss.4th switching circuit 4 is made up of driven MOS B, the input of the 4th switching circuit 4 is the drain electrode of driven MOS B, output is the source electrode of driven MOS B, unique control end is the grid of driven MOS B, the drain electrode of driven MOS B is electrically connected with Vdd, and source electrode and interconnection line 5 input the drain electrode of MOSFET one end near subordinate's circuit is electrically connected.The grid of the source electrode of MOS B, the source electrode of MOS A ', the grid of driven MOS A and driven MOS B is electrically connected on node A.By the control of MOS A, MOS B, MOS A ' and MOS B ', close or open driven MOS A and driven MOS B; When higher level's circuit and subordinate's circuit normally work, by MOS A, MOS B, MOS A ' and MOS B ', driven MOS A and driven MOS B is closed, in interconnection line, only have the forward current that higher level's circuit and subordinate's circuit normally work; When higher level's circuit and subordinate's circuit are closed, make driven MOS A and driven MOS B conducting (unlatching) by MOS A, MOS B, MOS A ' and MOS B ', in interconnection line, produce reverse current.

According to the difference of the kind of higher level's circuit output mos FET and subordinate circuit input MOSFET, the kind of above-mentioned MOS A, MOS B, MOS A ', MOS B ', driven MOS A and driven MOS B has multiple combination mode, as shown in the table.

The specific embodiment of the circuit of the present invention that each device below just in upper table is formed is further described.

Embodiment 1

As shown in Figure 3 a, 3 b also with reference to figure 2, when the control very grid that higher level's circuit output mos FET is PMOS, this PMOS, export very source electrode, subordinate circuit input MOSFET is the control very grid of PMOS, this PMOS, when input very drains:

First switching circuit 1 comprises PMOS A and PMOS B, the source electrode of this PMOS A and the drain electrode electrical connection of PMOSB, first control end of the first switching circuit 1 is the grid of this PMOS A, second control end is the grid of this PMOS B, input is the drain electrode of this PMOS A, and output is the source electrode of this PMOS B; The grid of PMOS A is electrically connected with the grid of higher level's circuit output mos FET (PMOS), and the grid that the grid of PMOS B and subordinate circuit input MOSFET (PMOS) is electrically connected, and the drain electrode of PMOS A is electrically connected with Vss.Second switch circuit 2 comprises NMOS A ' and NMOSB ', the drain electrode of this NMOS A ' and the source electrode electrical connection of NMOS B ', first control end of second switch circuit 2 is the grid of this NMOS A ', second control end is the grid of this NMOS B ', output is the source electrode of this NMOS A ', and input is the drain electrode of this NMOS B '; The grid of NMOS A ' is electrically connected with the grid of higher level's circuit output mos FET (PMOS), and the grid that the grid of NMOS B ' and subordinate circuit input MOSFET (PMOS) is electrically connected, and the drain electrode of NMOS B ' is electrically connected with Vdd.3rd switching circuit 3 is made up of driving N MOS A, and the input of the 3rd switching circuit 3 is the drain electrode of this driving N MOS A, and output is the source electrode of this driving N MOS A, and unique control end is the grid of this driving N MOS A; The drain electrode of driving N MOS A is electrically connected with interconnection line 5 one end near the source electrode of higher level's circuit output mos FET (PMOS), and the source electrode of driving N MOS A is electrically connected with Vss.4th switching circuit 4 comprises driving N MOS B, the input of the 4th switching circuit 4 is the drain electrode of this driving N MOS B, output is the source electrode of this driving N MOS B, unique control end is the grid of this driving N MOS B, the drain electrode of driving N MOS B is electrically connected with Vdd, and the source electrode of driving N MOS B and interconnection line 5 input the drain electrode of MOSFET (PMOS) one end near subordinate's circuit is electrically connected.The source electrode of PMOS B, the source electrode of NMOS A ', the grid of driving N MOS A and the grid of driving N MOSB are electrically connected on node A.

As shown in Figure 3 a, when higher level's circuit and subordinate's circuit normally work, the grid of higher level's circuit output mos FET (PMOS) and subordinate's circuit input MOSFET (PMOS) all meets negative voltage Vgg1, makes them all be in opening.Now in circuit of the present invention, the grid of PMOS A, PMOS B, NMOS A ' and NMOS B ' equally all meets negative voltage Vgg1.Be timing conducting because NMOS unlocking condition is gate source voltage Vgs, PMOS unlocking condition is gate source voltage Vgs is conducting time negative, so when higher level's circuit voltage Vgg1 is negative, namely when the Vgs of PMOS A, PMOS B, NMOS A ' and NMOSB ' is negative voltage, PMOS A and PMOS B is in conducting state (the first switching circuit 1 is opened), and NMOS A ' and NMOS B ' is in closed condition (second switch circuit 2 is closed).Now, the grid voltage of driving N MOS A and driving N MOS B is the first supply voltage Vss, makes driving N MOS A and driving N MOS B now be in closed condition (namely the 3rd switching circuit 3 and the 4th switching circuit 4 are closed) like this.Now can not produce reverse current in interconnection line 5, higher level's circuit and subordinate's circuit can keep normal operating conditions, and such as the arrow in Fig. 3 a of the electric current in interconnection line 5 is depicted as the forward current from higher level's circuit to subordinate's circuit.

As shown in Figure 3 b, when higher level's circuit and subordinate's circuit are closed, the grid of higher level's circuit output mos FET (PMOS) and subordinate's circuit input MOSFET (PMOS) all meets positive voltage Vgg2, to ensure that they are all in closed condition.Now in circuit of the present invention, the grid of PMOS A, PMOS B, NMOSA ' and NMOS B ' all meets positive voltage Vgg2, in this situation, PMOS A and PMOS B is in closed condition (the first switching circuit 1 cuts out), and NMOS A ' and NMOS B ' is in conducting state (second switch circuit 2 is opened).Now the grid voltage of driving N MOS A and driving N MOS B is second source voltage Vdd, makes driving N MOS A and driving N MOS B be in conducting state (the 3rd switching circuit 3 and the 4th switching circuit 4 are opened) like this.In interconnection line 5, now produce the reverse current as shown in arrow in Fig. 3 b.

Embodiment 2

Also with reference to figure 2 as shown in Fig. 4 a, Fig. 4 b, when the control very grid that higher level's circuit output mos FET is PMOS, this PMOS, export very source electrode, subordinate circuit input MOSFET is the control very grid of PMOS, this PMOS, when input very drains:

First switching circuit 1 comprises NMOS A and NMOS B, the source electrode of this NMOS A and the drain electrode electrical connection of NMOSB, first control end of the first switching circuit 1 is the grid of this NMOS A, second control end is the grid of this NMOS B, input is the drain electrode of this NMOS A, and output is the source electrode of this NMOS B; The grid of NMOS A is electrically connected with the grid of higher level's circuit output mos FET (PMOS), and the grid that the grid of NMOS B and subordinate circuit input MOSFET (PMOS) is electrically connected, and the drain electrode of NMOS A is electrically connected with Vss.Second switch circuit 2 comprises PMOS A ' and PMOSB ', the drain electrode of this PMOS A ' and the source electrode electrical connection of PMOS B ', first control end of second switch circuit 2 is the grid of this PMOS A ', second control end is the grid of this PMOS B ', output is the source electrode of this PMOS A ', and input is the drain electrode of this PMOS B '; The grid of PMOS A ' is electrically connected with the grid of higher level's circuit output mos FET (PMOS), and the grid that the grid of PMOS B ' and subordinate circuit input MOSFET (PMOS) is electrically connected, and the drain electrode of PMOS B ' is electrically connected with Vdd.3rd switching circuit 3 is made up of driving PMOS A, and the input of the 3rd switching circuit 3 is the drain electrode of this driving PMOS A, and output is the source electrode of this driving PMOS A, and unique control end is the grid of this driving PMOS A; Drive the drain electrode of PMOS A to be electrically connected with interconnection line 5 one end near the source electrode of higher level's circuit output mos FET (PMOS), drive the source electrode of PMOS A to be electrically connected with Vss.4th switching circuit 4 comprises driving PMOS B, the input of the 4th switching circuit 4 is the drain electrode of this driving PMOS B, output is the source electrode of this driving PMOS B, unique control end is the grid of this driving PMOS B, drive the drain electrode of PMOS B to be electrically connected with Vdd, the one end driving the source electrode of PMOS B and interconnection line 5 to input the drain electrode of MOSFET (PMOS) near subordinate's circuit is electrically connected.The grid of the source electrode of NMOS B, the source electrode of PMOS A ', driving PMOS A and the grid of driving PMOS B are electrically connected on node A.

As shown in fig. 4 a, when higher level's circuit and subordinate's circuit normally work, the grid of higher level's circuit output mos FET (PMOS) and subordinate's circuit input MOSFET (PMOS) all meets negative voltage Vgg1, makes them all be in opening.Now in circuit of the present invention, the grid of NMOS A, NMOS B, PMOS A ' and PMOS B ' equally all meets negative voltage Vgg1.Be timing conducting because NMOS unlocking condition is gate source voltage Vgs, PMOS unlocking condition is gate source voltage Vgs is conducting time negative, so when higher level's circuit voltage Vgg1 is negative, namely when the Vgs of NMOS A, NMOS B, PMOS A ' and PMOSB ' is negative voltage, NMOS A and NMOS B is in closed condition (the first switching circuit 1 cuts out), and PMOS A ' and PMOS B ' is in conducting state (second switch circuit 2 is opened).The grid voltage now driving PMOS A and driving PMOS B is second source voltage Vdd, makes like this to drive PMOS A and drive PMOS B to be now in closed condition (namely the 3rd switching circuit 3 and the 4th switching circuit 4 are closed).Now can not produce reverse current in interconnection line 5, higher level's circuit and subordinate's circuit can keep normal operating conditions, and the electric current in interconnection line 5 is the forward current from higher level's circuit to subordinate's circuit as illustrated by the arrow shown in fig. 4a.

As shown in Figure 4 b, when higher level's circuit and subordinate's circuit are closed, the grid of higher level's circuit output mos FET (PMOS) and subordinate's circuit input MOSFET (PMOS) all meets positive voltage Vgg2, to ensure that they are all in closed condition.Now in circuit of the present invention, the grid of NMOS A, NMOS B, PMOSA ' and PMOS B ' all meets positive voltage Vgg2, in this situation, NMOS A and NMOS B is in conducting state (the first switching circuit 1 is opened), and PMOS A ' and PMOS B ' is in closed condition (second switch circuit 2 is closed).The grid voltage now driving the grid voltage of PMOS A and driving PMOS B is the first supply voltage Vss, makes like this to drive PMOS A and drive PMOS B to be in conducting state (namely the 3rd switching circuit 3 and the 4th switching circuit 4 are opened).In interconnection line 5, now produce reverse current as shown by the arrow in figure 4b.

Embodiment 3

Also with reference to figure 2 as shown in Fig. 5 a, Fig. 5 b, when the control very grid that higher level's circuit output mos FET is PMOS, this PMOS, export very source electrode, subordinate circuit input MOSFET is the control very grid of NMOS, this NMOS, when input very drains:

First switching circuit 1 comprises PMOS A and NMOS B, the source electrode of this PMOS A and the drain electrode electrical connection of NMOSB, first control end of the first switching circuit 1 is the grid of this PMOS A, second control end is the grid of this NMOS B, input is the drain electrode of this PMOS A, and output is the source electrode of this NMOS B; The grid of PMOS A is electrically connected with the grid of higher level's circuit output mos FET (PMOS), and the grid that the grid of NMOS B and subordinate circuit input MOSFET (NMOS) is electrically connected, and the drain electrode of PMOS A is electrically connected with Vss.Second switch circuit 2 comprises NMOS A ' and PMOSB ', the drain electrode of this NMOS A ' and the source electrode electrical connection of PMOS B ', first control end of second switch circuit 2 is the grid of this NMOS A ', second control end is the grid of this PMOS B ', output is the source electrode of this NMOS A ', and input is the drain electrode of this PMOS B '; The grid of NMOS A ' is electrically connected with the grid of higher level's circuit output mos FET (PMOS), and the grid that the grid of PMOS B ' and subordinate circuit input MOSFET (NMOS) is electrically connected, and the drain electrode of PMOS B ' is electrically connected with Vdd.3rd switching circuit 3 is made up of driving N MOS A, and the input of the 3rd switching circuit 3 is the drain electrode of this driving N MOS A, and output is the source electrode of this driving N MOS A, and unique control end is the grid of this driving N MOS A; The drain electrode of driving N MOS A is electrically connected with interconnection line 5 one end near the source electrode of higher level's circuit output mos FET (PMOS), and the source electrode of driving N MOS A is electrically connected with Vss.4th switching circuit 4 comprises driving N MOS B, the input of the 4th switching circuit 4 is the drain electrode of this driving N MOS B, output is the source electrode of this driving N MOS B, unique control end is the grid of this driving N MOS B, the drain electrode of driving N MOS B is electrically connected with Vdd, and the source electrode of driving N MOS B and interconnection line 5 input the drain electrode of MOSFET (NMOS) one end near subordinate's circuit is electrically connected.The source electrode of NMOS B, the source electrode of NMOS A ', the grid of driving N MOS A and the grid of driving N MOS B are electrically connected on node A.

As shown in Figure 5 a, when higher level's circuit and subordinate's circuit normally work: the grid of higher level's circuit output mos FET (PMOS) meets negative voltage Vgg1, the grid of subordinate's circuit input MOSFET (NMOS) meets positive voltage Vgg2, makes them all be in opening.Now in circuit of the present invention: the grid for the PMOS A in the first switching circuit 1 and NMOS B, PMOS A meets negative voltage Vgg1, and the grid of NMOS B meets positive voltage Vgg2, make PMOS A and the equal conducting of NMOS B, the first switching circuit 1 is opened; Grid for the NMOS A ' in second switch circuit 2 and PMOS B ', NMOS A ' meets negative voltage Vgg1, and the grid of PMOS B ' meets positive voltage Vgg2, and NMOS A ' and PMOS B ' is all closed, and second switch circuit 2 is closed.Now, the grid voltage of driving N MOS A and driving N MOS B is the first supply voltage Vss, makes driving N MOS A and driving N MOS B now be in closed condition (namely the 3rd switching circuit 3 and the 4th switching circuit 4 are closed) like this.Now can not produce reverse current in interconnection line 5, higher level's circuit and subordinate's circuit can keep normal operating conditions, and such as the arrow in Fig. 5 a of the electric current in interconnection line 5 is depicted as the forward current from higher level's circuit to subordinate's circuit.

As shown in Figure 5 b, when higher level's circuit and subordinate's circuit are closed, the grid of higher level's circuit output mos FET (PMOS) meets positive voltage Vgg2, and the grid of subordinate's circuit input MOSFET (NMOS) meets negative voltage Vgg1, makes them all be in closed condition.Now in circuit of the present invention: the grid for the PMOS A in the first switching circuit 1 and NMOS B, PMOS A meets positive voltage Vgg2, and the grid of NMOS B meets negative voltage Vgg1, PMOS A and NMOS B is all closed, and the first switching circuit 1 cuts out; Grid for the NMOS A ' in second switch circuit 2 and PMOS B ', NMOSA ' meets positive voltage Vgg2, and the grid of PMOS B ' meets negative voltage Vgg1, and NMOS A ' and PMOS B ' is all opened, and second switch circuit 2 is opened.Now, the grid voltage of driving N MOS A and driving N MOSB is second source voltage Vdd, makes driving N MOS A and driving N MOS B now be in conducting state (namely the 3rd switching circuit 3 and the 4th switching circuit 4 are opened) like this.In interconnection line 5, now produce the reverse current as shown in arrow in Fig. 5 b.

Embodiment 4

Also with reference to figure 2 as shown in Fig. 6 a, Fig. 6 b, when the control very grid that higher level's circuit output mos FET is PMOS, this PMOS, export very source electrode, subordinate circuit input MOSFET is the control very grid of NMOS, this NMOS, when input very drains:

First switching circuit 1 comprises NMOS A and PMOS B, the source electrode of this NMOS A and the drain electrode electrical connection of PMOSB, first control end of the first switching circuit 1 is the grid of this NMOS A, second control end is the grid of this PMOS B, input is the drain electrode of this NMOS A, and output is the source electrode of this PMOS B; The grid of NMOS A is electrically connected with the grid of higher level's circuit output mos FET (PMOS), and the grid that the grid of PMOS B and subordinate circuit input MOSFET (NMOS) is electrically connected, and the drain electrode of NMOS A is electrically connected with Vss.Second switch circuit 2 comprises PMOS A ' and NMOSB ', the drain electrode of this PMOS A ' and the source electrode electrical connection of NMOS B ', first control end of second switch circuit 2 is the grid of this PMOS A ', second control end is the grid of this NMOS B ', output is the source electrode of this PMOS A ', and input is the drain electrode of this NMOS B '; The grid of PMOS A ' is electrically connected with the grid of higher level's circuit output mos FET (PMOS), and the grid that the grid of NMOS B ' and subordinate circuit input MOSFET (NMOS) is electrically connected, and the drain electrode of NMOS B ' is electrically connected with Vdd.3rd switching circuit 3 is made up of driving PMOS A, and the input of the 3rd switching circuit 3 is the drain electrode of this driving PMOS A, and output is the source electrode of this driving PMOS A, and unique control end is the grid of this driving PMOS A; Drive the drain electrode of PMOS A to be electrically connected with interconnection line 5 one end near the source electrode of higher level's circuit output mos FET (PMOS), drive the source electrode of PMOS A to be electrically connected with Vss.4th switching circuit 4 comprises driving PMOS B, the input of the 4th switching circuit 4 is the drain electrode of this driving PMOS B, output is the source electrode of this driving PMOS B, unique control end is the grid of this driving PMOS B, drive the drain electrode of PMOS B to be electrically connected with Vdd, the one end driving the source electrode of PMOS B and interconnection line 5 to input the drain electrode of MOSFET (NMOS) near subordinate's circuit is electrically connected.The grid of the source electrode of PMOS B, the source electrode of PMOS A ', driving PMOS A and the grid of driving PMOS B are electrically connected on node A.

As shown in Figure 6 a, when higher level's circuit and subordinate's circuit normally work: the grid of higher level's circuit output mos FET (PMOS) meets negative voltage Vgg1, the grid of subordinate's circuit input MOSFET (NMOS) meets positive voltage Vgg2, makes them all be in opening.Now in circuit of the present invention: the grid for the NMOS A in the first switching circuit 1 and PMOS B, NMOS A meets negative voltage Vgg1, and the grid of PMOS B meets positive voltage Vgg2, NMOS A and PMOS B is all closed, and the first switching circuit 1 cuts out; Grid for the PMOS A ' in second switch circuit 2 and NMOS B ', PMOS A ' meets negative voltage Vgg1, and the grid of NMOS B ' meets positive voltage Vgg2, and make PMOS A ' and NMOS B ' all conductings, second switch circuit 2 is opened.Now, the grid voltage driving PMOS A and driving PMOS B is second source voltage Vdd, drives PMOS A and drives PMOS B to be now in closed condition (namely the 3rd switching circuit 3 and the 4th switching circuit 4 are closed).Now can not produce reverse current in interconnection line 5, higher level's circuit and subordinate's circuit can keep normal operating conditions, and such as the arrow in Fig. 6 a of the electric current in interconnection line 5 is depicted as the forward current from higher level's circuit to subordinate's circuit.

As shown in Figure 6 b, when higher level's circuit and subordinate's circuit are closed, the grid of higher level's circuit output mos FET (PMOS) meets positive voltage Vgg2, and the grid of subordinate's circuit input MOSFET (NMOS) meets negative voltage Vgg1, makes them all be in closed condition.Now in circuit of the present invention: the grid for the NMOS A in the first switching circuit 1 and PMOS B, NMOS A meets positive voltage Vgg2, and the grid of PMOS B meets negative voltage Vgg1, make NMOS A and the equal conducting of PMOS B, the first switching circuit 1 is opened; Grid for the PMOS A ' in second switch circuit 2 and NMOS B ', PMOSA ' meets positive voltage Vgg2, and the grid of NMOS B ' meets negative voltage Vgg1, and PMOS A ' and NMOS B ' is all closed, and second switch circuit 2 is closed.Now, the grid voltage driving PMOS A and driving PMOSB is the first supply voltage Vss, makes like this to drive PMOS A and drive PMOS B to be now in conducting state (namely the 3rd switching circuit 3 and the 4th switching circuit 4 are opened).In interconnection line 5, now produce the reverse current as shown in arrow in Fig. 6 b.

Embodiment 5

Also with reference to figure 2 as shown in Fig. 7 a, Fig. 7 b, when the control very grid that higher level's circuit output mos FET is NMOS, this NMOS, export very source electrode, subordinate circuit input MOSFET is the control very grid of PMOS, this PMOS, when input very drains:

First switching circuit 1 comprises NMOS A and PMOS B, the source electrode of this NMOS A and the drain electrode electrical connection of PMOSB, first control end of the first switching circuit 1 is the grid of this NMOS A, second control end is the grid of this PMOS B, input is the drain electrode of this NMOS A, and output is the source electrode of this PMOS B; The grid of NMOS A is electrically connected with the grid of higher level's circuit output mos FET (NMOS), and the grid that the grid of PMOS B and subordinate circuit input MOSFET (PMOS) is electrically connected, and the drain electrode of NMOS A is electrically connected with Vss.Second switch circuit 2 comprises PMOS A ' and NMOSB ', the drain electrode of this PMOS A ' and the source electrode electrical connection of NMOS B ', first control end of second switch circuit 2 is the grid of this PMOS A ', second control end is the grid of this NMOS B ', output is the source electrode of this PMOS A ', and input is the drain electrode of this NMOS B '; The grid of PMOS A ' is electrically connected with the grid of higher level's circuit output mos FET (NMOS), and the grid that the grid of NMOS B ' and subordinate circuit input MOSFET (PMOS) is electrically connected, and the drain electrode of NMOS B ' is electrically connected with Vdd.3rd switching circuit 3 is made up of driving N MOS A, and the input of the 3rd switching circuit 3 is the drain electrode of this driving N MOS A, and output is the source electrode of this driving N MOS A, and unique control end is the grid of this driving N MOS A; The drain electrode of driving N MOS A is electrically connected with interconnection line 5 one end near the source electrode of higher level's circuit output mos FET (NMOS), and the source electrode of driving N MOS A is electrically connected with Vss.4th switching circuit 4 comprises driving N MOS B, the input of the 4th switching circuit 4 is the drain electrode of this driving N MOS B, output is the source electrode of this driving N MOS B, unique control end is the grid of this driving N MOS B, the drain electrode of driving N MOS B is electrically connected with Vdd, and the source electrode of driving N MOS B and interconnection line 5 input the drain electrode of MOSFET (PMOS) one end near subordinate's circuit is electrically connected.The source electrode of PMOS B, the source electrode of PMOS A ', the grid of driving N MOS A and the grid of driving N MOSB are electrically connected on node A.

As shown in Figure 7a, when higher level's circuit and subordinate's circuit normally work: the grid of higher level's circuit output mos FET (NMOS) meets positive voltage Vgg2, the grid of subordinate's circuit input MOSFET (PMOS) meets negative voltage Vgg1, makes them all be in opening.Now in circuit of the present invention: the grid for the NMOS A in the first switching circuit 1 and PMOS B, NMOS A meets positive voltage Vgg2, and the grid of PMOS B meets negative voltage Vgg1, make NMOS A and the equal conducting of PMOS B, the first switching circuit 1 is opened; Grid for the PMOS A ' in second switch circuit 2 and NMOS B ', PMOS A ' meets positive voltage Vgg2, and the grid of NMOS B ' meets negative voltage Vgg1, and PMOS A ' and NMOS B ' is all closed, and second switch circuit 2 is closed.Now, the grid voltage of driving N MOS A and driving N MOS B is the first supply voltage Vss, makes driving N MOS A and driving N MOS B now be in closed condition (namely the 3rd switching circuit 3 and the 4th switching circuit 4 are closed) like this.Now can not produce reverse current in interconnection line 5, higher level's circuit and subordinate's circuit can keep normal operating conditions, and such as the arrow in Fig. 7 a of the electric current in interconnection line 5 is depicted as the forward current from higher level's circuit to subordinate's circuit.

As shown in Figure 7b, when higher level's circuit and subordinate's circuit are closed, the grid of higher level's circuit output mos FET (NMOS) meets negative voltage Vgg1, and the grid of subordinate's circuit input MOSFET (PMOS) meets positive voltage Vgg2, makes them all be in closed condition.Now in circuit of the present invention: the grid for the NMOS A in the first switching circuit 1 and PMOS B, NMOS A meets negative voltage Vgg1, and the grid of PMOS B meets positive voltage Vgg2, NMOS A and PMOS B is all closed, and the first switching circuit 1 cuts out; Grid for the PMOS A ' in second switch circuit 2 and NMOS B ', PMOSA ' meets negative voltage Vgg1, and the grid of NMOS B ' meets positive voltage Vgg2, and make PMOS A ' and NMOS B ' all conductings, second switch circuit 2 is opened.Now, the grid voltage of driving N MOS A and driving N MOS B is second source voltage Vdd, makes driving N MOS A and driving N MOS B now be in conducting state (the 3rd switching circuit 3 and the 4th switching circuit 4 are opened) like this.In interconnection line 5, now produce the reverse current as shown in arrow in Fig. 7 b.

Embodiment 6

Also with reference to figure 2 as shown in Fig. 8 a, Fig. 8 b, when the control very grid that higher level's circuit output mos FET is NMOS, this NMOS, export very source electrode, subordinate circuit input MOSFET is the control very grid of PMOS, this PMOS, when input very drains:

First switching circuit 1 comprises PMOS A and NMOS B, the source electrode of this PMOS A and the drain electrode electrical connection of NMOSB, first control end of the first switching circuit 1 is the grid of this PMOS A, second control end is the grid of this NMOS B, input is the drain electrode of this PMOS A, and output is the source electrode of this NMOS B; The grid of PMOS A is electrically connected with the grid of higher level's circuit output mos FET (NMOS), and the grid that the grid of NMOS B and subordinate circuit input MOSFET (PMOS) is electrically connected, and the drain electrode of PMOS A is electrically connected with Vss.Second switch circuit 2 comprises NMOS A ' and PMOSB ', the drain electrode of this NMOS A ' and the source electrode electrical connection of PMOS B ', first control end of second switch circuit 2 is the grid of this NMOS A ', second control end is the grid of this PMOS B ', output is the source electrode of this NMOS A ', and input is the drain electrode of this PMOS B '; The grid of NMOS A ' is electrically connected with the grid of higher level's circuit output mos FET (NMOS), and the grid that the grid of PMOS B ' and subordinate circuit input MOSFET (PMOS) is electrically connected, and the drain electrode of PMOS B ' is electrically connected with Vdd.3rd switching circuit 3 is made up of driving PMOS A, and the input of the 3rd switching circuit 3 is the drain electrode of this driving PMOS A, and output is the source electrode of this driving PMOS A, and unique control end is the grid of this driving PMOS A; Drive the drain electrode of PMOS A to be electrically connected with interconnection line 5 one end near the source electrode of higher level's circuit output mos FET (NMOS), the source electrode of driving N MOS A is electrically connected with Vss.4th switching circuit 4 comprises driving PMOS B, the input of the 4th switching circuit 4 is the drain electrode of this driving PMOS B, output is the source electrode of this driving PMOS B, unique control end is the grid of this driving PMOS B, drive the drain electrode of PMOS B to be electrically connected with Vdd, the one end driving the source electrode of PMOS B and interconnection line 5 to input the drain electrode of MOSFET (PMOS) near subordinate's circuit is electrically connected.The grid of the source electrode of NMOS B, the source electrode of NMOS A ', driving PMOS A and the grid of driving PMOS B are electrically connected on node A.

As shown in Figure 8 a, when higher level's circuit and subordinate's circuit normally work: the grid of higher level's circuit output mos FET (NMOS) meets positive voltage Vgg2, the grid of subordinate's circuit input MOSFET (PMOS) meets negative voltage Vgg1, makes them all be in opening.Now in circuit of the present invention: the grid for the PMOS A in the first switching circuit 1 and NMOS B, PMOS A meets positive voltage Vgg2, and the grid of NMOS B meets negative voltage Vgg1, PMOS A and NMOS B is all closed, and the first switching circuit 1 cuts out; Grid for the NMOS A ' in second switch circuit 2 and PMOS B ', NMOS A ' meets positive voltage Vgg2, and the grid of PMOS B ' meets negative voltage Vgg1, makes NMOS A ' and PMOS B ' all conductings, second switch circuit 2 conducting.Now, the grid voltage driving PMOS A and driving PMOS B is second source voltage Vdd, makes like this to drive PMOS A and drive PMOS B to be now in closed condition (namely the 3rd switching circuit 3 and the 4th switching circuit 4 are closed).Now can not produce reverse current in interconnection line 5, higher level's circuit and subordinate's circuit can keep normal operating conditions, and such as the arrow in Fig. 8 a of the electric current in interconnection line 5 is depicted as the forward current from higher level's circuit to subordinate's circuit.

As shown in Figure 8 b, when higher level's circuit and subordinate's circuit are closed, the grid of higher level's circuit output mos FET (NMOS) meets negative voltage Vgg1, and the grid of subordinate's circuit input MOSFET (PMOS) meets positive voltage Vgg2, makes them all be in closed condition.Now in circuit of the present invention: the grid for the PMOS A in the first switching circuit 1 and NMOS B, PMOS A meets negative voltage Vgg1, and the grid of NMOS B meets positive voltage Vgg2, make PMOS A and the equal conducting of NMOS B, the first switching circuit 1 is opened; Grid for the NMOS A ' in second switch circuit 2 and PMOS B ', NMOSA ' meets negative voltage Vgg1, and the grid of PMOS B ' meets positive voltage Vgg2, and NMOS A ' and PMOS B ' is all closed, and second switch circuit 2 is closed.Now, the grid voltage driving PMOS A and driving PMOSB is the first supply voltage Vss, makes like this to drive PMOS A and drive PMOS B to be now in conducting state (the 3rd switching circuit 3 and the 4th switching circuit 4 are opened).In interconnection line 5, now produce the reverse current as shown in arrow in Fig. 8 b.

Embodiment 7

Also with reference to figure 2 as shown in Fig. 9 a, Fig. 9 b, when the control very grid that higher level's circuit output mos FET is NMOS, this NMOS, export very source electrode, subordinate circuit input MOSFET is the control very grid of NMOS, this NMOS, when input very drains:

First switching circuit 1 comprises NMOS A and NMOS B, the source electrode of this NMOS A and the drain electrode electrical connection of NMOSB, first control end of the first switching circuit 1 is the grid of this NMOS A, second control end is the grid of this NMOS B, input is the drain electrode of this NMOS A, and output is the source electrode of this NMOS B; The grid of NMOS A is electrically connected with the grid of higher level's circuit output mos FET (NMOS), and the grid that the grid of NMOS B and subordinate circuit input MOSFET (NMOS) is electrically connected, and the drain electrode of NMOS A is electrically connected with Vss.Second switch circuit 2 comprises PMOS A ' and PMOS B ', the drain electrode of this PMOS A ' and the source electrode electrical connection of PMOS B ', first control end of second switch circuit 2 is the grid of this PMOS A ', second control end is the grid of this PMOS B ', output is the source electrode of this PMOS A ', and input is the drain electrode of this PMOS B '; The grid of PMOS A ' is electrically connected with the grid of higher level's circuit output mos FET (NMOS), and the grid that the grid of PMOS B ' and subordinate circuit input MOSFET (NMOS) is electrically connected, and the drain electrode of PMOS B ' is electrically connected with Vdd.3rd switching circuit 3 is made up of driving N MOS A, and the input of the 3rd switching circuit 3 is the drain electrode of this driving N MOS A, and output is the source electrode of this driving N MOS A, and unique control end is the grid of this driving N MOS A; The drain electrode of driving N MOS A is electrically connected with interconnection line 5 one end near the source electrode of higher level's circuit output mos FET (NMOS), and the source electrode of driving N MOS A is electrically connected with Vss.4th switching circuit 4 comprises driving N MOS B, the input of the 4th switching circuit 4 is the drain electrode of this driving N MOS B, output is the source electrode of this driving N MOS B, unique control end is the grid of this driving N MOS B, the drain electrode of driving N MOS B is electrically connected with Vdd, and the source electrode of driving N MOS B and interconnection line 5 input the drain electrode of MOSFET (NMOS) one end near subordinate's circuit is electrically connected.The source electrode of NMOS B, the source electrode of PMOS A ', the grid of driving N MOS A and the grid of driving N MOSB are electrically connected on node A.

As illustrated in fig. 9, when higher level's circuit and subordinate's circuit normally work, the grid of higher level's circuit output mos FET (NMOS) and subordinate's circuit input MOSFET (NMOS) all meets positive voltage Vgg2 makes them all be in opening.Now in circuit of the present invention, the grid of NMOS A, NMOS B, PMOS A ' and PMOS B ' all meets positive voltage Vgg2.Be timing conducting because NMOS unlocking condition is gate source voltage Vgs, PMOS unlocking condition is gate source voltage Vgs is conducting time negative, so when higher level's circuit voltage Vgg2 is just, namely when the Vgs of NMOS A, NMOS B, PMOS A ' and PMOSB ' is positive voltage, NMOS A and NMOS B is in conducting state (the first switching circuit 1 is opened), and PMOS A ' and PMOS B ' is in closed condition (second switch circuit 2 is closed).Now, the grid voltage of driving N MOS A and driving N MOS B is the first supply voltage Vss, makes driving N MOS A and driving N MOS B now be in closed condition (namely the 3rd switching circuit 3 and the 4th switching circuit 4 are closed) like this.Now can not produce reverse current in interconnection line 5, higher level's circuit and subordinate's circuit can keep normal operating conditions, and such as the arrow in Fig. 9 a of the electric current in interconnection line 5 is depicted as the forward current from higher level's circuit to subordinate's circuit.

As shown in figure 9b, when higher level's circuit and subordinate's circuit are closed, the grid of higher level's circuit output mos FET (NMOS) and subordinate's circuit input MOSFET (NMOS) all meets negative voltage Vgg1, to ensure that they are all in closed condition.Now in circuit of the present invention, the grid of NMOS A, NMOS B, PMOSA ' and PMOS B ' all meets negative voltage Vgg1, in this situation, NMOS A and NMOS B is in closed condition (the first switching circuit 1 cuts out), and PMOS A ' and PMOS B ' is in conducting state (second switch circuit 2 is opened).Now, the grid voltage of driving N MOS A and driving N MOS B is second source voltage Vdd, makes driving N MOS A and driving N MOS B now be in conducting state (the 3rd switching circuit 3 and the 4th switching circuit 4 are opened) like this.In interconnection line 5, now produce the reverse current as shown in arrow in Fig. 9 b.

Embodiment 8

Also with reference to figure 2 as shown in Figure 10 a, Figure 10 b, when the control very grid that higher level's circuit output mos FET is NMOS, this NMOS, export very source electrode, subordinate circuit input MOSFET is the control very grid of NMOS, this NMOS, when input very drains:

First switching circuit 1 comprises PMOS A and PMOS B, the source electrode of this PMOS A and the drain electrode electrical connection of PMOSB, first control end of the first switching circuit 1 is the grid of this PMOS A, second control end is the grid of this PMOS B, input is the drain electrode of this PMOS A, and output is the source electrode of this PMOS B; The grid of PMOS A is electrically connected with the grid of higher level's circuit output mos FET (NMOS), and the grid that the grid of PMOS B and subordinate circuit input MOSFET (NMOS) is electrically connected, and the drain electrode of PMOS A is electrically connected with Vss.Second switch circuit 2 comprises NMOS A ' and NMOSB ', the drain electrode of this NMOS A ' and the source electrode electrical connection of NMOS B ', first control end of second switch circuit 2 is the grid of this NMOS A ', second control end is the grid of this NMOS B ', output is the source electrode of this NMOS A ', and input is the drain electrode of this NMOS B '; The grid of NMOS A ' is electrically connected with the grid of higher level's circuit output mos FET (NMOS), and the grid that the grid of NMOS B ' and subordinate circuit input MOSFET (NMOS) is electrically connected, and the drain electrode of NMOS B ' is electrically connected with Vdd.3rd switching circuit 3 is made up of driving PMOS A, and the input of the 3rd switching circuit 3 is the drain electrode of this driving PMOS A, and output is the source electrode of this driving PMOS A, and unique control end is the grid of this driving PMOS A; Drive the drain electrode of PMOS A to be electrically connected with interconnection line 5 one end near the source electrode of higher level's circuit output mos FET (NMOS), drive the source electrode of PMOS A to be electrically connected with Vss.4th switching circuit 4 comprises driving PMOS B, the input of the 4th switching circuit 4 is the drain electrode of this driving PMOS B, output is the source electrode of this driving PMOS B, unique control end is the grid of this driving PMOS B, drive the drain electrode of PMOS B to be electrically connected with Vdd, the one end driving the source electrode of PMOS B and interconnection line 5 to input the drain electrode of MOSFET (NMOS) near subordinate's circuit is electrically connected.The grid of the source electrode of PMOS B, the source electrode of NMOS A ', driving PMOS A and the grid of driving PMOS B are electrically connected on node A.

As shown in Figure 10 a, when higher level's circuit and subordinate's circuit normally work, the grid of higher level's circuit output mos FET (NMOS) and subordinate's circuit input MOSFET (NMOS) all meets positive voltage Vgg2, makes them all be in opening.Now in circuit of the present invention, the grid of PMOS A, PMOS B, NMOS A ' and NMOS B ' equally all meets positive voltage Vgg2.Be timing conducting because NMOS unlocking condition is gate source voltage Vgs, PMOS unlocking condition is gate source voltage Vgs is conducting time negative, so when higher level's circuit voltage Vgg2 is just, namely when the Vgs of PMOS A, PMOS B, NMOS A ' and NMOSB ' is positive voltage, PMOS A and PMOS B is in closed condition (the first switching circuit 1 cuts out), and NMOS A ' and NMOS B ' is in conducting state (second switch circuit 2 is opened).Now, the grid voltage driving PMOS A and driving PMOS B is second source voltage Vdd, makes like this to drive PMOS A and drive PMOS B to be now in closed condition (namely the 3rd switching circuit 3 and the 4th switching circuit 4 are closed).Now can not produce reverse current in interconnection line 5, higher level's circuit and subordinate's circuit can keep normal operating conditions, and such as the arrow in Figure 10 a of the electric current in interconnection line 5 is depicted as the forward current from higher level's circuit to subordinate's circuit.

As shown in fig. lob, when higher level's circuit and subordinate's circuit are closed, the grid of higher level's circuit output mos FET (NMOS) and subordinate's circuit input MOSFET (NMOS) all meets negative voltage Vgg1, to ensure that they are all in closed condition.Now in circuit of the present invention, the grid of PMOS A, PMOS B, NMOSA ' and NMOS B ' all meets negative voltage Vgg1, in this situation, PMOS A and PMOS B is in conducting state (the first switching circuit 1 is opened), and NMOS A ' and NMOS B ' is in closed condition (second switch circuit 2 is closed).Now, the grid voltage driving PMOS A and driving PMOS B is the first supply voltage Vss, makes like this to drive PMOS A and drive PMOS B to be now in conducting state (namely the 3rd switching circuit 3 and the 4th switching circuit 4 are opened).In interconnection line 5, now produce the reverse current as shown in arrow in Figure 10 b.

The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.

Claims

1. reverse current of interconnection line produces a circuit, it is characterized in that:

Described second source voltage is higher than the first supply voltage;

2. reverse current of interconnection line according to claim 1 produces circuit, it is characterized in that:

Described 3rd switching circuit comprises driving N MOS A, and the input of described 3rd switching circuit is the source electrode of this driving N MOS A, and output is the drain electrode of this driving N MOS A, and unique control end is the grid of this driving N MOS A; The drain electrode of described driving N MOS A is electrically connected with described interconnection line one end near the source electrode of higher level's circuit output mos FET, and the source electrode of described driving N MOS A is electrically connected with the first supply voltage;

3. reverse current of interconnection line according to claim 1 produces circuit, it is characterized in that:

Described 3rd switching circuit comprises driving PMOS A, and the input of described 3rd switching circuit is the source electrode of this driving PMOS A, and output is the drain electrode of this driving PMOS A, and unique control end is the grid of this driving PMOS A; The drain electrode of described driving PMOS A is electrically connected with described interconnection line one end near the source electrode of higher level's circuit output mos FET, and the source electrode of described driving PMOS A is electrically connected with the first supply voltage;

4. reverse current of interconnection line according to claim 1 produces circuit, it is characterized in that:

5. reverse current of interconnection line according to claim 1 produces circuit, it is characterized in that:

6. reverse current of interconnection line according to claim 1 produces circuit, it is characterized in that:

7. reverse current of interconnection line according to claim 1 produces circuit, it is characterized in that:

8. reverse current of interconnection line according to claim 1 produces circuit, it is characterized in that:

9. reverse current of interconnection line according to claim 1 produces circuit, it is characterized in that:

10. the reverse current of interconnection line according to any one of claim 1 to 9 produces circuit, and it is characterized in that: described first supply voltage is Vss voltage, described second source voltage is Vdd voltage.