200929781 九、發明說明： 【發明所屬之技術領域】 本發明係相關於一種靜電放電保護電路’尤指一種用 於之輸出電路中之靜電放電保護電路。 【先前技術】 在一般電路設計中，由於需要避免因為環境或人體靜 電對電路造成的傷害，通常會在電路中設置一個電路組， 以使整個電路避免因為靜電的傷害破壞或是減損電路的壽200929781 IX. Description of the Invention: [Technical Field] The present invention relates to an electrostatic discharge protection circuit, particularly an electrostatic discharge protection circuit used in an output circuit. [Prior Art] In general circuit design, since it is necessary to avoid damage to the circuit caused by the environment or human body static electricity, a circuit group is usually set in the circuit, so that the entire circuit can be prevented from being damaged by static electricity or detracting from the life of the circuit.
這樣的電路通常稱為靜電放電（ESD ; Electrostatic Discharge)防護電路，在習知技術中，考慮ESD電路設計 通常有兩種方法： 1. 在電路中裝設鎮流電阻(Ballast resistor)，可避免因 為電路中的寄生(parasitic)NMOS，因為不正常的打開，因 而降低靜電保護的等級，在電路中裝設鎮流電阻可改善 NM0S不正常打開的問題。 2. 在電源線間加上ESD箝制電路，以引導部份或全部 的電流。請參閱第1圖，其係為傳統具有ESD箝制電路之 輸出電路電路圖’如第1圖所示，輸出電路1中包含ESD 箝制電路11，連接於電壓源VCC以及接地端12之間，輸 出電路1另外包含PM0S13，PM0S13之源極耦接於電壓 源VCC、没極耦接於輸出端16，以及nm〇S14，NMOS14 之源極搞接至接地端12，汲極耦接至輸出單元16，二極體 15耦接於電壓源VCC ’輸出單元16耦接於二極體15。因 5 200929781 為ESD箝制電路可引導靜電電流按照二極體η、電壓源 VCC、ESD箝制電路η到接地端12的路線行走，因此可 以避免靜電對電路造成的破壞。 但是在大尺寸的輸出電路應用上，普遍都有低通導電 阻(RDS ON)的需求，但是鎮流電阻會使通導電阻升高，因 此在考量通導電阻以及電路佈局尺寸所反應出的成本，大 尺寸輸出電路中一般都是不加或只是加極小的鎮流電阻， 因此寄生NPN非常容易有不正常打開的情形發生，而如果 ❹ 發生在大尺寸的〇DNMOS(open drain NMOD)，則ESD的 問題將會更加的嚴重，因為此時缺少順偏二極體使靜電電 流如第1圖所示按照二極體、電壓源、p〇wer clamp ESD電 路到接地端的路線行走’而必須流經NMOS。請參閱第2 圖’其係顯示大尺寸〇DNMOS(open drain NMOS)的輸出電 路圖’如第2圖所示，輸出電路2中，第一及第二電容2卜 22用以提供分壓來使第一 NMOS23正常的打開，但在實際 電路中，當進行靜電放電時，會透過第一電容21與二極體 25使電壓源VCC被充電，如果電壓源與接地端之間的電 容比第一電容21大，則電壓源vcc只會被充電到一個不 高的電位，造成第一 NMOS23的閘極電位不夠高，使第一 NMOS23通道打開的阻抗過高，因而降低了靜電防 現，另外第JMOS24如果處於打開的狀態下，也合更進 一步的將第-丽OS23的_電位拉低至接地端，二 放電防護的表現更差。 【發明内容】 200929781 因此，本發明的目的之一，在於提供一種靜電放電保 護電路，其係用於保護一輸出電路在一靜電電壓產生時免 於受到靜電的影響，該靜電放電保護電路包含：一電壓源； 一阻斷充電單元耦接至該電壓源，提供一逆偏以控制該電 壓源在該靜電電壓產生時維持零電位；一：p型金屬氧化半 導體耦接至該阻斷充電單元；一第一N型金屬氧化半導體 耦接至該P型金屬氧化半導體；一第二N型金屬氧化半導 體耦接至該P型金屬氧化半導體以及該第一 N型金屬氧化 ❹ 半導體；及一輸出單元耦接至該第二N型金屬氧化半導 體；其中該靜電電壓受到該阻斷充電單元的影響，不提高 該第二N型金屬氧化半導體開啟的阻抗。 【實施方式】 請參閱第3圖，第3圖為本發明較佳實施例之靜電放 電保護電路，如第3圖所示，靜電放電保護電路4包含一 輸入電壓源IN、偶數級電路41、升位電路42、與否邏輯 閘43、輸出電路44以及輸出單元45。 ® 其中輸入電壓源IN輸入輸入電壓至耦接於輸入電壓源 IN之偶數級電路41，偶數級電路41包含複數個反向器， 如反向器S1、反向器S2等，其中每一反向器互相串連成 偶數級電路41，偶數級電路並耦接至與否邏輯閘43之第 一輸入端。 與否邏輯閘43之第二輸入端耦接至升位電路42,升位 電路42由電壓源VCC、電阻421、第二P型金屬氧化半導 體(PMOS)422、第一電容423以及接地端46所組成，電阻 7 200929781 421之一端耦接至電壓源VCC，另一端耦接至第二 PMOS422之閘極’第二Pm〇S422之源極耦接至第一電容 423之第一端，汲極耦接至接地端46。其中與否邏輯閘之 第二輸入端耦接至第一電容423之第一端與第二PMOS之 源極之間’因為升位電路42的存在，可以切斷整個靜電放 電防護電路與其他接腳（未圖示）的偶數級電路關係，避免 因為偶數級電路41而使與否邏輯閘43的邏輯輸出為低位 準’升位電路可以將與否邏輯閘43的輸出提升為邏輯高位 © 準的狀態。 輸出電路44耦接至與否邏輯閘43之輸出端，包含第 一 PMOS441、第一 NMOS442、阻斷充電單元443、第二 NMOS444 和電壓源 VCC。第一 PMOS441 與第一 NMOS442 之閘極互相耦接，並且耦接至與否邏輯閘43之輸出端，第 一 PMOS441耦接至阻斷充電單元443以及第一 NMOS442 之源極，第一 NMOS442之汲極耦接至接地端46。阻斷單 元443耦接至電壓源VCC。第二NMOS444之閘極耦接至 ❷ 第一 PMOS441之汲極與第一 NMOS442之源極，源極耦接 至輸出單元45、汲極耦接至接地端46。 當靜電電壓在靜電放電防護電路中產生時，阻斷充電 單元443可以阻斷電壓源VCC因為靜電電壓的產生而充 電，使電壓源VCC維持在零電位，而第二NMOS444也因 為電壓源VCC維持在零電位，故閘極電位不會因為VCC 的充電而不夠高，可以有效解決因為分壓而使第二 NMOS444之閘極電壓下降的問題，使第二NMOS444通道 8 ❹ 參 200929781 打開的阻抗變小；另外笛 XTAmCm , 茭J为外弟—NMOS442也不會打開，因此 不會有第-N腦442的_電位純至接地端的情況發 生，相將靜電放電防護的表現維持在很好的品質。 請再參考第4圖’第4圖⑻〜(f)為本發明第一〜第五 f例之阻斷充電單元電路圖，如第4 _所示，阻斷充電 :凡包含第一二極體5卜第一二極體51之一端耦接至電 尺源vcc ’另一端轉接至第—pM〇s44i之源極，第一 PMOS441之源極_至第—pM〇s44i线極，第一 體Μ用㈣斷f壓源vcc在靜電電壓產 _ 徑’使源VCC維持在零電位。 ㈣的路 第4圖（b)為本發明第二較佳實施例之阻斷充 路圖’如第4圖⑻所示’阻斷充電單元包含第三二極體53 與第-高阻抗電阻54，第一二極體51之 體53 源VCC，另-端耗接至第_ pM〇麗之源極，第一2 抗電阻54 一端耦接至電壓源VCC，另一端耦接至第一 圓洲之沒極，第三二極體53和第—高阻抗電阻54用 以阻斷電壓源vcc在靜電電壓產生時充電的路彳 源VCC維持在零電位。 1之冤壓 第4圖（C)為本發明第三較佳實施例之阻斷充電 路圖’如第4圖⑷所示，阻斷充電單元包含第二高阻抗電 阻55第一鬲阻抗電阻55之一端耦接至電壓源VCc， -端耗接至第-PM〇S441之源極，第二高阻 以阻斷電壓源VCC在料電壓產生時充電㈣彳 源VCC維持在零電位。 1更電屢 9 200929781 第4圖（d)為本發明第四較佳實施例之阻斷充電單元電 路圖’如第4圖（d)所示’阻斷充電單元包含第四二極體56、 第五二極體57與第三高阻抗電阻58，第四二極體56之-端麵接至電壓源vcc，另-端搞接至第五二極體57，第五 二極體57之另—端耦接至第一 PMOS441之源極，第三高 阻抗電阻58 —端耦接至電壓源vCc，另一端耦接至第一 PMOS441之沒極，第四二極體56、第五二極體57與第三 面阻抗電阻58用以阻斷電壓源vcc在靜電電壓產生時充 G 電的路徑，使電壓源VCC維持在零電位。 第4圖（e)為本發明第五較佳實施例之阻斷充電單元電 路圖’如第4圖（e)所示，阻斷充電單元包含第六二極體59 與第三PMOS60’第六二極體59之一端耦接至電壓源 VCC，另一端耦接至第一 pm〇S441之源極，第三PMOS60 為一長通道（long-channel)並且汲極端極小的MOS，其中第 三PMOS60的源極耦接至電壓源VCC，閘極耦接至第一 PMOS441之閘極，汲極耦接至第一 pm〇S441之汲極，第 ❹ 六二極體59與第三PMOS60用以阻斷電壓源VCC在靜電 電壓產生時充電的路徑，使電壓源VCC維持在零電位。 第4圖（f)為本發明第六較佳實施例之阻斷充電單元電 路圖，如第4圖⑴所示，阻斷充電單元包含第七二極體 與第一電晶體62 ’第七二極體61之一端耦接至電壓源 VCC，另一端耦接至第一 PMOS441之源極’第一電晶體 62的射極耦接至電壓源VCC，基極耦接至接地端，集極轉 接至第一 PMOS441之汲極，第七二極體61與第一電晶體 200929781 62用以阻斷電壓源vcc在靜電電壓產生時充電的路徑， 使電壓源VCC維持在零電位。 Ο ❹ 如上所述’第4圖⑷〜(f)所示之阻斷充電單元可以有效 的阻斷電壓源vcc因為靜電電壓的產生而充電，使電壓源 VCC維持在零電位，而第二編⑽44也因為電塵源vcc 持在零電位，故閘極在為不會因為的充電而不夠 同可以有效解決因為分壓而使第二丽〇s444之閘極電 麼下降的問題’使第二NM〇S444通道打開的阻抗變小； 另外第- NMOS442 t不會打開，因此不會有第一 〇S442^閘極電位拉低至接地端的情況發生，可以將靜 、放電防4的表現維持在很好的品質。其中第5圖⑻〜⑺ =不之阻斷充電單元僅是實施例之―，實施上之阻斷充電 =不以使為限’凡足以阻斷電壓源充電以避免靜電放 方^表現下降之電路接為本發明所保護之技術。 向哭2戶I述’本發明可以解決靜電放電防護表現因為反 °輸出為低位準或是NM〇S閘極電壓ϋ低以及不 專:。丁开而降低等問題，極具產業上之價值，援以此提出 專二，僅為本發明之較佳實施例，凡依本發明申請 圍。乾做之均等變化與修飾，皆應屬本發明之涵蓋範 200929781 【圖式簡單說明】 第1圖為傳統具有箝制ESD電路之輸出電路電路圖； 第2圖為顯示大尺寸ODNMOS(open drain NMOS)的輸 出電路圖； 第3圖為本發明較佳實施例之靜電放電保護電路；及 第4圖（a)〜(f)為本發明第一〜第五實施例之阻斷充電單 元電路圖。 【主要元件符號說明】Such a circuit is commonly referred to as an electrostatic discharge (ESD) protection circuit. In the prior art, there are generally two methods for considering an ESD circuit design: 1. Install a ballast resistor in the circuit to avoid Because of the parasitic NMOS in the circuit, because of the abnormal opening, thus reducing the level of electrostatic protection, installing a ballast resistor in the circuit can improve the problem that the NM0S is not normally opened. 2. Add an ESD clamp circuit between the power lines to direct some or all of the current. Please refer to FIG. 1 , which is a circuit diagram of an output circuit with a conventional ESD clamp circuit. As shown in FIG. 1 , the output circuit 1 includes an ESD clamp circuit 11 connected between a voltage source VCC and a ground terminal 12 , and an output circuit. 1 further comprising a PM0S13, a source of the PM0S13 is coupled to the voltage source VCC, a pole is coupled to the output terminal 16, and an anode 14S14, the source of the NMOS 14 is connected to the ground terminal 12, and the drain is coupled to the output unit 16, The diode 15 is coupled to the voltage source VCC 'the output unit 16 is coupled to the diode 15 . Because 2009 2981, the ESD clamp circuit can guide the electrostatic current to follow the route of the diode η, the voltage source VCC, and the ESD clamp circuit η to the ground terminal 12, so that the damage caused by static electricity can be avoided. However, in large-scale output circuit applications, there is generally a need for low on-resistance (RDS ON), but ballast resistance will increase the on-resistance, so it is considered in consideration of the on-resistance and the layout size of the circuit. Cost, large-size output circuits generally do not add or only add very small ballast resistors, so parasitic NPN is very likely to have abnormal opening, and if ❹ occurs in a large-sized 〇DNMOS (open drain NMOD), Then the problem of ESD will be more serious, because the lack of a biased diode at this time causes the electrostatic current to follow the route of the diode, the voltage source, and the p〇wer clamp ESD circuit to the ground as shown in Fig. 1 Flow through the NMOS. Please refer to FIG. 2, which shows an output circuit diagram of a large size openDNMOS (open drain NMOS). As shown in FIG. 2, in the output circuit 2, the first and second capacitors 2 are used to provide a voltage division. The first NMOS 23 is normally turned on, but in the actual circuit, when the electrostatic discharge is performed, the voltage source VCC is charged through the first capacitor 21 and the diode 25, if the capacitance between the voltage source and the ground is first. When the capacitor 21 is large, the voltage source vcc will only be charged to a non-high potential, causing the gate potential of the first NMOS 23 to be not high enough, so that the impedance of the first NMOS 23 channel is too high, thereby reducing the static electricity prevention, and additionally If JMOS24 is in the open state, it will further lower the _ potential of the first-stage OS23 to the ground, and the performance of the two-discharge protection is even worse. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an electrostatic discharge protection circuit for protecting an output circuit from static electricity when an electrostatic voltage is generated. The electrostatic discharge protection circuit includes: a voltage source; a blocking charging unit coupled to the voltage source, providing a reverse bias to control the voltage source to maintain a zero potential when the electrostatic voltage is generated; a p-type metal oxide semiconductor coupled to the blocking charging unit a first N-type metal oxide semiconductor coupled to the P-type metal oxide semiconductor; a second N-type metal oxide semiconductor coupled to the P-type metal oxide semiconductor and the first N-type metal-oxide semiconductor; and an output The unit is coupled to the second N-type metal oxide semiconductor; wherein the electrostatic voltage is affected by the blocking charging unit, and the impedance of the second N-type metal oxide semiconductor is not increased. [Embodiment] Please refer to FIG. 3, which is an electrostatic discharge protection circuit according to a preferred embodiment of the present invention. As shown in FIG. 3, the ESD protection circuit 4 includes an input voltage source IN, an even-numbered circuit 41, The boost circuit 42, the logic gate 43, the output circuit 44, and the output unit 45. ® wherein the input voltage source IN inputs an input voltage to an even-numbered circuit 41 coupled to the input voltage source IN, and the even-numbered circuit 41 includes a plurality of inverters, such as an inverter S1, an inverter S2, etc., each of which is inverted The directors are connected in series to an even-numbered circuit 41, and the even-numbered circuits are coupled to the first input of the logical gate 43. The second input terminal of the logic gate 43 is coupled to the boost circuit 42. The boost circuit 42 is composed of a voltage source VCC, a resistor 421, a second P-type metal oxide semiconductor (PMOS) 422, a first capacitor 423, and a ground terminal 46. The first end of the resistor 7 200929781 421 is coupled to the voltage source VCC, and the other end is coupled to the gate of the second PMOS 422. The source of the second Pm 〇 S422 is coupled to the first end of the first capacitor 423, and the drain It is coupled to the ground terminal 46. The second input end of the logic gate is coupled between the first end of the first capacitor 423 and the source of the second PMOS. The entire electrostatic discharge protection circuit can be disconnected from the other by the presence of the ascending circuit 42. The even-numbered circuit relationship of the pin (not shown) avoids whether the logic output of the logic gate 43 is low due to the even-numbered circuit 41. The rising circuit can raise the output of the logic gate 43 to a logic high level. status. The output circuit 44 is coupled to the output of the logic gate 43 and includes a first PMOS 441, a first NMOS 442, a blocking charging unit 443, a second NMOS 444, and a voltage source VCC. The first PMOS 441 is coupled to the gate of the first NMOS 442 and coupled to the output of the logic gate 43. The first PMOS 441 is coupled to the blocking charging unit 443 and the source of the first NMOS 442. The drain is coupled to ground terminal 46. Blocking unit 443 is coupled to voltage source VCC. The gate of the second NMOS 444 is coupled to the drain of the first PMOS 441 and the source of the first NMOS 442, the source is coupled to the output unit 45, and the drain is coupled to the ground terminal 46. When the electrostatic voltage is generated in the ESD protection circuit, the blocking charging unit 443 can block the voltage source VCC from being charged due to the generation of the electrostatic voltage, so that the voltage source VCC is maintained at the zero potential, and the second NMOS 444 is also maintained by the voltage source VCC. At zero potential, the gate potential is not high enough due to the charging of VCC, which can effectively solve the problem that the gate voltage of the second NMOS 444 is lowered due to the voltage division, so that the impedance of the second NMOS 444 channel 8 2009 2009 200929781 is turned on. Small; in addition, the flute XTAmCm, 茭J is the younger brother - NMOS442 will not open, so there will be no _ potential of the -N brain 442 pure to the ground, the performance of the electrostatic discharge protection is maintained at a good quality . Please refer to FIG. 4 'FIG. 4 (8) to (f) are circuit diagrams of the blocking charging unit of the first to fifth f examples of the present invention, as shown in FIG. 4, blocking charging: where the first diode is included One end of the first diode 51 is coupled to the source of the power source vcc' and the other end is switched to the source of the first -pM〇s44i, the source _ to the -pM〇s44i line of the first PMOS 441, first For body ( (4) break f voltage source vcc in the static voltage production _ diameter 'to maintain the source VCC at zero potential. (4) Road Figure 4 (b) is a block diagram of the second preferred embodiment of the present invention. As shown in Fig. 4 (8), the blocking charging unit includes the third diode 53 and the first high impedance resistor. 54. The body 53 of the first diode 51 is sourced from VCC, and the other end is connected to the source of the first _pM, and the first 2 resistance 54 is coupled to the voltage source VCC and coupled to the first end. The fifth pole 53 and the first high impedance resistor 54 are used to block the voltage source vcc from being maintained at a zero potential when the electrostatic voltage is generated. FIG. 4(C) is a block diagram of a charge charging circuit according to a third preferred embodiment of the present invention. As shown in FIG. 4(4), the blocking charging unit includes a second high-impedance resistor 55. One end of 55 is coupled to voltage source VCc, the - terminal is connected to the source of -PM〇S441, and the second high resistance is used to block voltage source VCC to charge when material voltage is generated. (4) Source VCC is maintained at zero potential. 1 more electric repeatedly 9 200929781 4 (d) is a circuit diagram of the blocking charging unit according to the fourth preferred embodiment of the present invention, as shown in FIG. 4(d), the blocking charging unit includes a fourth diode 56, The fifth diode 57 and the third high-impedance resistor 58, the end face of the fourth diode 56 is connected to the voltage source vcc, and the other end is connected to the fifth diode 57, and the fifth diode 57 is The other end is coupled to the source of the first PMOS 441, the third high-impedance resistor 58 is coupled to the voltage source vCc, and the other end is coupled to the first PMOS 441, the fourth diode 56, the fifth The pole body 57 and the third surface impedance resistor 58 are used to block the path of the voltage source vcc charging G when the electrostatic voltage is generated, so that the voltage source VCC is maintained at zero potential. 4(e) is a circuit diagram of a blocking charging unit according to a fifth preferred embodiment of the present invention. As shown in FIG. 4(e), the blocking charging unit includes a sixth diode 59 and a third PMOS 60'. One end of the diode 59 is coupled to the voltage source VCC, the other end is coupled to the source of the first pm 〇 S441, and the third PMOS 60 is a long-channel and 汲 extremely small MOS, wherein the third PMOS 60 The source is coupled to the voltage source VCC, the gate is coupled to the gate of the first PMOS 441, the drain is coupled to the drain of the first pm 〇 S441, and the second hexapole 59 and the third PMOS 60 are used to block The path of the voltage source VCC that is charged when the electrostatic voltage is generated maintains the voltage source VCC at zero potential. FIG. 4(f) is a circuit diagram of a blocking charging unit according to a sixth preferred embodiment of the present invention. As shown in FIG. 4(1), the blocking charging unit includes a seventh diode and a first transistor 62'. One end of the pole body 61 is coupled to the voltage source VCC, and the other end is coupled to the source of the first PMOS 441. The emitter of the first transistor 62 is coupled to the voltage source VCC, and the base is coupled to the ground terminal. Connected to the drain of the first PMOS 441, the seventh diode 61 and the first transistor 200929781 62 are used to block the path of the voltage source vcc charging when the electrostatic voltage is generated, so that the voltage source VCC is maintained at zero potential. Ο ❹ As described above, the blocking charging unit shown in Fig. 4 (4) to (f) can effectively block the voltage source vcc from being charged due to the generation of electrostatic voltage, so that the voltage source VCC is maintained at zero potential, and the second series (10)44 also because the electric dust source vcc is held at zero potential, so the gate is not enough because of the charging, it can effectively solve the problem that the second 〇 s444 gate is reduced due to the partial pressure. The impedance of the NM〇S444 channel is reduced. In addition, the first-NMOS 442t does not turn on, so there is no case where the first 〇S442^ gate potential is pulled down to the ground, and the performance of the static and discharge protection 4 can be maintained. Very good quality. Figure 5 (8) ~ (7) = not blocking the charging unit is only the embodiment - the implementation of blocking charging = not limited to 'anything is enough to block the voltage source to avoid the static discharge The circuit is connected to the technology protected by the present invention. To cry 2 households I said that the invention can solve the electrostatic discharge protection performance because the reverse output is low or the NM 〇S gate voltage is low and not special:. Ding Kai and other problems, which are of great industrial value, are proposed to be specific, and are only preferred embodiments of the present invention, and are applied in accordance with the present invention. Equivalent changes and modifications of dryness should belong to the scope of the present invention 200929781 [Simple description of the diagram] Figure 1 is a circuit diagram of an output circuit with a conventional clamped ESD circuit; Figure 2 is a diagram showing a large size ODNMOS (open drain NMOS) FIG. 3 is an electrostatic discharge protection circuit according to a preferred embodiment of the present invention; and FIGS. 4(a) to (f) are circuit diagrams of the blocking charging unit of the first to fifth embodiments of the present invention. [Main component symbol description]
1 輸出電路 11 ESD箝制電路 VCC 電壓源 12 接地端 13 PMOS 14 NMOS 15 二極體 16 輸出單元 2 輸出電路 21 第一電容 22 第二電容 23 第一 NMOS 24 第二 NMOS 25 二極體 IN 電壓源 4 靜電放電防護電路 42 升位電路 41 偶數級電路 44 輸出電路 43 與否邏輯閘 S1 〜S2 複數個反向器 45 輸出單元 422 第二 PMOS 421 電阻 46 接地端 423 第一電容 442 第一 NMOS 441 第一 PMOS 444 第二 NMOS 443 阻斷充電單元 60 第三PMOS 51 第一二極體 200929781 54 第一高阻抗電阻 53 第三二極體 56 第四二極體 55 第二高阻抗電阻 58 第三高阻抗電阻 57 第五二極體 61 第七二極體 59 第六二極體 62 第一電晶體1 Output circuit 11 ESD clamp circuit VCC Voltage source 12 Ground terminal 13 PMOS 14 NMOS 15 Diode 16 Output unit 2 Output circuit 21 First capacitor 22 Second capacitor 23 First NMOS 24 Second NMOS 25 Diode IN voltage source 4 Electrostatic discharge protection circuit 42 Ascending circuit 41 Even-numbered circuit 44 Output circuit 43 or not Logic gate S1 ～S2 A plurality of inverters 45 Output unit 422 Second PMOS 421 Resistor 46 Ground terminal 423 First capacitor 442 First NMOS 441 First PMOS 444 second NMOS 443 blocking charging unit 60 third PMOS 51 first diode 200929781 54 first high impedance resistor 53 third diode 56 fourth diode 55 second high impedance resistor 58 third High-impedance resistor 57 fifth diode 61 seventh diode 59 sixth diode 62 first transistor
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