CN112600521B - Switch circuit for adjusting offset voltage of amplifier, adjusting circuit and amplifier - Google Patents
Switch circuit for adjusting offset voltage of amplifier, adjusting circuit and amplifier Download PDFInfo
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- CN112600521B CN112600521B CN202110227217.6A CN202110227217A CN112600521B CN 112600521 B CN112600521 B CN 112600521B CN 202110227217 A CN202110227217 A CN 202110227217A CN 112600521 B CN112600521 B CN 112600521B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
Abstract
The invention discloses a switching circuit for trimming offset voltage of an amplifier, a trimming circuit and an amplifier. The switching circuit for adjusting the offset voltage of the amplifier is used for controlling the working state of the amplifier; the first end of the first switch circuit is connected to a first input signal; the second end of the first switch circuit is electrically connected with the first input end of the amplifying module; the first end of the second switch circuit is connected with a second input signal, and the second end of the second switch circuit is electrically connected with the second input end of the amplifying module; the first short circuit is connected between two input ends of the amplification module and is connected with a first power supply signal; the second short circuit is connected between the two input ends of the amplifying module and is connected to a second power supply signal. The first power signal and the second power signal have different electric potentials. The embodiment of the invention can improve the trimming precision of the offset voltage of the amplifier.
Description
Technical Field
The embodiment of the invention relates to the technical field of amplifiers, in particular to a switching circuit for adjusting offset voltage of an amplifier, an adjusting circuit and an amplifier.
Background
At present, amplifiers are widely applied in the fields of industrial control systems, instruments and meters, medical equipment, security monitoring, communication, automobiles and the like. Ideally, when the voltages at the two inputs of an amplifier are the same, the output voltage should always be zero regardless of the gain. In practice, however, the output of the amplifier is not zero in this case due to problems in the manufacturing process and the like. The difference between the voltages of the two input ends when the output voltage is zero is the Offset voltage (Vos) of the operational amplifier.
The existence of offset voltage directly influences the precision index of the equipment or system applying the amplifier. Therefore, reducing the offset voltage is important in high-precision circuit system design. Generally, in order to reduce the offset voltage, a common solution is to adjust the offset voltage by modifying an internal circuit by using a laser or a fuse or other technology during the chip processing. However, the above method has complicated process and expensive equipment, and the offset voltage may change again after the chip processing is completed. Therefore, the existing offset voltage trimming method has the problem of low precision.
Disclosure of Invention
The embodiment of the invention provides a switching circuit for trimming offset voltage of an amplifier, a trimming circuit and an amplifier, so as to improve the trimming precision of the offset voltage of the amplifier.
In a first aspect, an embodiment of the present invention provides a switching circuit for adjusting an offset voltage of an amplifier, where the switching circuit is configured to control a working state of the amplifier; the switching circuit includes: the first input end, the second input end, the first output end, the second output end, the first switch circuit, the second switch circuit, the first short circuit and the second short circuit;
the first end of the first switch circuit is a first input end of the switch circuit and is connected with a first input signal; the second end of the first switch circuit is a first output end of the switch circuit and is electrically connected with a first input end of the amplifying module; the first end of the second switch circuit is a second input end of the switch circuit and is connected with a second input signal; the second end of the second switch circuit is a second output end of the switch circuit and is electrically connected with a second input end of the amplifying module;
a first end of the first short circuit is electrically connected with a second end of the first switch circuit, the second end of the first short circuit is connected with a first power signal, and a third end of the first short circuit is electrically connected with a second end of the second switch circuit; a first end of the second short circuit is electrically connected with a second end of the first switch circuit, the second end of the second short circuit is connected with a second power supply signal, and a third end of the second short circuit is electrically connected with a second end of the second switch circuit; wherein the first power signal and the second power signal have different potentials.
Optionally, the operating state of the amplifier comprises:
in a normal working state, the first switch circuit and the second switch circuit are switched on, and the first short-circuit and the second short-circuit are switched off;
the first input tube is in a first input tube trimming state, the first switch circuit, the second switch circuit and the first short circuit are disconnected, and the second short circuit is connected;
and the second type input tube is in a trimming state, the first switch circuit, the second switch circuit and the second short-circuit are disconnected, and the first short-circuit is switched on.
Optionally, the first switching circuit comprises: a first transistor; a gate of the first transistor is connected to a first control signal, a first pole of the first transistor is a first end of the first switch circuit, and a second pole of the first transistor is a second end of the first switch circuit;
the second switching circuit includes: a second transistor; the grid electrode of the second transistor is connected with a second control signal, the first pole of the second transistor is the first end of the second switch circuit, and the second pole of the second transistor is the second end of the second switch circuit.
Optionally, the polarities of the first transistor and the second transistor are the same, and the first control signal is multiplexed into the second control signal.
Optionally, the first switch circuit further comprises a third transistor; a first pole of the third transistor is electrically connected with the first pole of the first transistor, a second pole of the third transistor is electrically connected with the second pole of the first transistor, and a grid electrode of the third transistor is connected with a third control signal; wherein the first transistor and the third transistor are of different polarities;
the second switching circuit further comprises a fourth transistor; a first pole of the fourth transistor is electrically connected with the first pole of the second transistor, a second pole of the fourth transistor is electrically connected with the second pole of the second transistor, and a gate of the fourth transistor is connected with a fourth control signal; wherein the second transistor and the fourth transistor are different in polarity.
Optionally, the first switch circuit further comprises a fifth transistor, a sixth transistor and a seventh transistor;
the grid electrode of the fifth transistor is connected with the first control signal; a first pole of the fifth transistor is electrically connected to the second pole of the first transistor, the first pole of the sixth transistor, and the first pole of the seventh transistor, respectively; a second pole of the fifth transistor is connected to a reference voltage signal; the grid electrode of the sixth transistor is connected with the first control signal; a second pole of the sixth transistor is electrically connected to a second pole of the seventh transistor and serves as a second end of the first switch circuit; the gate of the seventh transistor is connected to the third control signal; the polarities of the first transistor and the sixth transistor are the same; the third transistor, the fifth transistor, and the seventh transistor have the same polarity;
the second switch circuit further includes an eighth transistor, a ninth transistor, and a tenth transistor;
the grid electrode of the eighth transistor is connected with the second control signal; a first pole of the eighth transistor is electrically connected to the second pole of the second transistor, the first pole of the ninth transistor, and the first pole of the tenth transistor, respectively; a second pole of the eighth transistor is connected to the reference voltage signal; the grid electrode of the ninth transistor is connected with the second control signal; a second pole of the ninth transistor is electrically connected to a second pole of the tenth transistor and serves as a second end of the second switch circuit; the gate of the tenth transistor is connected to the fourth control signal; the polarities of the second transistor and the ninth transistor are the same; the polarity of the fourth transistor, the eighth transistor, and the tenth transistor is the same.
Optionally, the first short circuit includes: an eleventh transistor and a twelfth transistor;
a gate of the eleventh transistor is connected to a fifth control signal; a first pole of the eleventh transistor is a first end of the first short circuit; a second pole of the eleventh transistor is electrically connected with a second pole of the twelfth transistor and serves as a second end of the first short circuit; the grid electrode of the twelfth transistor is connected with the fifth control signal; a first pole of the twelfth transistor is a third end of the first short circuit; the eleventh transistor and the twelfth transistor have the same polarity.
Optionally, the second short circuit includes: a thirteenth transistor and a fourteenth transistor;
the grid electrode of the thirteenth transistor is connected with a sixth control signal; a first pole of the thirteenth transistor is a first end of the second short circuit; a second pole of the thirteenth transistor is electrically connected with a second pole of the fourteenth transistor and serves as a second end of the second short circuit; the gate of the fourteenth transistor is connected to the sixth control signal; a first pole of the fourteenth transistor is a third end of the second short circuit; the polarity of the thirteenth transistor and the fourteenth transistor is the same.
In a second aspect, an embodiment of the present invention further provides a trimming circuit, including: the control circuit, the compensation circuit and the switch circuit for adjusting the offset voltage of the amplifier are provided by any embodiment of the invention;
the control circuit is electrically connected with the switch circuit, and the control circuit is electrically connected with the compensation circuit; the compensation circuit is electrically connected with the first input end of the amplification module, the second input end of the amplification module and the output end of the amplification module respectively.
In a third aspect, an embodiment of the present invention further provides an amplifier, including: such as the trimming circuit provided by any of the embodiments of the present invention.
The switching circuit for adjusting the offset voltage of the amplifier, provided by the embodiment of the invention, is provided with the first switching circuit and the second switching circuit, and can control the connection state between the amplifying module and the first input signal and the second input signal. For example, when the amplifier is modified, the connection between the amplification module and the two input signals is disconnected. Meanwhile, a first short circuit is arranged in the switch circuit and connected with a first power supply signal; and the second short circuit is connected with a second power supply signal. Because the first power supply signal and the second power supply signal have different electric potentials, when the first short-circuit short-circuits the two input ends of the amplification module to the first power supply signal, the transistor with one polarity in the amplification module is conducted, and the trimming circuit can correct offset voltage caused by the transistor; when the second short circuit short-circuits the two input ends of the amplifying module to the second power signal, the transistor with the other polarity in the amplifying module is turned on, and the trimming circuit can correct the offset voltage caused by the transistor. The offset voltages caused by the two types of transistors are different when the two types of transistors are conducted, so that the embodiment of the invention can realize the respective trimming of the transistors with different polarities in the amplification module, and the trimming precision of the offset voltage of the amplifier is improved.
Drawings
Fig. 1 is a schematic structural diagram of a switching circuit for adjusting an offset voltage of an amplifier according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an amplifying module according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another switching circuit for adjusting an offset voltage of an amplifier according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a control timing sequence of a switch circuit for adjusting an offset voltage of an amplifier according to an embodiment of the present invention;
fig. 5 is a schematic diagram of an equivalent circuit of a switching circuit in a second-type input tube trimming state according to an embodiment of the present invention;
FIG. 6 is a simplified equivalent circuit diagram of a switch circuit in a second type input tube trimming state according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of another switching circuit for adjusting an offset voltage of an amplifier according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of an equivalent circuit of another switch circuit according to an embodiment of the present invention in a second type input tube trimming state;
FIG. 9 is a simplified equivalent circuit diagram of another switch circuit according to an embodiment of the present invention in a second type input tube trimming state;
fig. 10 is a schematic structural diagram of a trimming circuit according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
The embodiment of the invention provides a switching circuit for adjusting offset voltage of an amplifier. Fig. 1 is a schematic structural diagram of a switching circuit for adjusting an offset voltage of an amplifier according to an embodiment of the present invention. As shown in fig. 1, the switching circuit 10 includes: a first input terminal, a second input terminal, a first output terminal, a second output terminal, a first switch circuit 110, a second switch circuit 120, a first short circuit 130, and a second short circuit 140.
The first terminal of the first switch circuit 110 is a first input terminal of the switch circuit 10, and is connected to a first input signal VIP _ PIN; the second terminal of the first switch circuit 110 is a first output terminal of the switch circuit 10 and is electrically connected to a first input terminal of the amplifying module 20; the first end of the second switch circuit 120 is a second input end of the switch circuit 10, and is connected to a second input signal VIN _ PIN; the second terminal of the second switch circuit 120 is a second output terminal of the switch circuit 10 and is electrically connected to a second input terminal of the amplifying module 20. A first end of the first short circuit 130 is electrically connected to a second end of the first switch circuit 110, the second end of the first short circuit 130 is connected to a first power signal VDD, and a third end of the first short circuit 130 is electrically connected to a second end of the second switch circuit 120; a first end of the second short circuit 140 is electrically connected to a second end of the first switch circuit 110, a second end of the second short circuit 140 is connected to the second power signal VSS, and a third end of the second short circuit 140 is electrically connected to a second end of the second switch circuit 120; the first power signal VDD and the second power signal VSS have different potentials.
The amplifying module 20 is configured to amplify a difference between a signal input by the first input terminal and a signal input by the second input terminal, and convert the difference into an output signal Vout for output. Ideally, if the voltages at the two input terminals of the amplifying module 20 are identical, the output signal Vout should be 0V. In practice, a small differential voltage must also be applied at the input terminals, forcing the output signal Vout to 0V. The small differential voltage is called offset voltage Vos, and the offset voltage Vos of a general operational amplifier (i.e. the amplification module 20) is usually several millivolts, so that the amplification module 20 generates a large error when operating, especially when performing a precise operational amplifier or when using a dc amplifier. Therefore, the offset voltage Vos needs to be trimmed.
The switch circuit 10 is used to control the operating state of the amplifier (e.g., control whether the amplifier is in the trimming state). Specifically, the first switch circuit 110 is configured to control a connection state of a first input terminal of the amplification block 20 and a first input signal VIP _ PIN; alternatively, the first switch circuit 110 may be formed of a switching device such as a transistor. The second switch circuit 120 is configured to control a connection state between the second input terminal of the amplifying module 20 and the second input signal VIN _ PIN; alternatively, the second switch circuit 120 may be formed of a switching device such as a transistor. The first short-circuit switch circuit 130 is configured to control whether the first input terminal and the second input terminal of the amplifying module 20 are short-circuited to the first power signal VDD; alternatively, the first short circuit 130 may be formed of a switching device such as a transistor. The second short-circuit switch circuit 140 is used for controlling whether the first input terminal and the second input terminal of the amplifying module 20 are short-circuited to the second power signal VSS; alternatively, the second short circuit 140 may be formed of a switching device such as a transistor.
The switching circuit for adjusting the offset voltage of the amplifier according to the embodiment of the present invention is provided with the first switching circuit 110 and the second switching circuit 120, and can control the connection state between the amplifying module 20 and the first input signal VIP _ PIN and the second input signal VIN _ PIN. For example, when the amplifier is trimmed, the amplification block 20 is disconnected from the two input signals. Meanwhile, the switch circuit 10 is provided with a first short circuit 130 connected to a first power supply signal VDD; and a second short circuit 140 connected to a second power signal VSS. Because the first power signal VDD and the second power signal VSS have different potentials, when the first short circuit 130 shorts the two input ends of the amplifying module 20 to the first power signal VDD, the transistor with one polarity in the amplifying module 20 is turned on, and the trimming circuit can correct the offset voltage caused by the transistor; when the second short circuit 140 short-circuits the two input terminals of the amplifying module 20 to the second power signal VSS, the transistor with the other polarity in the amplifying module 20 is turned on, and the trimming circuit can correct the offset voltage caused by the transistor. The offset voltages caused by the two transistors are different when the two transistors are turned on, so that the embodiments of the present invention can implement respective trimming of the transistors with different polarities in the amplifying module 20, thereby improving the trimming precision of the offset voltage of the amplifier.
Fig. 2 is a schematic structural diagram of an amplifying module according to an embodiment of the present invention. The above embodiments exemplarily give the function of the switch circuit 10, and the operation state of the amplifier will be specifically described below with reference to fig. 2.
First, referring to fig. 2, the amplification module 20 includes an input unit 210 and an output unit 220. A first input terminal of the input unit 210 is a first input terminal of the amplifying module 20, a second input terminal of the input unit 210 is a second input terminal of the amplifying module 20, and an output terminal of the output unit 220 is an output terminal of the amplifying module 20. In the input unit 210, the first P-type transistor MP1 and the second P-type transistor MP2 are both first-type input transistors, and both form a first input pair group, first poles of both are connected to the first power signal VDD through the first current source I1, and second poles of both are electrically connected to the output unit 220. The first N-type transistor MN1 and the second N-type transistor MN2 are both a second-type input transistor, and both constitute a second input pair group, first poles of both are connected to the second power signal VSS through the second current source I2, and second poles are both electrically connected to the output unit 220. The gate of the first P-type transistor MP1 and the gate of the first N-type transistor MN1 are both switched in the first output signal VIP _ INT of the switch circuit 10; the gate of the second P-type transistor MP2 and the gate of the second N-type transistor MN2 are both coupled to the second output signal VIN _ INT of the switch circuit 10.
Since the offset voltages Vos caused by the P-type pair transistors and the N-type pair transistors are different in the amplification module 20, the P-type pair transistors and the N-type pair transistors need to be respectively trimmed. Thus, the operational states of the amplifier include: normal working state, first type input tube trimming state and second type input tube trimming state. The first power signal VDD is at a high level and the second power signal VSS is at a low level.
In a normal operating state, the first switch circuit 110 and the second switch circuit 120 are turned on, and the first short circuit 130 and the second short circuit 140 are turned off; the switch circuit 10 transmits its first input signal VIP _ PIN to the first output terminal, and outputs it as a first output signal VIP _ INT to the amplification block 20; the switch circuit 10 transmits the second input signal VIN _ PIN to the second output terminal, and outputs the second input signal VIN _ PIN as a second output signal VIN _ INT to the amplifying module 20; that is, the amplifying module 20 directly processes and outputs two input signals inputted by the amplifier, and the amplifier normally operates.
Under the first type input tube trimming state, the first switch circuit 110, the second switch circuit 120 and the first short circuit 130 are disconnected, and the second short circuit 140 is connected; the switching circuit 10 shorts both input terminals of the amplifying block 20 to the second power signal VSS, that is, both the first output signal VIP _ INT and the second output signal VIN _ INT of the switching circuit 10 are low level. Therefore, in the input unit 210 of the amplifying module 20, the first P-type transistor MP1 and the second P-type transistor MP2 are turned on, the first N-type transistor MN1 and the second N-type transistor MN2 are turned off, and in this state, the offset voltage Vos caused by the P-type pair transistors is corrected.
Under the second type input tube trimming state, the first switch circuit 110, the second switch circuit 120 and the second short circuit 140 are disconnected, and the first short circuit 130 is conducted; the switch circuit 10 shorts two input terminals of the amplification block 20 to the first power signal VDD, that is, both the first output signal VIP _ INT and the second output signal VIN _ INT of the switch circuit 10 are high level. Therefore, in the input unit 210 of the amplifying module 20, the first P-type transistor MP1 and the second P-type transistor MP2 are turned off, the first N-type transistor MN1 and the second N-type transistor MN2 are turned on, and in this state, the offset voltage Vos caused by the pair of N-type transistors is corrected.
It should be noted that the structure of the amplifying module 20 is only an exemplary structure, and is not a limitation of the present invention. In other embodiments, the amplifying module 20 may have other structures, and the switching circuit 10 may control the amplifier to switch different operation states as long as transistors with different polarities are included therein.
The above embodiments exemplarily explain the function of the switch circuit 10, and optionally, the structure of the switch circuit 10 is various, and several of them will be described below.
Fig. 3 is a schematic structural diagram of another switching circuit for adjusting an offset voltage of an amplifier according to an embodiment of the present invention. Referring to fig. 3, in one embodiment, the first switching circuit 110 optionally includes: a first transistor M1; the gate of the first transistor N1 is connected to the first control signal S1, the first terminal of the first transistor M1 is the first terminal of the first switch circuit 110, and the second terminal of the first transistor M1 is the second terminal of the first switch circuit 110.
The second switching circuit 120 includes: a second transistor M2; the gate of the second transistor M2 is connected to the second control signal S2, the first terminal of the second transistor M2 is the first terminal of the second switch circuit 120, and the second terminal of the second transistor M2 is the second terminal of the second switch circuit 120.
In the embodiment of the present invention, the first switch circuit 110 and the second switch circuit 120 are both configured to include only one transistor, so that the circuit structure is simple, the implementation is easy, and the overall size of the amplifier is favorably reduced. Alternatively, the first transistor M1 may be an N-type transistor or a P-type transistor; the second transistor M2 may be an N-type transistor or a P-type transistor.
On the basis of the above embodiments, optionally, the polarities of the first transistor M1 and the second transistor M2 are the same, and the first control signal S1 is multiplexed into the second control signal S2. By the arrangement, the control logic of the circuit can be simplified, and the circuit is easy to realize. Fig. 3 illustrates a case where the first transistor M1 and the second transistor M2 are both P-type transistors, but the present invention is not limited thereto, and in other embodiments, both of them may be N-type transistors.
With continued reference to fig. 3, in addition to the above embodiments, preferably, the first switch circuit 110 further includes a third transistor M3; a first pole of the third transistor M3 is electrically connected to the first pole of the first transistor M1, a second pole of the third transistor M3 is electrically connected to the second pole of the first transistor M1, and a gate of the third transistor M3 is connected to the third control signal S3; wherein, the polarities of the first transistor M1 and the third transistor M3 are different. The second switch circuit 120 further includes a fourth transistor M4; a first pole of the fourth transistor M4 is electrically connected to the first pole of the second transistor M2, a second pole of the fourth transistor M4 is electrically connected to the second pole of the second transistor M2, and a gate of the fourth transistor M4 is connected to the fourth control signal S4; the polarity of the second transistor M2 is different from that of the fourth transistor M4.
In the embodiment of the invention, the third transistor M3 with the opposite polarity to the first transistor M1 is arranged and connected in parallel with the first transistor M1 to form the first switch circuit 110, so that the input range of the first input signal VIP _ PIN can be effectively enlarged, and the first input signal VIP _ PIN can be ensured to be transmitted normally within the range of 0 and VDD. Similarly, the fourth transistor M4 with the polarity opposite to that of the second transistor M2 is arranged and connected in parallel with the second transistor M2 to form the second switch circuit 120, so that the input range of the second input signal VIN _ PIN can be effectively enlarged, and the second input signal VIN _ PIN can be ensured to be normally transmitted within the range of [0, VDD ].
In the above embodiments, optionally, the third transistor M3 and the fourth transistor M4 have the same polarity, and the third control signal S3 is multiplexed into the fourth control signal S4. By the arrangement, the control logic of the circuit can be further simplified, and the circuit is easy to realize.
With continued reference to fig. 3, based on the above embodiments, optionally, the first short circuit 130 includes: an eleventh transistor M11 and a twelfth transistor M12.
The gate of the eleventh transistor M11 is connected to the fifth control signal S5; a first terminal of the eleventh transistor M11 is a first terminal of the first short circuit 130; a second pole of the eleventh transistor M11 is electrically connected to a second pole of the twelfth transistor M12 and serves as a second terminal of the first short circuit 130; the gate of the twelfth transistor M12 is switched on the fifth control signal S5; the first terminal of the twelfth transistor M12 is the third terminal of the first short circuit 130; the eleventh transistor M11 and the twelfth transistor M12 have the same polarity. In this way, the eleventh transistor M11 and the twelfth transistor M12 are ensured to be turned on simultaneously, and when the first short circuit 130 is activated, the two input terminals of the amplifying block are shorted to the first power signal VDD. Alternatively, when the polarity of the eleventh transistor M11 is different from that of the twelfth transistor M12, the magnitude of the potential of the control signal switched in by the eleventh transistor M11 and the twelfth transistor M12 is also different.
With continued reference to fig. 3, based on the above embodiments, optionally, the second short circuit 140 includes: a thirteenth transistor M13 and a fourteenth transistor M14.
The gate of the thirteenth transistor M13 is switched on the sixth control signal S6; a first terminal of the thirteenth transistor M13 is a first terminal of the second short circuit 140; a second pole of the thirteenth transistor M13 is electrically connected to the second pole of the fourteenth transistor M14 and serves as a second terminal of the second short circuit 140; the gate of the fourteenth transistor M14 is connected to the sixth control signal S6; the first terminal of the fourteenth transistor M14 is the third terminal of the second short circuit 140; the thirteenth transistor M13 and the fourteenth transistor M14 have the same polarity. In this way, the thirteenth transistor M13 and the fourteenth transistor M14 are ensured to be turned on simultaneously, and when the second short circuit 140 is activated, the two input terminals of the amplifying block are shorted to the second power signal VSS. Alternatively, when the polarity of the thirteenth transistor M13 and the polarity of the fourteenth transistor M14 are different, the magnitudes of the potentials of the control signals switched in by the thirteenth transistor M13 and the fourteenth transistor M14 are also different.
Fig. 4 is a schematic control timing diagram of a switching circuit for adjusting an offset voltage of an amplifier according to an embodiment of the present invention. Next, a control process of the switching circuit 10 will be described with reference to fig. 3 and 4.
The operation of the switching circuit 10 includes:
in the first-type input tube trimming stage T1, the first control signal S1, the second control signal S2, the fifth control signal S5 and the sixth control signal S6 are all at high level, and the third control signal S3 and the fourth control signal S4 are all at low level. The thirteenth transistor M13 and the fourteenth transistor M14 are turned on, and the other transistors are turned off, that is, only the second short circuit 140 is turned on, so as to short-circuit the two input terminals of the amplifying module to the second power signal VSS.
In the second-type input tube trimming stage T2, the first control signal S1 and the second control signal S2 are both high, and the third control signal S3, the fourth control signal S4, the fifth control signal S5 and the sixth control signal S6 are all low. The eleventh transistor M11 and the twelfth transistor M12 are turned on, and the other transistors are turned off, that is, only the first short circuit 130 is turned on, so as to short-circuit the two input terminals of the amplifying module to the first power signal VDD.
In the normal operation stage T3, the first control signal S1, the second control signal S2 and the sixth control signal S6 are all at low level, and the third control signal S3, the fourth control signal S4 and the fifth control signal S5 are all at high level. The first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are all turned on, and the other transistors are turned off, that is, the first switch circuit 110 and the second switch circuit 120 are turned on, and the amplifier operates normally. Optionally, the normal operation stage T3 may be performed after the first type input tube is trimmed and the second type input tube is trimmed for a plurality of times, and the trimming accuracy of the offset voltage Vos meets the requirement, so as to ensure the trimming effect of the offset voltage Vos of the amplifier.
The switch circuit 10 provided in the foregoing embodiments can implement respective trimming of transistors with different polarities in the amplification module. In the trimming process, two input ends of the amplifying module are short-circuited to the first power supply signal VDD or the second power supply signal VSS. Ideally, the first output signal VIP _ INT and the second output signal VIN _ INT of the switching circuit 10 should be equal, and the voltage difference between the input terminals of the amplifying block should be 0V. However, in practical applications, the existence of the switch circuit 10 will bring a new error (denoted as Δ V) to the amplifying circuit due to its own structure, and the error Δ V will be superimposed on the offset voltage Vos, so that the first output signal VIP _ INT and the second output signal VIN _ INT are not equal to each other, and thus an error occurs in the trimming result.
Next, an error Δ V caused by the switching circuit 10 shown in fig. 3 is explained by taking the switching circuit 10 as an example in the second-type input tube trimming stage.
Fig. 5 is a schematic diagram of an equivalent circuit of a switching circuit in a second-type input tube trimming state according to an embodiment of the present invention. Referring to fig. 5, the switch circuit 10 can be simplified in terms of resistance to be equivalent during trimming of the second type input tube (N-type input tube). Assuming that the eleventh transistor M11 and the twelfth transistor M12 are identical (meaning the sizes are identical and the matching error is ignored), Rp _ on represents the on-resistance of the two pull-up switches; the thirteenth transistor M13 and the fourteenth transistor M14 are identical, and Rn _ leak represents the resistance of the two pull-down switches in the off state due to leakage; the first transistor M1 and the third transistor M3 are equivalent to a first switch tube, and the second transistor M2 and the fourth transistor M4 are equivalent to a second switch tube, and given that the first switch tube and the second switch tube are identical, Rsw _ leak represents the resistance of the two switch tubes in the off state due to leakage.
Typically Rn _ leak > > Rsw _ leak, so fig. 5 can be simplified to the form of fig. 6. Referring to fig. 6, the first output signal VIP _ INT and the second output signal VIN _ INT of the switching circuit 10 may be obtained as:
VIP_INT=(VDD-VIP_PIN)*Rsw_leak/(Rp_on+Rsw_leak)+VIP_PIN；
VIN_INT=(VDD-VIN_PIN)*Rsw_leak/(Rp_on+Rsw_leak)+VIN_PIN
the error Δ V thus obtained is:
ΔV=VIP_INT-VIN_INT=Rp_on/(Rp_on+Rsw_leak)*(VIP_PIN-VIN_PIN)
as can be seen from the above equation, the error Δ V is related to Rp _ on, Rsw _ leak, and the difference between the voltages at the inputs of the amplifier, VIP _ PIN-VIN _ PIN. Usually Rsw _ leak > > Rp _ on, so the above formula can be simplified as:
ΔV=Rp_on/Rsw_leak*(VIP_PIN-VIN_PIN)
in the above circuit configuration, the voltage difference VIP _ PIN-VIN _ PIN is related to the external input voltage, and generally, the voltages of the two input signals of the amplifier are different, the maximum value of the absolute value of the difference between the two input signals is VDD, and the larger the difference is, the larger the error Δ V is. In addition, at a high temperature (above 85 ℃), the leakage of the semiconductor device increases exponentially, Rsw _ leak decreases rapidly, and the influence of the voltage difference VIP _ PIN-VIN _ PIN on the error Δ V is further amplified.
Therefore, in order to minimize the influence of the error Δ V, the embodiments of the present invention are further improved on the basis of the above-described embodiments.
In one embodiment, the on-resistance Rp _ on of the pull-up switch can be optionally reduced by increasing the sizes of the eleventh transistor M11 and the twelfth transistor M12, and the influence of external voltage and temperature variation on the output of the trimming circuit can also be reduced.
Fig. 7 is a schematic structural diagram of another switching circuit for adjusting an offset voltage of an amplifier according to an embodiment of the present invention. Referring to fig. 7, in an embodiment, the first switch circuit 110 further optionally includes a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7; the second switch circuit 120 further includes an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10.
The gate of the fifth transistor M5 is connected to the first control signal S1; a first pole of the fifth transistor M5 is electrically connected to the second pole of the first transistor M1, the first pole of the sixth transistor M6, and the first pole of the seventh transistor M7, respectively; a second pole of the fifth transistor M5 is connected to the reference voltage signal VREF; the gate of the sixth transistor M6 is switched on the first control signal S1; a second pole of the sixth transistor M6 is electrically connected to a second pole of the seventh transistor M7 and serves as a second terminal of the first switch circuit 110; the gate of the seventh transistor M7 is switched on the third control signal S3; the polarities of the first transistor M1 and the sixth transistor M6 are the same; the polarities of the third transistor M3, the fifth transistor M5 and the seventh transistor M7 are the same; the gate of the eighth transistor M8 is switched on the second control signal S2; a first pole of the eighth transistor M8 is electrically connected to the second pole of the second transistor M2, the first pole of the ninth transistor M9, and the first pole of the tenth transistor M10, respectively; a second pole of the eighth transistor M8 is connected to the reference voltage signal VREF; the gate of the ninth transistor M9 is switched on the second control signal S2; a second pole of the ninth transistor M9 is electrically connected to the second pole of the tenth transistor M10 and serves as a second terminal of the second switch circuit 120; the gate of the tenth transistor M10 is switched on the fourth control signal S4; the polarities of the second transistor M2 and the ninth transistor M9 are the same; the polarities of the fourth transistor M4, the eighth transistor M8, and the tenth transistor M10 are the same.
The first switch circuit 110 includes a first transistor M1, a third transistor M3, a fifth transistor M5, a sixth transistor M6, and a seventh transistor M7, and forms a T-type switch tube; the second switch circuit 120 includes a second transistor M2, a fourth transistor M4, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10, and forms a T-type switch transistor, so that the influence of the error Δ V can be reduced. Alternatively, the on-resistance of the switching device may be made the same as in each of the embodiments described above by increasing the size of the device in the first switching circuit 110 and the second switching circuit 120. The specific analysis of error Δ V is as follows:
under the action of the switch circuit 10, the operating states of the amplifier still include three types, namely a normal operating state, a first-type input tube trimming state and a second-type input tube trimming state, and reference is still made to the timing chart shown in fig. 4, and for convenience of understanding, the switch circuit 10 is still explained in the second-type input tube trimming stage as an example.
In the second-type input-tube trimming stage T2, the first control signal S1 and the second control signal S2 are both high, and the third control signal S3, the fourth control signal S4, the fifth control signal S5 and the sixth control signal S6 are all low. The fifth transistor M5, the eighth transistor M8, the eleventh transistor M11 and the twelfth transistor M12 are turned on, and the other transistors are turned off, that is, the first short circuit 130 is turned on, so as to short-circuit the two input terminals of the amplifying module to the first power signal VDD. And, the reference voltage signal VREF is loaded on the intermediate node G1 of the first switch circuit 110 through the fifth transistor M5; the reference voltage signal VREF is loaded on the intermediate node G2 of the second switching circuit 120 through the eighth transistor M8.
At this time, the equivalent circuit diagram of the switch circuit 10 is as shown in fig. 8, referring to fig. 8, assuming that the eleventh transistor M11 and the twelfth transistor M12 are identical (meaning that the sizes are identical and the matching error is ignored), Rp _ on represents the on-resistances of the two pull-up switches; the thirteenth transistor M13 and the fourteenth transistor M14 are identical, and Rn _ leak represents the resistance of the two pull-down switches in the off state due to leakage; the first transistor M1 and the third transistor M3 are equivalent to a first switch tube, the second transistor M2 and the fourth transistor M4 are equivalent to a second switch tube, the sixth transistor M6 and the seventh transistor M7 are equivalent to a third switch tube, the ninth transistor M9 and the tenth transistor M10 are equivalent to a fourth switch tube, and Rsw _ leak represents resistance of the four switch tubes in an off state due to leakage assuming that the first switch tube, the second switch tube, the third switch tube and the fourth switch tube are identical; the fifth transistor M5 and the eighth transistor M8 are identical, and Rn _ on represents the on-resistance of the two pull-up switches.
Typically Rn _ on is small and can be considered as a short circuit, and Rn _ leak is large and can be considered as an open circuit. Therefore, fig. 8 can be simplified to the form of fig. 9, and referring to fig. 9, the first output signal VIP _ INT and the second output signal VIN _ INT of the switch circuit 10 can be obtained as follows:
VIP_INT=(VDD-VREF)*Rsw_leak/(Rp_on+Rsw_leak)+VREF；
VIN_INT=(VDD-VREF)*Rsw_leak/(Rp_on+Rsw_leak)+VREF
the error Δ V thus obtained is:
ΔV=VIP_INT-VIN_INT=0V
it can be seen from the above formula that the switching circuit 10 in the implementation of the present invention can completely eliminate the trimming error Δ V of the offset voltage Vos generated by the difference of the input voltages of the amplifiers under ideal conditions (the device sizes are consistent and matched). In practical applications (i.e. non-ideal situations) the error may be reduced to negligible.
Alternatively, the reference voltage signal VREF may be the second power supply signal VSS, and its value may be set to 0, so that the circuit configuration may be simplified.
The embodiment of the invention also provides a trimming circuit, which comprises the switching circuit provided by any embodiment of the invention and has corresponding beneficial effects. Fig. 10 is a schematic structural diagram of a trimming circuit according to an embodiment of the present invention. Referring to fig. 10, the trimming circuit includes: a control circuit 30, a compensation circuit 40 and a switch circuit 10 for amplifier offset voltage trimming as provided by any of the embodiments of the present invention.
Wherein, the control circuit 30 is electrically connected with the switch circuit 10, and the control circuit 30 is electrically connected with the compensation circuit 40; the compensation circuit 40 is electrically connected to the first input terminal of the amplification module 20, the second input terminal of the amplification module 20, and the output terminal of the amplification module 20, respectively. The control circuit 30 is configured to send control signals to the switching circuit 10 and the compensation circuit 40, respectively, so that the switching circuit 10 controls the operating state of the amplifier, and controls the compensation circuit 40 to be inoperative in the normal operating state of the amplifier, and perform corresponding compensation in different trimming states of the amplifier.
Illustratively, the operating principle of the trimming circuit is as follows: after the amplifier is started, the control circuit 30 controls the state of the switch circuit 10 to make the amplifier enter a certain trimming mode, and the compensation circuit 40 reads the output of the amplification module 20, converts the output into a digital signal of the offset voltage Vos, and stores the digital signal in the memory of the compensation circuit 40. In normal operation of the amplifier, the compensation circuit 40 reads the stored offset voltage information and generates a corresponding bias current at the input stage of the amplifying module 20 to correct the offset voltage Vos of the amplifier, thereby achieving the purpose of reducing the offset voltage Vos.
An embodiment of the present invention further provides an amplifier, including: the trimming circuit provided by any embodiment of the invention has corresponding beneficial effects.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (7)
1. The switch circuit is used for adjusting the offset voltage of the amplifier and is characterized in that the switch circuit is used for controlling the working state of the amplifier; the switching circuit includes: the first input end, the second input end, the first output end, the second output end, the first switch circuit, the second switch circuit, the first short circuit and the second short circuit;
the first end of the first switch circuit is a first input end of the switch circuit and is connected with a first input signal; the second end of the first switch circuit is a first output end of the switch circuit and is electrically connected with a first input end of the amplifying module; the first end of the second switch circuit is a second input end of the switch circuit and is connected with a second input signal; the second end of the second switch circuit is a second output end of the switch circuit and is electrically connected with a second input end of the amplifying module;
a first end of the first short circuit is electrically connected with a second end of the first switch circuit, the second end of the first short circuit is connected with a first power signal, and a third end of the first short circuit is electrically connected with a second end of the second switch circuit; a first end of the second short circuit is electrically connected with a second end of the first switch circuit, the second end of the second short circuit is connected with a second power supply signal, and a third end of the second short circuit is electrically connected with a second end of the second switch circuit; wherein the first power signal and the second power signal have different potentials;
the first switching circuit includes: a first transistor; a gate of the first transistor is connected to a first control signal, a first pole of the first transistor is a first end of the first switch circuit, and a second pole of the first transistor is a second end of the first switch circuit;
the second switching circuit includes: a second transistor; a gate of the second transistor is connected to a second control signal, a first pole of the second transistor is a first end of the second switch circuit, and a second pole of the second transistor is a second end of the second switch circuit;
the first switch circuit further includes a third transistor; a first pole of the third transistor is electrically connected with the first pole of the first transistor, a second pole of the third transistor is electrically connected with the second pole of the first transistor, and a grid electrode of the third transistor is connected with a third control signal; wherein the first transistor and the third transistor are of different polarities;
the second switching circuit further comprises a fourth transistor; a first pole of the fourth transistor is electrically connected with the first pole of the second transistor, a second pole of the fourth transistor is electrically connected with the second pole of the second transistor, and a gate of the fourth transistor is connected with a fourth control signal; wherein the polarities of the second transistor and the fourth transistor are different;
the first switch circuit further includes a fifth transistor, a sixth transistor, and a seventh transistor;
the grid electrode of the fifth transistor is connected with the first control signal; a first pole of the fifth transistor is electrically connected to the second pole of the first transistor, the first pole of the sixth transistor, and the first pole of the seventh transistor, respectively; a second pole of the fifth transistor is connected to a reference voltage signal; the grid electrode of the sixth transistor is connected with the first control signal; a second pole of the sixth transistor is electrically connected to a second pole of the seventh transistor and serves as a second end of the first switch circuit; the gate of the seventh transistor is connected to the third control signal; the polarities of the first transistor and the sixth transistor are the same; the third transistor, the fifth transistor, and the seventh transistor have the same polarity;
the second switch circuit further includes an eighth transistor, a ninth transistor, and a tenth transistor;
the grid electrode of the eighth transistor is connected with the second control signal; a first pole of the eighth transistor is electrically connected to the second pole of the second transistor, the first pole of the ninth transistor, and the first pole of the tenth transistor, respectively; a second pole of the eighth transistor is connected to the reference voltage signal; the grid electrode of the ninth transistor is connected with the second control signal; a second pole of the ninth transistor is electrically connected to a second pole of the tenth transistor and serves as a second end of the second switch circuit; the gate of the tenth transistor is connected to the fourth control signal; the polarities of the second transistor and the ninth transistor are the same; the polarity of the fourth transistor, the eighth transistor, and the tenth transistor is the same.
2. The switching circuit for amplifier offset voltage trimming of claim 1, wherein the operating state of the amplifier comprises:
in a normal working state, the first switch circuit and the second switch circuit are switched on, and the first short-circuit and the second short-circuit are switched off;
the first input tube is in a first input tube trimming state, the first switch circuit, the second switch circuit and the first short circuit are disconnected, and the second short circuit is connected;
and the second type input tube is in a trimming state, the first switch circuit, the second switch circuit and the second short-circuit are disconnected, and the first short-circuit is switched on.
3. The switch circuit for amplifier offset voltage trimming of claim 1, wherein the first transistor and the second transistor have the same polarity, and the first control signal is multiplexed into the second control signal.
4. The switching circuit for amplifier offset voltage trimming of claim 1, wherein the first shorting circuit comprises: an eleventh transistor and a twelfth transistor;
a gate of the eleventh transistor is connected to a fifth control signal; a first pole of the eleventh transistor is a first end of the first short circuit; a second pole of the eleventh transistor is electrically connected with a second pole of the twelfth transistor and serves as a second end of the first short circuit; the grid electrode of the twelfth transistor is connected with the fifth control signal; a first pole of the twelfth transistor is a third end of the first short circuit; the eleventh transistor and the twelfth transistor have the same polarity.
5. The switching circuit for amplifier offset voltage trimming of claim 1, wherein the second shorting circuit comprises: a thirteenth transistor and a fourteenth transistor;
the grid electrode of the thirteenth transistor is connected with a sixth control signal; a first pole of the thirteenth transistor is a first end of the second short circuit; a second pole of the thirteenth transistor is electrically connected with a second pole of the fourteenth transistor and serves as a second end of the second short circuit; the gate of the fourteenth transistor is connected to the sixth control signal; a first pole of the fourteenth transistor is a third end of the second short circuit; the polarity of the thirteenth transistor and the fourteenth transistor is the same.
6. A trimming circuit, comprising: a control circuit, a compensation circuit and a switching circuit for amplifier offset voltage trimming as claimed in any one of claims 1-5;
the control circuit is electrically connected with the switch circuit, and the control circuit is electrically connected with the compensation circuit; the compensation circuit is electrically connected with the first input end of the amplification module, the second input end of the amplification module and the output end of the amplification module respectively.
7. An amplifier, comprising: the trimming circuit of claim 6.
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| CN202110227217.6A CN112600521B (en) | 2021-03-02 | 2021-03-02 | Switch circuit for adjusting offset voltage of amplifier, adjusting circuit and amplifier |
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| CN202110227217.6A CN112600521B (en) | 2021-03-02 | 2021-03-02 | Switch circuit for adjusting offset voltage of amplifier, adjusting circuit and amplifier |
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| CN112600521B true CN112600521B (en) | 2021-06-04 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102820854A (en) * | 2012-08-08 | 2012-12-12 | 苏州坤元微电子有限公司 | Amplifier and method for improving precision of amplifier |
| CN108599764A (en) * | 2018-04-12 | 2018-09-28 | 中国电子科技集团公司第三十八研究所 | A kind of adjustable comparator imbalance voltage correction circuit of step-length and method |
| CN108634949A (en) * | 2018-05-16 | 2018-10-12 | 西安电子科技大学 | The DC maladjustment of copped wave instrument amplifier calibrates circuit |
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2021
- 2021-03-02 CN CN202110227217.6A patent/CN112600521B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102820854A (en) * | 2012-08-08 | 2012-12-12 | 苏州坤元微电子有限公司 | Amplifier and method for improving precision of amplifier |
| CN108599764A (en) * | 2018-04-12 | 2018-09-28 | 中国电子科技集团公司第三十八研究所 | A kind of adjustable comparator imbalance voltage correction circuit of step-length and method |
| CN108634949A (en) * | 2018-05-16 | 2018-10-12 | 西安电子科技大学 | The DC maladjustment of copped wave instrument amplifier calibrates circuit |
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