CN110958031A

CN110958031A - RS485 receiver circuit, integrated circuit and transceiver

Info

Publication number: CN110958031A
Application number: CN201911364339.9A
Authority: CN
Inventors: 赵海亮; 阮颐; 王鑫森; 常祥岭; 李鹏; 张勇; 李军
Original assignee: Shanghai Beiling Co Ltd
Current assignee: Shanghai Beiling Co Ltd
Priority date: 2019-12-26
Filing date: 2019-12-26
Publication date: 2020-04-03
Anticipated expiration: 2039-12-26
Also published as: CN110958031B

Abstract

The invention discloses an RS485 receiver circuit, an integrated circuit and a transceiver. The receiver circuit includes: the level shift circuit is used for receiving the input of an A line and the input of a B line of the RS485 bus, converting the voltage input by the A line into a first voltage and outputting the first voltage, converting the voltage input by the B line into a second voltage and outputting the second voltage, wherein the first voltage and the second voltage are both in a preset voltage range, and the preset voltage range is not completely the same as the voltage ranges of the input of the A line and the input of the B line; the comparator circuit is used for receiving the first voltage and the second voltage, comparing the voltage difference of the first voltage and the second voltage to obtain a level signal and outputting the level signal; and the output circuit is used for receiving the level signal, generating an output signal with the same high level as the level signal and outputting the output signal. The invention converts the input of the A line and the input of the B line of the RS485 bus into a preset voltage range, and meets the voltage requirements of different ports connected with the output of the RS485 bus.

Description

RS485 receiver circuit, integrated circuit and transceiver

Technical Field

The invention belongs to the field of integrated circuit design, and particularly relates to an RS485 receiver circuit, an integrated circuit and a transceiver.

Background

The RS-485 interface defines the electrical characteristics of the corresponding interface, and can be used in the application fields of networking of an electric meter system and the like. In the receiver circuit of the existing RS485 transceiver, the input voltage range of the A port and the B port is usually +/-13V, and the voltage range limits the output of the receiver circuit, so that the output of the receiver circuit cannot meet the voltage requirement of the subsequent connected port.

Disclosure of Invention

The invention aims to overcome the defect that the output of an RS485 receiver circuit in the prior art cannot meet the voltage requirement of a port connected subsequently because the output of the receiver circuit is limited by the input voltage range of an A port and a B port, and provides an RS485 receiver circuit, an integrated circuit and a transceiver.

The invention solves the technical problems through the following technical scheme:

an RS485 receiver circuit, comprising:

the level shift circuit is used for receiving an A line input and a B line input of the RS485 bus, converting the voltage input by the A line into a first voltage and outputting the first voltage, converting the voltage input by the B line into a second voltage and outputting the second voltage, wherein the first voltage and the second voltage are both within a preset voltage range, and the preset voltage range is not completely the same as the voltage ranges of the A line input and the B line input; and the number of the first and second groups,

the comparator circuit is connected with the level shift circuit and used for receiving the first voltage and the second voltage, comparing the voltage difference between the first voltage and the second voltage to obtain a level signal and outputting the level signal; and the number of the first and second groups,

and the output circuit is connected with the comparator circuit and used for receiving the level signal, generating an output signal with the same high level as the level signal and outputting the output signal.

Preferably, the predetermined voltage range is 0 to 5V or 0 to 3.3V.

Preferably, the level shift circuit includes:

the first end of the first resistor is connected with an A line connecting pin, the second end of the first resistor is connected with the base electrode of the first PNP tube and is connected with a common-mode voltage through the second resistor, and the collector electrode of the first PNP tube is grounded; and the number of the first and second groups,

the common-mode voltage divider comprises a third resistor, a fourth resistor and a second PNP tube, wherein the first end of the third resistor is connected with a B line connecting pin, the second end of the third resistor is connected with the base electrode of the second PNP tube and the common-mode voltage through the fourth resistor, and the collector electrode of the second PNP tube is grounded; and the number of the first and second groups,

the circuit comprises a first phase inverter, a second phase inverter, a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube, wherein the input end of the first phase inverter is connected with a polarity inversion signal, the output end of the first phase inverter is respectively connected with the grid electrode of the first PMOS tube, the input end of the second phase inverter and the grid electrode of the fourth PMOS tube, the drain electrode of the first PMOS tube is connected with the emitter electrode of the first PNP tube, the output end of the second phase inverter is respectively connected with the grid electrode of the second PMOS tube and the grid electrode of the third PMOS tube, the drain electrode of the second PMOS tube is connected with the emitter electrode of the second PNP tube, the drain electrode of the third PMOS tube is connected with the emitter electrode of the first PNP tube, and the drain electrode of the fourth PMOS tube is connected with the emitter electrode of the second PN; and the number of the first and second groups,

the first current source is respectively connected with the source electrode of the first PMOS tube and the source electrode of the second PMOS tube sequentially through the seventh resistor and the fifth resistor, the second current source is respectively connected with the source electrode of the third PMOS tube and the source electrode of the fourth PMOS tube through the sixth resistor, a first node for outputting the first voltage is formed between the first current source and the seventh resistor, and a second node for outputting the second voltage is formed between the second current source and the sixth resistor; and the number of the first and second groups,

the power supply comprises an eighth resistor, a ninth resistor and a first operational amplifier, wherein a first end of the eighth resistor is connected with the power supply, a second end of the eighth resistor is grounded through the ninth resistor and is further connected with a forward input end of the first operational amplifier, an output end of the first operational amplifier is connected with a reverse input end of the first operational amplifier, and an output end of the first operational amplifier outputs the common-mode voltage.

Preferably, the first resistor and the third resistor have the same resistance, the second resistor and the fourth resistor have the same resistance, the fifth resistor and the sixth resistor have the same resistance, the first current source and the second current source have the same output current, the first PNP transistor and the second PNP transistor have the same output current, and the first PMOS transistor, the second PMOS transistor, the third PMOS transistor and the fourth PMOS transistor have the same output current;

and adjusting the voltage values of the first voltage and the second voltage to be within the preset voltage range by adjusting the resistance value ratio of the first resistor and the second resistor.

Preferably, the comparator circuit includes:

a first NPN transistor, a second NPN transistor, a first NMOS transistor, a second NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a third current source, a fourth current source, and a fifth current source, wherein a base of the first NPN transistor is connected to the second voltage, a collector of the first NPN transistor is connected to a power supply through the fourth current source, a base of the second NPN transistor is connected to the first voltage, a collector of the second NPN transistor is connected to the power supply through the fifth current source, an emitter of the first NPN transistor and an emitter of the second NPN transistor are respectively grounded through the third current source, the power supply is further connected to a drain of the fifth PMOS transistor through the fourth current source, a source of the fifth PMOS transistor is respectively connected to a drain of the first NMOS transistor, a gate of the first NMOS transistor, and a gate of the second NMOS transistor, a source of the first NMOS transistor is grounded, and the power supply is further connected to a drain of the sixth PMOS transistor through the fifth current source, the source electrode of the sixth PMOS tube is connected with the drain electrode of the second NMOS tube, the source electrode of the second NMOS tube is grounded, and the grid electrode of the fifth PMOS tube and the grid electrode of the sixth PMOS tube are connected with a third bias voltage; and the number of the first and second groups,

the power supply is also connected with the drain electrode of the third NMOS tube through the eleventh resistor, the source electrode of the third NMOS tube is connected with the drain electrode of the seventh PMOS tube, the source electrode of the seventh PMOS tube is grounded through the tenth resistor, the grid electrode of the third NMOS tube is connected with a first bias voltage, and the grid electrode of the seventh PMOS tube is connected with a second bias voltage; and the number of the first and second groups,

and the input end of the third phase inverter is respectively connected with the source electrode of the third NMOS tube, the drain electrode of the seventh PMOS tube and the source electrode of the sixth PMOS tube, and the output end of the third phase inverter outputs the level signal.

Preferably, the same delay time of the rising edge and the falling edge is obtained by adjusting the relationship between the current passing through the third NMOS transistor and the seventh PMOS transistor and the sixth PMOS transistor and the third NMOS transistor.

Preferably, the output signal is any one of three-state outputs, which are respectively a high-level output, a low-level output and a high-impedance output.

Preferably, the output signal has the capability of driving a load.

An integrated circuit, characterized in that an RS485 receiver circuit as described above is integrated.

An RS485 transceiver, comprising:

the RS485 receiver circuit described above; and the number of the first and second groups,

an RS485 transmitter circuit.

On the basis of the common knowledge in the field, the above preferred conditions can be combined randomly to obtain the preferred embodiments of the invention.

The positive progress effects of the invention are as follows: the invention converts the input of the line A and the input of the line B of the RS485 bus into a preset voltage range, thereby meeting the voltage requirements of different ports connected with the output of the RS485 bus; in addition, the delay time difference between the rising edge and the falling edge of the high-speed RS485 is optimized particularly through the specific design of the comparator circuit, so that the delay time between the rising edge and the falling edge is the same, and meanwhile, the electrical characteristic requirements of national network standards on RS485 interface remote data transmission application standards can be met.

Drawings

Fig. 1 is a schematic block diagram of an RS485 receiver circuit according to embodiment 1 of the present invention;

fig. 2 is a circuit connection diagram of a level shift circuit of an RS485 receiver circuit according to embodiment 1 of the present invention;

fig. 3 is a circuit connection diagram of a comparator circuit of an RS485 receiver circuit according to embodiment 1 of the present invention;

fig. 4 is a schematic block diagram of an RS485 transceiver according to embodiment 3 of the present invention.

Detailed Description

The invention is further illustrated by the following examples, which are not intended to limit the scope of the invention.

Example 1

The present embodiment provides an RS485 receiver circuit, as shown in fig. 1, which includes: a level shift circuit 101, a comparator circuit 102, and an output circuit 103. The level shift circuit 101 is connected to the comparator circuit 102, and the comparator circuit 102 is connected to the output circuit 103. The level shift circuit 101 has two input terminals and two output terminals, the comparator circuit 102 has two input terminals and one output terminal, and the output circuit 103 has one input terminal and one output terminal. Two input ends of the level shift circuit 101 are respectively connected with a line a and a line B of the RS485 bus, two output ends are respectively connected with two input ends of the comparator circuit 102, an output end of the comparator circuit 102 is connected with an input end of the output circuit 103, and an output end of the output circuit 103 is an output end of the RS485 receiver circuit.

Level shift circuit 101 is used for receiving RS485 bus A line input and B line input, converts the voltage A of A line input into first voltage LSA and export, converts the voltage B of B line input into second voltage LSB and export, first voltage LSA with second voltage LSB all in predetermineeing the voltage range just predetermine the voltage range and A line input and the voltage range of B line input not identical. The non-identical means that the preset voltage range may be completely different from or partially identical to the voltage ranges of the a-line input and the B-line input. For example, the voltage range of the A and B line inputs is +/-13V, and the predetermined voltage range may be 0 to 5V or 0 to 3.3V. Of course, the voltage ranges of the line a input and the line B input are not limited to these, and other voltage ranges are also possible.

The comparator circuit 102 is configured to receive the first voltage LSA and the second voltage LSB, compare a voltage difference between the first voltage LSA and the second voltage LSB to obtain a level signal COMP _ OUT, and output the level signal COMP _ OUT.

The output circuit 103 is configured to receive the level signal COMP _ OUT, generate an output signal RO having the same high level as the level signal, and output the output signal RO. The output signal RO is in the same state as the level signal COMP _ OUT, and is at a high level if the level signal COMP _ OUT is at a high level, and is at a low level if the level signal COMP _ OUT is at a low level.

The circuit connection of the level shift circuit 101 is specifically described as follows:

as shown in fig. 2, the level shift circuit 101 includes: the circuit comprises a first resistor R1 to a ninth resistor R9, a first PNP transistor Q1 and a second PNP transistor Q2, a first inverter 1011 and a second inverter 1012, a first PMOS transistor M1 to a fourth PMOS transistor M4, a first current source I1 and a second current source I2 and a first operational amplifier 1013.

Wherein, a first end of the first resistor R1 is connected to an a-line connection pin (the a-line connection pin is used for connecting to an a-line, so as to receive an a-line input), a second end of the first resistor R1 is connected to the base of the first PNP transistor Q1 and to a common mode voltage VCOM through the second resistor R2, and the collector of the first PNP transistor Q1 is grounded;

a first end of the third resistor R3 is connected to a B-line connection pin (the B-line connection pin is connected to a B-line so as to receive a B-line input), a second end of the third resistor R3 is connected to the base of the second PNP transistor Q2 and the common mode voltage VCOM through the fourth resistor R4, and a collector of the second PNP transistor Q2 is grounded;

an input end of the first inverter 1011 is connected to a polarity inversion signal POLA, output ends of the first inverter 1011 are respectively connected to a gate of the first PMOS transistor M1, an input end of the second inverter 1012 and a gate of the fourth PMOS transistor M4, a drain electrode of the first PMOS transistor M1 is connected to an emitter of the first PNP transistor Q1, an output end of the second inverter 1012 is respectively connected to a gate of the second PMOS transistor M2 and a gate of the third PMOS transistor M3, a drain electrode of the second PMOS transistor M2 is connected to an emitter of the second PNP transistor Q2, a drain electrode of the third PMOS transistor M3 is connected to an emitter of the first PNP transistor Q1, and a drain electrode of the fourth PMOS transistor M4 is connected to an emitter of the second PNP transistor Q2;

the first current source I1 is sequentially connected to the source of the first PMOS transistor M1 and the source of the second PMOS transistor M2 through the seventh resistor R7 and the fifth resistor R5, respectively, the second current source I2 is connected to the source of the third PMOS transistor M3 and the source of the fourth PMOS transistor M4 through the sixth resistor R6, a first node outputting the first voltage LSA is formed between the first current source I1 and the seventh resistor R7, and a second node outputting the second voltage LSB is formed between the second current source I2 and the sixth resistor R6;

a first end of the eighth resistor R8 is connected to a power supply VDD, a second end of the eighth resistor R8 is connected to ground through the ninth resistor R9, and is further connected to a positive input terminal of the first operational amplifier 1013, an output terminal of the first operational amplifier 1013 is connected to a negative input terminal of the first operational amplifier 1013, and an output terminal of the first operational amplifier 1013 further outputs the common mode voltage VCOM.

In the above circuit, the first inverter 1011, the second inverter 1012, the first PMOS transistor M1, the second PMOS transistor M2, the third PMOS transistor M3, and the fourth PMOS transistor M4 constitute a polarity inversion circuit. In the RS485 bus lan, if data is not transmitted, the a line is normally high and the B line is low, but due to some special reasons (such as the a/B bus interchanging the a/B bus connection during the networking operation), the a line may be low and the B line may be high. Whether the a line and the B line are at a high level or a low level can be detected by a special polarity detection module, and a corresponding polarity inversion signal POLA is provided to indicate whether polarity inversion is required and to turn on the corresponding circuit. In this embodiment, if the detected signal is high, the line a is high, and the line B is low, the polarity inversion is not required, the polarity inversion signal POLA is low, the second PMOS transistor M2 and the third PMOS transistor M3 are turned on, the first PMOS transistor M1 and the fourth PMOS transistor M4 are turned off, the node a is in phase with the LSA node, and the node B is in phase with the LSB node; if through the detection, the A line is the low level, and the B line is the high level, then needs the polarity upset, polarity upset signal POLA is the high level, this moment second PMOS pipe M2 with third PMOS pipe M3 cuts off, first PMOS pipe M1 with fourth PMOS pipe M4 switches on, and this moment the A node is with LSB node in phase, and the B node is with LSA node in phase. Thereby realizing polarity inversion from the input voltage to the output voltage.

The eighth resistor R8, the ninth resistor R9, and the first operational amplifier 1013 generate the common mode voltage VCOM. Wherein the first operational amplifier 1013 can be implemented by any operational amplifier circuit that satisfies the driving capability requirement and the input/output range. The eighth resistor R8 and the ninth resistor R9 generate a reference voltage for the divided voltage of the power source VDD, the reference voltage is connected to the positive input terminal of the first operational amplifier 1013, and the first operational amplifier 1013 outputs the reference voltage to form a final common mode voltage VCOM. The output end of the first operational amplifier 1013 has a relatively strong current flowing into and out of the output terminal, and generally adopts an a/B output structure, which can provide a large driving capability and realize a small distortion.

The first resistor R1 and the third resistor R3 have the same resistance value, the second resistor R2 and the fourth resistor R4 have the same resistance value, the fifth resistor R5 and the sixth resistor R6 have the same resistance value, the first current source I1 and the second current source I2 have the same output current, the first PNP transistor Q1 and the second PNP transistor Q2 have the same resistance value, and the first PMOS transistor M1, the second PMOS transistor M2, the third PMOS transistor M3 and the fourth PMOS transistor M4 have the same resistance value. The differential output of the level shift circuit 101 is

As can be seen from the above formula, the voltage values of the first voltage LSA and the second voltage LSB are adjusted to be within the preset voltage range by adjusting the resistance ratio of the first resistor R1 and the second resistor R2. The voltage of the first voltage LSA and the second voltage LSB can be controlled within the preset voltage range by setting the resistance ratio of the first resistor R1 and the second resistor R2, and the voltage of all internal nodes except the two nodes a and B is within the preset voltage range (e.g. 0-5V).

Through the seventh resistor R7, the threshold point of the level shift circuit 101 is set to be a negative value, so that the output end of the RS485 receiver circuit is in a high-level state when the input ends A and B of the RS485 receiver circuit are open-circuited, short-circuited and suspended. Considering that the conventional differential input threshold voltage range of the a and B lines is-200 mV to-50 mV for RS485, in this embodiment, after the a/B line input is converted to the preset voltage range, if v (lsa) -v (lsb) > -50mV, the output signal RO outputs high level; if V (LSA) -V (LSB) -200mV, the output signal RO outputs a low level.

The national network standard requires that one RS485 driver host can drive a sufficient number of RS485 slave machines, so that the input impedance of the RS485 slave machines in a data receiving state is required to be in a certain value, and the circuit can meet the requirements of various requirements on different impedances of pins A and B by adjusting the resistance values of the first resistor R1 and the second resistor R2.

The comparator circuit 102 has special requirements on signal delay, and it is necessary that the delay of the rising edge and the delay of the falling edge are the same, so as to keep the duty ratio of the signal unchanged. Particularly, the requirement is high in high-speed RS485 application, in the high-speed RS485 application, the transmission signal period is short, the proportion of the rising edge and the falling edge of the signal in the whole period is large, and if the rising edge delay and the falling edge delay are different, the duty ratio of the signal changes obviously, so that the communication of the signal is influenced. Therefore, in order to make the delay time of the rising edge and the falling edge of the comparator circuit 102 the same, the circuit connection of the comparator circuit 102 is specifically described as follows:

as shown in fig. 3, the comparator circuit 102 includes: the current source circuit comprises a first NPN transistor Q3, a second NPN transistor Q4, a first NMOS transistor M5, a second NMOS transistor M6, a fifth PMOS transistor M7, a sixth PMOS transistor M8, a third current source I3, a fourth current source I4, a fifth current source I5, a tenth resistor R10, an eleventh resistor R11, a third NMOS transistor M9, a seventh PMOS transistor M10 and a third inverter 1021.

The base of the first NPN transistor Q3 is connected to the LSB of the second voltage, the collector of the first NPN transistor Q3 is connected to the VDD through the fourth current source I4, the base of the second NPN transistor Q4 is connected to the LSA of the first voltage, the collector of the second NPN transistor Q4 is connected to the VDD through the fifth current source I5, the emitter of the first NPN transistor Q3 and the emitter of the second NPN transistor Q4 are respectively connected to the ground through the third current source I3, the VDD is further connected to the drain of the fifth PMOS transistor M7 through the fourth current source I4, the source of the fifth PMOS transistor M7 is connected to the drain of the first NMOS transistor M5, the gate of the first NMOS transistor M5 and the gate of the second NMOS transistor M6, the source of the first NMOS transistor M5 is connected to the ground, the power is further connected to the drain of the sixth PMOS transistor M8 through the fifth current source I5, and the source of the sixth NPN transistor M6 is connected to the drain of the sixth PMOS transistor M8, the source electrode of the second NMOS transistor M6 is grounded, and the gate electrodes of the fifth PMOS transistor M7 and the sixth PMOS transistor M8 are connected with a third BIAS BIAS 3; and the number of the first and second groups,

the power supply VDD is further connected to the drain of the third NMOS transistor M9 through the eleventh resistor R11, the source of the third NMOS transistor M9 is connected to the drain of the seventh PMOS transistor M10, the source of the seventh PMOS transistor M10 is grounded through the tenth resistor R10, the gate of the third NMOS transistor M9 is connected to the first BIAS1, and the gate of the seventh PMOS transistor M10 is connected to the second BIAS 2; and the number of the first and second groups,

an input end of the third inverter 1021 is connected to a source of the third NMOS transistor M9, a drain of the seventh PMOS transistor M10, and a source of the sixth PMOS transistor M8, respectively, and an output end of the third inverter 1021 outputs the level signal COMP _ OUT.

In the circuit, the comparator part adopts a folded-cascode structure (other comparator input stage implementation manners can be replaced). The first NPN transistor Q3 and the second NPN transistor Q4 constitute an input differential pair. The network 1022 composed of the third NMOS transistor M9, the seventh PMOS transistor M10, the eleventh resistor R11 and the tenth resistor R10 is used to balance the outputs of the differential stage. Taking the third NMOS transistor M9 as an example, when the differential stage output is one NMOS transistor threshold voltage Vthn lower than the first BIAS1, the third NMOS transistor M9 is turned on. At this time, the power supply VDD supplies an extra current through the eleventh resistor R11, the extra current reduces the rising and falling speed of the node voltage, and the extra current is automatically adjusted according to the node voltage, thereby affecting the delay. The seventh PMOS transistor M10 functions similarly. By adjusting the relationship between the current passing through the third NMOS transistor M9 and the seventh PMOS transistor M10 and the sixth PMOS transistor M8 and the third NMOS transistor M9, the same delay time of the rising edge and the falling edge is obtained.

In the output circuit 103, the output signal RO may be any one of three-state outputs, which are respectively a high-level output, a low-level output, and a high-impedance output. Driven by the output circuit 103, the output signal RO may have the capability of driving a load. The specific structure of the output circuit 103 can be realized by the prior art, and this embodiment is not specifically described.

In the embodiment, the input of the line A and the input of the line B of the RS485 bus are converted into the preset voltage range, so that the voltage requirements of different ports connected with the output of the RS485 bus are met; in addition, in this embodiment, particularly by specifically designing the comparator circuit, the delay difference between the rising edge and the falling edge of the high-speed RS485 is optimized, so that the delay between the rising edge and the falling edge is the same, and the electrical characteristic requirements of the national network standard on the RS485 interface remote data transmission application standard can be met.

Example 2

The present embodiment provides an integrated circuit into which the RS485 receiver circuit in embodiment 1 is integrated.

Example 3

The present embodiment provides an RS485 transceiver, as shown in fig. 4, which includes: an RS485 receiver circuit 10 and an RS485 transmitter 20 circuit. The RS485 receiver circuit 10 can be implemented by using embodiment 1, and the RS485 transmitter circuit 20 can use an existing transmitter circuit, which is not specifically described in this embodiment. The RS485 transceiver may further include a digital control logic 30, a polarity detection module 40, an overvoltage/overcurrent detection module 50, an over-temperature protection module 60, and the like, and these modules may implement common functions in the existing RS485 transceiver, which are not specifically described. A, B is an IO interface for networking communication. RE is an enable signal of the RS485 receiver circuit 10, and RO is an output signal of the RS485 receiver circuit 10 (a data signal of a power grid network is received through pins a and B, and is sent to a front stage MCU through RO after data processing and the like); when RE is at a low level, the RS485 receiver circuit 10 compares A, B the voltage on the line and outputs RO; when RE is high level, the RS485 receiver circuit 10 is turned off; the maximum input voltage range on the a/B line may be +/-13V when the RS485 receiver circuit 10 is in operation. DE is an enable signal of the RS485 transmitter circuit 20, and DI is a data input signal of the RS485 transmitter circuit 20 (receiving a data signal given by a preceding stage MCU or the like, transmitting to a and B pins, and transmitting an output to a grid network). RE and DE control the digital control logic 30 to control the half-duplex mode of operation of the RS485 transceiver.

While specific embodiments of the invention have been described above, it will be appreciated by those skilled in the art that this is by way of example only, and that the scope of the invention is defined by the appended claims. Various changes and modifications to these embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention, and these changes and modifications are within the scope of the invention.

Claims

1. An RS485 receiver circuit, comprising:

2. The RS485 receiver circuit of claim 1, wherein the predetermined voltage range is 0 to 5V or 0 to 3.3V.

3. The RS485 receiver circuit of claim 1 or 2, wherein the level shifting circuit comprises:

4. The RS485 receiver circuit of claim 3, wherein the first resistor and the third resistor have the same resistance, the second resistor and the fourth resistor have the same resistance, the fifth resistor and the sixth resistor have the same resistance, the first current source and the second current source have the same output current, the first PNP transistor and the second PNP transistor have the same output current, and the first PMOS transistor, the second PMOS transistor, the third PMOS transistor and the fourth PMOS transistor have the same output current;

5. The RS485 receiver circuit of claim 1 or 2, wherein the comparator circuit comprises:

6. The RS485 receiver circuit of claim 5, wherein the same delay for a rising edge and a falling edge is obtained by adjusting the relationship between the current through the third NMOS transistor and the seventh PMOS transistor and the sixth PMOS transistor and the third NMOS transistor.

7. The RS485 receiver circuit of claim 1 or 2, wherein the output signal is any one of a tri-state output, a high level output, a low level output and a high impedance output, respectively.

8. The RS485 receiver circuit of claim 7, wherein the output signal has a capability to drive a load.

9. An integrated circuit incorporating an RS485 receiver circuit according to any one of claims 1 to 8.

10. An RS485 transceiver, comprising:

the RS485 receiver circuit of any of claims 1-8; and the number of the first and second groups,

an RS485 transmitter circuit.