CN117674876B - RS-485 receiver circuit - Google Patents
RS-485 receiver circuit Download PDFInfo
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- CN117674876B CN117674876B CN202410116377.7A CN202410116377A CN117674876B CN 117674876 B CN117674876 B CN 117674876B CN 202410116377 A CN202410116377 A CN 202410116377A CN 117674876 B CN117674876 B CN 117674876B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses an RS-485 receiver circuit, which comprises a resistor voltage dividing module, a hysteresis comparator module and a receiver output module, wherein the resistor voltage dividing module is used for receiving an A line input voltage and a B line input voltage of an RS485 bus and generating a first voltage and a second voltage based on the A line input voltage, the B line input voltage and a common mode voltage; the hysteresis comparator module is used for receiving the first voltage and the second voltage and comparing the voltage difference of the first voltage and the second voltage to obtain a level signal; the receiver output module is used for receiving the level signal and the common mode voltage, generating an output signal with the opposite high and low levels of the level signal and outputting the output signal. The receiver circuit accords with the RS-485 standard, and solves the problem that the output signal of the conventional RS-485 receiver is unstable when power is supplied.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to an RS-485 receiver circuit.
Background
As a common interface chip device, the RS-485 transceiver chip has wide application in the fields of intelligent instruments, industrial control, instruments, communication and the like. The RS-485 bus standard specifies that the voltage differential at the receiver input can be as low as + -200 mV at a minimum and can withstand voltage inputs in the range of-7V to + 12V.
Chinese patent application number 201911364339.9 provides an RS485 receiver circuit, an integrated circuit and a transceiver, the receiver circuit comprising: the level shift circuit is used for receiving the input of the A line and the input of the B line of the RS485 bus, converting the voltage input by the A line into a first voltage and outputting the first voltage, converting the voltage input by the B line into a second voltage and outputting the second voltage, wherein the first voltage and the second voltage are both in a preset voltage range, and the preset voltage range is not identical with the voltage ranges of the input of the A line and the input of the B line; and a comparator circuit for receiving the first voltage and the second voltage, comparing the voltage difference between the first voltage and the second voltage to obtain a level signal, and outputting the level signal; and an output circuit for receiving the level signal, generating an output signal opposite to the high-low level of the level signal and outputting the output signal. According to the scheme, the input of the A line and the input of the B line of the RS485 bus are converted into a preset voltage range, and the voltage requirements of different ports connected with the output of the input are met.
However, including the foregoing invention, to reduce the power consumption of the overall transceiver, existing receivers are powered down internally when not in operation; when turned on, the internal circuit powers up, where the internal common mode voltage powers up for a much longer period of time than the comparator. In the period from the power-on stabilization of the comparator to the power-on stabilization of the internal common-mode voltage, the input pair of the comparator is in an unsaturated state, so that the output of the comparator is unstable, and further, the output signal of the receiver is unstable, and the scheme is generated to be improved.
Disclosure of Invention
The invention aims to provide an RS-485 receiver circuit which accords with the RS-485 standard and solves the problem of unstable output signals of a conventional RS-485 receiver during power-on.
In order to achieve the above object, the solution of the present invention is:
the RS-485 receiver circuit comprises a resistor voltage dividing module, a hysteresis comparator module and a receiver output module, wherein the resistor voltage dividing module is used for receiving an A line input voltage and a B line input voltage of an RS485 bus and generating a first voltage and a second voltage based on the A line input voltage, the B line input voltage and a common mode voltage; the hysteresis comparator module is used for receiving the first voltage and the second voltage and comparing the voltage difference of the first voltage and the second voltage to obtain a level signal; the receiver output module is used for receiving the level signal and the common mode voltage and generating an output signal with the opposite high level and low level of the level signal;
The hysteresis comparator module comprises a hysteresis circuit, a rail-to-rail input stage circuit, a gain stage circuit and a wide-range output circuit, wherein the hysteresis circuit is used for generating hysteresis voltage; the rail-to-rail input stage circuit is used for comparing the first voltage with the second voltage and outputting a comparison signal; the gain stage circuit amplifies and gains the comparison signal; the wide-range output circuit is used for expanding the comparison signal of the amplification gain;
The hysteresis circuit comprises a second PMOS tube, a twelfth PMOS tube and a thirteenth PMOS tube, wherein the source electrode of the second PMOS tube is connected with a power supply VCC, the grid electrode of the second PMOS tube is connected with a bias voltage VPBAIS, and the drain electrode of the second PMOS tube is respectively connected with the source electrode of the twelfth PMOS tube and the source electrode of the thirteenth PMOS tube; the grid electrode of the twelfth PMOS tube is connected with the reverse voltage VCMB of the hysteresis voltage VCM, and the drain electrode of the twelfth PMOS tube is connected to the rail-to-rail input stage circuit; the grid electrode of the thirteenth PMOS tube is connected with a hysteresis voltage VCM, and the drain electrode of the thirteenth PMOS tube is connected to the rail-to-rail input stage circuit;
The rail-to-rail input stage circuit comprises a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a seventh resistor, an eighth resistor, a ninth resistor and a tenth resistor, wherein the source electrode of the third PMOS tube is connected with a power supply VCC, the grid electrode of the third PMOS tube is connected with a bias voltage VPBAIS, and the drain electrode of the third PMOS tube is respectively connected with the source electrode of the eighth PMOS tube and the source electrode of the ninth PMOS tube; the drain electrode of the eighth PMOS tube is connected with the drain electrode of the third NMOS tube, and the grid electrode of the eighth PMOS tube is connected with the second voltage; the drain electrode of the ninth PMOS tube is connected with the drain electrode of the fourth NMOS tube, and the grid electrode of the ninth PMOS tube is connected with the first voltage; the grid electrode of the eighth NMOS tube is connected with the second voltage, the drain electrode of the eighth NMOS tube is connected with the drain electrode of the fourth PMOS tube, and the source electrode of the eighth NMOS tube is respectively connected with the source electrode of the ninth NMOS tube and the drain electrode of the second NMOS tube; the grid electrode of the ninth NMOS tube is connected with the first voltage, and the drain electrode of the ninth NMOS tube is connected with the drain electrode of the fifth PMOS tube; the grid electrode of the second NMOS tube is connected with bias voltage VNBAIS, and the source electrode is grounded; the source electrode of the fourth PMOS tube is connected with a power supply VCC, and the grid electrode of the fourth PMOS tube is respectively connected with the grid electrode of the fifth PMOS tube and the drain electrode of the fourth PMOS tube; the source electrode of the fifth PMOS tube is connected with a power supply VCC;
The first end of the seventh resistor is connected with the drain electrode of the fourth PMOS tube, the second end of the seventh resistor is connected with the first end of the eighth resistor, and the second end of the eighth resistor is connected with the drain electrode of the third NMOS tube; the first end of the ninth resistor is connected with the drain electrode of the fifth PMOS tube, the second end of the ninth resistor is connected with the first end of the tenth resistor, and the second end of the tenth resistor is connected with the drain electrode of the fourth NMOS tube;
the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube and is commonly connected with bias voltage VNBAIS; the source electrode of the third NMOS tube and the source electrode of the fourth NMOS tube are grounded;
the second end of the seventh resistor and the second end of the ninth resistor are used for outputting comparison signals to the gain stage circuit;
The gain stage circuit comprises a sixth PMOS tube, a seventh PMOS tube, a tenth NMOS tube, an eleventh NMOS tube and a fifth NMOS tube, wherein the source electrode of the sixth PMOS tube is connected with a power supply VCC, and the grid electrode and the drain electrode are connected to the drain electrode of the tenth NMOS tube after being in short circuit; the source electrode of the seventh PMOS tube is connected with a power supply VCC, and the grid electrode and the drain electrode are connected to the drain electrode of the eleventh NMOS tube after being short-circuited; the source electrode of the tenth NMOS tube is connected with the source electrode of the eleventh NMOS tube and then is commonly connected to the drain electrode of the fifth NMOS tube, and the grid electrode of the tenth NMOS tube and the grid electrode of the eleventh NMOS tube are used for accessing a comparison signal output by the rail-to-rail input stage; the grid electrode of the fifth NMOS tube is connected with bias voltage VNBAIS, and the source electrode is grounded; the drain electrode of the sixth PMOS tube and the drain electrode of the seventh PMOS tube are used for outputting comparison signals after amplification gain;
The wide-range output circuit comprises a tenth PMOS tube, an eleventh PMOS tube, a sixth NMOS tube, a seventh NMOS tube, a first inverter and a second inverter, wherein the grid electrode of the tenth PMOS tube and the grid electrode of the eleventh PMOS tube are connected with the comparison signal after amplifying the gain output by the gain stage circuit; the source electrode of the tenth PMOS tube and the source electrode of the eleventh PMOS tube are both connected with a power supply VCC, the drain electrode of the tenth PMOS tube is respectively connected with the drain electrode of the sixth NMOS tube, the grid electrode of the sixth NMOS tube and the grid electrode of the seventh NMOS tube, and the drain electrode of the eleventh PMOS tube is respectively connected with the drain electrode of the seventh NMOS tube and the input end of the first inverter; the source electrode of the sixth NMOS tube and the source electrode of the seventh NMOS tube are grounded;
The output end of the first inverter is connected with the input end of the second inverter, and the output end of the second inverter is used for outputting a level signal VCM;
The receiver output module comprises a first comparator, a second comparator, a first AND gate, a second AND gate, a third inverter, a first NOT gate, a second NOT gate, a first resistor, a second resistor, a first PMOS tube and a first NMOS tube, wherein the positive input end of the first comparator is connected with a power supply, the negative input end of the second comparator is grounded, the negative input end of the first comparator and the positive input end of the second comparator are both connected with common-mode voltage, the output end of the first comparator and the output end of the second comparator are respectively connected with the two input ends of the third AND gate, and the output end of the third AND gate is respectively connected with the input end of the third inverter and the first input end of the second AND gate; the two input ends of the first AND gate are respectively connected with the level signal of the hysteresis comparator module and the output end of the second NOT gate, the output end of the first AND gate is connected with the second input end of the second AND gate, and the output end of the second AND gate is respectively connected with the second input end of the first NOT gate and the grid electrode of the first NMOS tube; the first input end of the first NOT gate is connected with the level signal of the hysteresis comparator module, the output end of the first NOT gate is connected with the first input end of the second NOT gate, and the second input end of the second NOT gate is connected with the output end of the third inverter; the output end of the second NOT gate is connected with the grid electrode of the first PMOS tube, the source electrode of the first PMOS tube is connected with the power supply, the drain electrode of the first PMOS tube is connected with one end of the first resistor, the other end of the first resistor is connected with one end of the second resistor, and the end is used for outputting signals of the receiver circuit; the other end of the second resistor is connected with the drain electrode of the first NMOS tube, and the source electrode of the first NMOS tube is grounded.
The resistor voltage dividing module comprises third-sixth resistors and a current source, wherein one end of the third resistor is connected with the input voltage of the A line, the other end of the third resistor is used for outputting first voltage, and the other end of the third resistor is also connected with one end of the fourth resistor; the other end of the fourth resistor is connected with one end of a fifth resistor, the other end of the fifth resistor is connected with the positive electrode of a current source, and the negative electrode of the current source is grounded; one end of the sixth resistor is connected with the input voltage of the B line, the other end of the sixth resistor is used for outputting a second voltage, and the other end of the sixth resistor is also connected with the positive electrode of the current source;
The resistor voltage division module further comprises an operational amplifier, wherein the positive input end of the operational amplifier is connected to a reference voltage VREF, and the reference voltage VREF can be adjusted manually; the negative input end of the operational amplifier is connected to the output end of the operational amplifier, the output end of the operational amplifier is connected between the fourth resistor and the fifth resistor, and the output end of the operational amplifier is used for outputting the common-mode voltage VCM.
The resistance of the fourth resistor is the same as that of the fifth resistor, and the resistance of the third resistor is the same as that of the sixth resistor.
The resistor voltage dividing module generates a first voltage and a second voltage based on an A line input voltage, a B line input voltage and a common mode voltage, and the resistor voltage dividing module comprises the following steps of:
，
wherein, the input voltage of the A line and the input voltage of the B line are common-mode voltage respectively; the ratio is the ratio of the third resistance to the fourth resistance.
After the scheme is adopted, the invention has the following beneficial effects:
(1) The invention converts high voltage input by the RS-485 bus into low voltage through the resistor voltage dividing module, compares the low voltage with the high voltage through the hysteresis comparator circuit, and ensures stable and accurate signal output through enabling control logic, thereby conforming to the electrical characteristics of the RS-485 standard;
(2) The receiver output module adopted by the invention can keep the function of outputting a high resistance state by the receiver when the common mode voltage is not in the range from the power supply voltage to the ground.
Drawings
FIG. 1 is a block diagram of the present invention;
FIG. 2 is a circuit diagram of a resistor divider module according to the present invention;
FIG. 3 is a circuit diagram of a hysteresis comparator module of the present invention;
fig. 4 is a circuit diagram of a receiver output module in accordance with the present invention.
Detailed Description
The technical scheme and beneficial effects of the present invention will be described in detail below with reference to the accompanying drawings.
As shown in fig. 1, the invention provides an RS-485 receiver circuit, which comprises a resistor voltage dividing module, a hysteresis comparator module and a receiver output module, wherein the resistor voltage dividing module is used for receiving an a-line input and a B-line input of an RS485 bus, generating a first voltage and a second voltage based on a voltage input by the a-line, a voltage input by the B-line and a common mode voltage, and outputting the first voltage and the second voltage; the hysteresis comparator module is used for receiving the first voltage and the second voltage, comparing the voltage difference of the first voltage and the second voltage to obtain a level signal and outputting the level signal; the receiver output module is used for receiving the level signal output by the hysteresis comparator module and the common-mode voltage output by the resistor voltage dividing module, generating and outputting an output signal with the opposite high level and low level of the level signal.
The RS-485 receiver circuit typically has a supply voltage of 5V, but the bus input voltage exceeds the supply voltage, so the input signal needs to be first reduced, as shown in fig. 2, which is a resistor divider module, where the resistor r4=r5, r3=r6 in fig. 2. The resistor divider module has two functions, the first function is to reduce the large signal exceeding the input of the receiver bus, the reduction ratio requires the voltage on the line A and the line B to be reduced from-7V to +12V, the voltage is reduced to 3.3V or 5V, so that the hysteresis comparator circuit can process the voltage, and the typical reduction ratio is 10:1, the internal voltage amplitude is reduced; the second is to bias the bus voltage to a fixed common mode voltage, which can ensure the normal operation of the subsequent hysteresis comparator module. The fixed common mode voltage is generated by a unity gain op amp and a reference voltage and a current source connected between the B line input and ground will generate a voltage drop across R4 and R6 connected to the negative input of the hysteresis comparator block. In the case of a bus idle or bus short (e.g., a differential voltage of 0V between the a and B lines), the bias voltage may cause the first voltage at the negative input to be lower than the second voltage at the positive input, ensuring that the output of the RS-485 receiver is high.
In the present embodiment, assuming that the a-line input voltage VA is greater than the B-line input voltage VB, there are:
，
Wherein VC is the common mode voltage output by the resistor voltage dividing module; k is the resistance reduction ratio, and the ratio is the resistance R3/the resistance R4.
The differential voltage (|VA-VB|) reduced by the resistor voltage division module outputs a comparison result through a hysteresis comparator module. The differential voltage is reduced by the resistor voltage dividing module, so that the hysteresis comparator module is required to have higher gain and ensure stable output, and particularly as shown in the hysteresis comparator module of fig. 3, the first part is a hysteresis circuit, the current magnitude of the current mirror tubes PM2 and PM3 can be adjusted by setting the magnitude of the gate bias voltage VPBAIS of the current mirror tube, a fixed hysteresis voltage can be generated on the output voltage VCM of the hysteresis comparator module by setting the proportion of PM2 and PM3, and PM12 and PM13 are controlled by the output signal VCM and a signal VCMB opposite to the output signal VCM; the second part is a rail-to-rail input stage circuit which is used for comparing the first voltage with the second voltage and outputting a comparison signal, when the first voltage or the second voltage is close to the GND voltage, the NMOS input pair transistor does not work, and the PMOS input pair transistor works independently; when the input voltage is close to the power supply voltage, the NMOS input pair transistors work independently, and the PMOS input pair transistors do not work; the remaining states both input pair tubes are working. Because the operational amplifier with unit gain of the resistor voltage division module has longer stabilizing time, a rail-to-rail input stage circuit is adopted, when the input signal of the hysteresis comparator module is in the range of power supply voltage to ground, at least one pair of PM8 and PM9 input pair transistors and NM8 and NM9 input pair transistors are in a stable saturation region, stable output is ensured, PM2, PM3, PM4, PM5, NM2, NM3 and NM4 are current mirror tubes, current is provided for a branch circuit, and R7 to R10 are input stage load resistors; the third part is a gain stage circuit, PM6 and PM7 are connected into diodes to serve as loads of NM10 and NM11 input tubes, a larger gain is provided, and NM5 is a current mirror tube to provide current; the fourth part is a wide-range output circuit, expands the signal range output by the gain stage circuit, NM6 and NM7 are equal-proportion current mirror tubes, and form wide-range output together with bias tubes PM10 and PM11, and the expanded signal range is from the ground voltage to the power supply voltage.
When the receiver is powered on, a certain time is required for the common mode voltage VCOM output by the unit gain operational amplifier in the resistor voltage dividing module to reach stability, and the hysteresis comparator module can be powered on rapidly, at this time, the input stage of the comparator may not be in a working area, and the output of the receiver is unstable, so a circuit for detecting VCOM is added, specifically, as shown in the receiver output module in FIG. 4, VCOM is the common mode voltage of the resistor voltage dividing module, and VCOM is compared with the power supply VDD through the CM1 comparator and the CM2 comparator. When VCOM is not in the range from the power supply voltage to the ground, AND3 outputs a low level, AND2 keeps the low level output, NM1 is turned off; after the low level output by the AND3 is inverted by the INV3, the OR2 is kept to be high level output, the PM1 is turned off, the receiver outputs a high resistance state, the VCM signal is a comparator output signal, the OR1 AND the AND1 output non-overlapping signals, only one output pipe PM1 AND NM1 is turned on at the same moment, AND the power consumption of the circuit is reduced. The resistors R1 and R2 limit the branch current to play a protective role.
It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. The scheme in the embodiment of the invention can be realized by adopting various computer languages, such as object-oriented programming language Java, an transliteration script language JavaScript and the like.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (3)
1. An RS-485 receiver circuit, characterized by: the circuit comprises a resistor voltage dividing module, a hysteresis comparator module and a receiver output module, wherein the resistor voltage dividing module is used for receiving an RS485 bus A line input voltage and a B line input voltage and generating a first voltage and a second voltage based on the A line input voltage, the B line input voltage and a common mode voltage; the hysteresis comparator module is used for receiving the first voltage and the second voltage and comparing the voltage difference of the first voltage and the second voltage to obtain a level signal; the receiver output module is used for receiving the level signal and the common mode voltage and generating an output signal with the opposite high level and low level of the level signal;
The hysteresis comparator module comprises a hysteresis circuit, a rail-to-rail input stage circuit, a gain stage circuit and a wide-range output circuit, wherein the hysteresis circuit is used for generating hysteresis voltage; the rail-to-rail input stage circuit is used for comparing the first voltage with the second voltage and outputting a comparison signal; the gain stage circuit amplifies and gains the comparison signal; the wide-range output circuit is used for expanding the comparison signal of the amplification gain;
The hysteresis circuit comprises a second PMOS tube, a twelfth PMOS tube and a thirteenth PMOS tube, wherein the source electrode of the second PMOS tube is connected with a power supply VCC, the grid electrode of the second PMOS tube is connected with a bias voltage VPBAIS, and the drain electrode of the second PMOS tube is respectively connected with the source electrode of the twelfth PMOS tube and the source electrode of the thirteenth PMOS tube; the grid electrode of the twelfth PMOS tube is connected with the reverse voltage VCMB of the hysteresis voltage VCM, and the drain electrode of the twelfth PMOS tube is connected to the rail-to-rail input stage circuit; the grid electrode of the thirteenth PMOS tube is connected with a hysteresis voltage VCM, and the drain electrode of the thirteenth PMOS tube is connected to the rail-to-rail input stage circuit;
The rail-to-rail input stage circuit comprises a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a seventh resistor, an eighth resistor, a ninth resistor and a tenth resistor, wherein the source electrode of the third PMOS tube is connected with a power supply VCC, the grid electrode of the third PMOS tube is connected with a bias voltage VPBAIS, and the drain electrode of the third PMOS tube is respectively connected with the source electrode of the eighth PMOS tube and the source electrode of the ninth PMOS tube; the drain electrode of the eighth PMOS tube is connected with the drain electrode of the third NMOS tube, and the grid electrode of the eighth PMOS tube is connected with the second voltage; the drain electrode of the ninth PMOS tube is connected with the drain electrode of the fourth NMOS tube, and the grid electrode of the ninth PMOS tube is connected with the first voltage; the grid electrode of the eighth NMOS tube is connected with the second voltage, the drain electrode of the eighth NMOS tube is connected with the drain electrode of the fourth PMOS tube, and the source electrode of the eighth NMOS tube is respectively connected with the source electrode of the ninth NMOS tube and the drain electrode of the second NMOS tube; the grid electrode of the ninth NMOS tube is connected with the first voltage, and the drain electrode of the ninth NMOS tube is connected with the drain electrode of the fifth PMOS tube; the grid electrode of the second NMOS tube is connected with bias voltage VNBAIS, and the source electrode is grounded; the source electrode of the fourth PMOS tube is connected with a power supply VCC, and the grid electrode of the fourth PMOS tube is respectively connected with the grid electrode of the fifth PMOS tube and the drain electrode of the fourth PMOS tube; the source electrode of the fifth PMOS tube is connected with a power supply VCC;
The first end of the seventh resistor is connected with the drain electrode of the fourth PMOS tube, the second end of the seventh resistor is connected with the first end of the eighth resistor, and the second end of the eighth resistor is connected with the drain electrode of the third NMOS tube; the first end of the ninth resistor is connected with the drain electrode of the fifth PMOS tube, the second end of the ninth resistor is connected with the first end of the tenth resistor, and the second end of the tenth resistor is connected with the drain electrode of the fourth NMOS tube;
the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube and is commonly connected with bias voltage VNBAIS; the source electrode of the third NMOS tube and the source electrode of the fourth NMOS tube are grounded;
the second end of the seventh resistor and the second end of the ninth resistor are used for outputting comparison signals to the gain stage circuit;
The gain stage circuit comprises a sixth PMOS tube, a seventh PMOS tube, a tenth NMOS tube, an eleventh NMOS tube and a fifth NMOS tube, wherein the source electrode of the sixth PMOS tube is connected with a power supply VCC, and the grid electrode and the drain electrode are connected to the drain electrode of the tenth NMOS tube after being in short circuit; the source electrode of the seventh PMOS tube is connected with a power supply VCC, and the grid electrode and the drain electrode are connected to the drain electrode of the eleventh NMOS tube after being short-circuited; the source electrode of the tenth NMOS tube is connected with the source electrode of the eleventh NMOS tube and then is commonly connected to the drain electrode of the fifth NMOS tube, and the grid electrode of the tenth NMOS tube and the grid electrode of the eleventh NMOS tube are used for accessing a comparison signal output by the rail-to-rail input stage; the grid electrode of the fifth NMOS tube is connected with bias voltage VNBAIS, and the source electrode is grounded; the drain electrode of the sixth PMOS tube and the drain electrode of the seventh PMOS tube are used for outputting comparison signals after amplification gain;
The wide-range output circuit comprises a tenth PMOS tube, an eleventh PMOS tube, a sixth NMOS tube, a seventh NMOS tube, a first inverter and a second inverter, wherein the grid electrode of the tenth PMOS tube and the grid electrode of the eleventh PMOS tube are connected with the comparison signal after amplifying the gain output by the gain stage circuit; the source electrode of the tenth PMOS tube and the source electrode of the eleventh PMOS tube are both connected with a power supply VCC, the drain electrode of the tenth PMOS tube is respectively connected with the drain electrode of the sixth NMOS tube, the grid electrode of the sixth NMOS tube and the grid electrode of the seventh NMOS tube, and the drain electrode of the eleventh PMOS tube is respectively connected with the drain electrode of the seventh NMOS tube and the input end of the first inverter; the source electrode of the sixth NMOS tube and the source electrode of the seventh NMOS tube are grounded;
The output end of the first inverter is connected with the input end of the second inverter, and the output end of the second inverter is used for outputting a level signal VCM;
The receiver output module comprises a first comparator, a second comparator, a first AND gate, a second AND gate, a third inverter, a first NOT gate, a second NOT gate, a first resistor, a second resistor, a first PMOS tube and a first NMOS tube, wherein the positive input end of the first comparator is connected with a power supply, the negative input end of the second comparator is grounded, the negative input end of the first comparator and the positive input end of the second comparator are both connected with common-mode voltage, the output end of the first comparator and the output end of the second comparator are respectively connected with the two input ends of the third AND gate, and the output end of the third AND gate is respectively connected with the input end of the third inverter and the first input end of the second AND gate; the two input ends of the first AND gate are respectively connected with the level signal of the hysteresis comparator module and the output end of the second NOT gate, the output end of the first AND gate is connected with the second input end of the second AND gate, and the output end of the second AND gate is respectively connected with the second input end of the first NOT gate and the grid electrode of the first NMOS tube; the first input end of the first NOT gate is connected with the level signal of the hysteresis comparator module, the output end of the first NOT gate is connected with the first input end of the second NOT gate, and the second input end of the second NOT gate is connected with the output end of the third inverter; the output end of the second NOT gate is connected with the grid electrode of the first PMOS tube, the source electrode of the first PMOS tube is connected with the power supply, the drain electrode of the first PMOS tube is connected with one end of the first resistor, the other end of the first resistor is connected with one end of the second resistor, and the end is used for outputting signals of the receiver circuit; the other end of the second resistor is connected with the drain electrode of the first NMOS tube, and the source electrode of the first NMOS tube is grounded;
The resistor voltage dividing module comprises third-sixth resistors and a current source, wherein one end of the third resistor is connected with the input voltage of the A line, the other end of the third resistor is used for outputting first voltage, and the other end of the third resistor is also connected with one end of the fourth resistor; the other end of the fourth resistor is connected with one end of a fifth resistor, the other end of the fifth resistor is connected with the positive electrode of a current source, and the negative electrode of the current source is grounded; one end of the sixth resistor is connected with the input voltage of the B line, the other end of the sixth resistor is used for outputting a second voltage, and the other end of the sixth resistor is also connected with the positive electrode of the current source;
The resistor voltage division module further comprises an operational amplifier, wherein the positive input end of the operational amplifier is connected to a reference voltage VREF, and the reference voltage VREF can be adjusted manually; the negative input end of the operational amplifier is connected to the output end of the operational amplifier, the output end of the operational amplifier is connected between the fourth resistor and the fifth resistor, and the output end of the operational amplifier is used for outputting the common-mode voltage VCM.
2. The RS-485 receiver circuit according to claim 1, characterized in that: the resistance of the fourth resistor is the same as that of the fifth resistor, and the resistance of the third resistor is the same as that of the sixth resistor.
3. The RS-485 receiver circuit according to claim 1, characterized in that: the resistor voltage dividing module generates a first voltage and a second voltage based on the A line input voltage, the B line input voltage and the common mode voltage, and the resistor voltage dividing module comprises the following steps of:
，
wherein VA, VB are input voltage of the A line and input voltage of the B line respectively, and VC is common mode voltage; k is the resistance reduction ratio, which is the ratio of the third resistance to the fourth resistance.
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| CN202410116377.7A CN117674876B (en) | 2024-01-29 | 2024-01-29 | RS-485 receiver circuit |
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| CN202410116377.7A CN117674876B (en) | 2024-01-29 | 2024-01-29 | RS-485 receiver circuit |
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| CN117674876B true CN117674876B (en) | 2024-04-26 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105680835A (en) * | 2016-03-14 | 2016-06-15 | 湘潭芯力特电子科技有限公司 | Hysteresis comparator applied to RS-485 receiving end |
| CN110958031A (en) * | 2019-12-26 | 2020-04-03 | 上海贝岭股份有限公司 | RS485 receiver circuit, integrated circuit and transceiver |
| CN112671359A (en) * | 2020-12-24 | 2021-04-16 | 上海贝岭股份有限公司 | Comparator circuit and RS485 receiver circuit |
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- 2024-01-29 CN CN202410116377.7A patent/CN117674876B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105680835A (en) * | 2016-03-14 | 2016-06-15 | 湘潭芯力特电子科技有限公司 | Hysteresis comparator applied to RS-485 receiving end |
| CN110958031A (en) * | 2019-12-26 | 2020-04-03 | 上海贝岭股份有限公司 | RS485 receiver circuit, integrated circuit and transceiver |
| CN112671359A (en) * | 2020-12-24 | 2021-04-16 | 上海贝岭股份有限公司 | Comparator circuit and RS485 receiver circuit |
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