CN104579185A - High-precision muting control circuit - Google Patents
High-precision muting control circuit Download PDFInfo
- Publication number
- CN104579185A CN104579185A CN201410828572.9A CN201410828572A CN104579185A CN 104579185 A CN104579185 A CN 104579185A CN 201410828572 A CN201410828572 A CN 201410828572A CN 104579185 A CN104579185 A CN 104579185A
- Authority
- CN
- China
- Prior art keywords
- transistor
- drain electrode
- signal
- grid
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Amplifiers (AREA)
Abstract
The invention provides a high-precision muting control circuit which comprises a pre-amplifier, a latch comparator and a pulse filter, wherein the pre-amplifier is used for respectively amplifying an input signal and a reference signal; the latch comparator is used for comparing the amplified input signal with the amplified reference signal; the pulse filter is used for outputting an enable signal when the amplified input signal is bigger than the amplified reference signal and outputting a non-enable signal when the amplified input signal is smaller than the amplified reference signal and lasts longer than the preset time duration. An automatic trimming unit is arranged in the pre-amplifier and is used for tracking the turnover level of the latch comparator and adjusting a first bias current and a second bias current on the basis of the turnover signal, so that the influence on the performance of a muting controller caused by the bias of the common mode level outputted by the pre-amplifier and the turnover level of the latch comparator resulted from the change in power voltage, input signal, bias current, technique and/or working temperature is avoided.
Description
[technical field]
The present invention relates to circuit design field, particularly a kind of high accuracy mute control circuit.
[background technology]
Squelch control device (Squelch) is functional module the most frequently used in communication interface circuit, lower than the range value of setting and the background noise of time duration of setting on its filtered signal line.When the amplitude of input signal is higher than set point (hereinafter referred to as threshold value), squelch control device sends enable signal, opens the corresponding functional module of receiving circuit, receives effective signal of communication.Otherwise, when receiving circuit is in the work of reception, if the amplitude of input signal is lower than setting threshold and when being continued above the time span of setting, squelch control device sends not enable signal, to close corresponding functional module, to shield the noise response on holding wire.
Very important design objective when low-power consumption, high reaction speed and high threshold decision accuracy are design mute control circuits.The precision of threshold determination is usually the error range of tens millivolts, and the reaction time is usually at nanosecond order.For USB2.0 high speed receiving mode, the error range of threshold value is 50mv, and the enable opening time of squelch control device is set in below 10ns usually, and guarantee first high-speed digital signal is accurately received.
In the prior art, described squelch control device generally includes preamplifier, latched comparator and pulsed filter.Current preamplifier and latched comparator are all relatively independent, and the relevant parameter that can arrange preamplifier and latched comparator according to the performance index of described squelch control device when designing is with can collaborative work efficiently both ensureing.But, there is deviation between the common mode electrical level that the change of supply voltage, input signal, bias current, technique and/or working temperature can cause preamplifier to export and the trigging signal of latched comparator, and this deviation can cause adverse effect to squelch control device performance.
Therefore, be necessary to provide a kind of technical scheme of improvement to overcome the problems referred to above.
[summary of the invention]
The object of the present invention is to provide a kind of high accuracy mute control circuit, the adverse effect that its change that can reduce supply voltage, input signal, bias current, technique and/or working temperature brings to the performance of mute control circuit.
In order to solve the problem, according to an aspect of the present invention, the invention provides a kind of mute control circuit, it comprises: preamplifier, for difference amplification input signal and reference signal; Latched comparator, for the reference signal of the input signal and amplification that compare amplification; Pulsed filter, when the input signal of described amplification is greater than the reference signal of described amplification, output enable signal, when the input signal of described amplification is less than the reference signal of described amplification and is continued above predetermined duration, exports disable signal.Described preamplifier comprises the first pre-amplifier unit, the second pre-amplifier unit and automatically trims unit, described first pre-amplifier unit provides the first bias current, and amplify described input signal based on the first bias current, described second pre-amplifier unit provides the second bias current, and amplify described reference signal based on the second bias current, the described trigging signal automatically trimming latched comparator described in element keeps track, and adjust the first bias current and the second bias current based on this trigging signal.
Further, described first pre-amplifier unit, comprise transistor PM5, PM1, PM2, PM7, resistance R1, R2, wherein the source electrode of transistor PM5 is connected with the first supply voltage, the drain electrode of transistor PM5 is connected with the source electrode of transistor PM2 with the source electrode of transistor PM1, and the grid of transistor PM5 is connected with bias voltage; The source electrode of transistor PM7 is connected with the first supply voltage, the drain electrode of transistor PM7 is connected with the drain electrode of transistor PM5, transistor PM7 and PM5 provides the first bias current, the drain electrode of transistor PM1 is by resistance R1 ground connection, described input signal comprises the first input differential signal and the second input differential signal, the grid of transistor PM1 receives the first input differential signal, the drain electrode of transistor PM2 is by resistance R2 ground connection, the grid of transistor PM2 receives the second input differential signal, and the drain electrode of transistor PM1 and/or the drain electrode of transistor PM2 export the input signal amplified.Described second pre-amplifier unit, comprise transistor PM6, PM3, PM4, PM8, resistance R3, R4, wherein the source electrode of transistor PM6 is connected with the first supply voltage, the drain electrode of transistor PM6 is connected with the source electrode of transistor PM4 with the source electrode of transistor PM3, and the grid of transistor PM6 is connected with bias voltage; The source electrode of transistor PM8 is connected with the first supply voltage, and the drain electrode of transistor PM8 is connected with the drain electrode of transistor PM6, and transistor PM6 and PM8 provides the first bias current, and the drain electrode of transistor PM3 is by resistance R3 ground connection.Described reference signal comprises the first reference differential and the second reference differential, the grid of transistor PM3 receives the first reference differential, the drain electrode of transistor PM4 is by resistance R4 ground connection, the grid of transistor PM4 receives the second reference differential, and the drain electrode of transistor PM3 and/or the drain electrode of transistor PM4 export the reference signal of amplifying.Describedly automatically trim unit, comprise trigging signal testing circuit, operational amplifier, resistance R5 and R6, described trigging signal testing circuit is for detecting the trigging signal of described latched comparator, and this trigging signal is supplied to the first input end of operational amplifier, the drain electrode of transistor PM3 is connected to the second input of operational amplifier by resistance R5, the drain electrode of transistor PM4 is connected to the second input of operational amplifier by resistance R6, the output of operational amplifier is connected to the grid of transistor PM7 and PM8, the described unit that automatically trims adjusts the first bias current and the second bias current by the grid voltage of adjustment transistor PM7 and PM8, until the voltage of the first input end of operational amplifier equals the voltage of the second input.
Further, described latched comparator comprises one or more latch comparing unit, and each latch comparing unit comprises transistor PM11, PM12, PM13, NM11, NM12, NM13, inverter INV1.The source electrode of transistor PM11 is connected with second source voltage, and its drain electrode is connected with the source electrode of transistor PM12 and the source electrode of transistor PM13, and its grid is connected with the grid of transistor NM13.The source ground of transistor NM13, its drain electrode is connected with the source electrode of transistor NM11 and the source electrode of transistor NM12.The drain electrode of transistor PM12 is connected with the drain electrode of transistor NM11, its grid is connected with the grid of transistor NM11, the drain electrode of transistor PM13 is connected with the drain electrode of transistor NM12, and its grid is connected with the grid of transistor NM12, and the drain electrode of transistor PM12 is connected with the grid of transistor PM11.The drain electrode of transistor PM13 is connected with the input of inverter INV1, and the output of inverter INV1 is the output of this latch comparing unit.The grid of transistor PM12 is as the first input end latching comparing unit, and this first input end is connected to the drain electrode of the transistor PM3 in the second pre-amplifier unit or the drain electrode of transistor PM4.The grid of transistor PM13 is as the second input latching comparing unit, and this second input is connected to the drain electrode of the transistor PM1 in the first pre-amplifier unit or the drain electrode of transistor PM2.
Further, described trigging signal testing circuit comprises transistor PM21, PM22, NM21, NM22.The source electrode of transistor PM21 connects second source voltage, and its grid is connected with the grid of transistor NM21, and its drain electrode is connected with the source electrode of transistor PM22.The drain electrode of transistor PM22 is connected with the drain electrode of transistor NM22, and the grid of transistor PM22 is connected with the grid of transistor NM22, and the source electrode of transistor NM22 is connected to the drain electrode of transistor NM21, the source ground of transistor NM21.The grid of transistor PM22 is connected with the drain electrode of transistor PM22, and the drain electrode of transistor PM22 is connected with the grid of transistor PM21, and the voltage of the grid of transistor PM22 is exactly the trigging signal of the described latched comparator detected.
Further, described latched comparator comprises the first latch comparing unit, the second latch comparing unit and or door.First first input end latching comparing unit is connected to the drain electrode of the transistor PM4 in the second pre-amplifier unit, and the second first input end latching comparing unit is connected to the drain electrode of the transistor PM4 in the second pre-amplifier unit.First the second input latching comparing unit is connected to the drain electrode of the transistor PM1 in the first pre-amplifier unit, and the second the second input latching comparing unit is connected to the drain electrode of the transistor PM2 in the first pre-amplifier unit.The output of the first inverter INV1 latched in comparing unit is connected to or an input of door, and the output of the second inverter INV1 latched in comparing unit is connected to or another input of door.Output that is described or door exports the compare result signal of the reference signal of input signal and the amplification of amplifying.
Further, the size of the transistor PM11 in each latch units and the ratio of the size of the described transistor PM21 automatically trimmed in unit, equal the size sum of transistor PM12 and PM13 in each latch units and the ratio of the size of the described transistor PM22 automatically trimmed in unit, also the size of the transistor NM13 in each latch units and the ratio of the size of the described transistor NM21 automatically trimmed in unit is equaled, also equal the size sum of transistor NM11 and NM12 in each latch units and the ratio of the size of the described transistor NM22 automatically trimmed in unit.
Compared with prior art, be provided with in preamplifier in the present invention and automatically trim unit, this trims the trigging signal of element keeps track latched comparator automatically, and adjust the first bias current and the second bias current based on this trigging signal, this avoid the deviation of the change of supply voltage, input signal, bias current, technique and/or working temperature and the trigging signal of common mode electrical level that the preamplifier that causes exports and latched comparator to the impact of squelch control device performance.
[accompanying drawing explanation]
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, below the accompanying drawing used required in describing embodiment is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.Wherein:
Fig. 1 is the high accuracy mute control circuit structural representation in one embodiment in the present invention;
Fig. 2 is the preamplifier circuit diagram in one embodiment in Fig. 1;
Fig. 3 is the latch comparing unit circuit diagram in one embodiment in the latched comparator in Fig. 1;
Fig. 4 is the latched comparator structured flowchart in one embodiment in Fig. 1.
[embodiment]
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
The invention provides a kind of high accuracy mute control circuit, the adverse effect that its change that can reduce supply voltage, input signal, bias current, technique and/or working temperature brings to the performance of mute control circuit.
As shown in Figure 1, it is in order to the high accuracy mute control circuit structural representation in one embodiment in the present invention, and described mute control circuit 100 comprises preamplifier 110, latched comparator 120, pulsed filter 130.
The input signal Vin_a that described preamplifier 110 is amplified for amplification input signal Vin, amplifies the reference signal Vref_a that reference signal Vref is amplified.Described latched comparator 120 for the reference signal Vref_a of the input signal Vin_a and amplification that compare amplification, and exports comparative result Vc.Described pulsed filter 130, when the input signal of described amplification is greater than the reference signal of described amplification, output enable signal S, now enable receiving circuit is started working, when the input signal of described amplification is less than the reference signal of described amplification and is continued above predetermined duration, export disable signal, now make receiving circuit quit work.
As shown in Figure 2, described preamplifier 110 comprises the first pre-amplifier unit 112, second pre-amplifier unit 112 and automatically trims unit 113.Described first pre-amplifier unit 111 provides the first bias current, and amplifies described input signal Vin based on the first bias current.Described second pre-amplifier unit 112 provides the second bias current, and amplify described reference signal Vref based on the second bias current, describedly automatically trim the trigging signal that unit 113 follows the tracks of described latched comparator 120, and adjust the first bias current and the second bias current based on this trigging signal.
This avoid the deviation of the change of supply voltage, input signal, bias current, technique and/or working temperature and the trigging signal of common mode electrical level that the preamplifier 110 that causes exports and latched comparator 120 to the impact of squelch control device 100 performance.
It is easily understood that the reference signal of the input signal and amplification that compare amplification refers to the amplitude of the amplitude of the input signal comparing amplification and the reference signal of amplification.The amplitude of described reference signal pre-sets, and can be called as predetermined threshold.When the amplitude of input signal exceedes described predetermined threshold, described squelch control device 100 output enable signal immediately, start working to make receiving circuit, avoid omitting valid data, the amplitude of input signal lower than predetermined threshold and the duration exceedes scheduled duration time, described squelch control device 100 just exports disable signal, to stop the work of receiving circuit.
In one embodiment, as shown in Figure 2, described first pre-amplifier unit 111 comprises PMOS (P-channel Metal Oxide Semiconductor) transistor PM5, PM1, PM2, PM7, resistance R1, R2.Wherein the source electrode of transistor PM5 is connected with the first supply voltage VDDIO, and the drain electrode of transistor PM5 is connected with the source electrode of transistor PM2 with the source electrode of transistor PM1, and the grid of transistor PM5 is connected with bias voltage pbias; The source electrode of transistor PM7 is connected with the first supply voltage VDDIO, and the drain electrode of transistor PM7 is connected with the drain electrode of transistor PM5, and transistor PM7 and PM5 provides the first bias current.Described input signal Vin is differential signal, comprises the first input differential signal inn and second and inputs the signal inp that checks the mark.The drain electrode of transistor PM1 is by resistance R1 ground connection, and the grid of transistor PM1 receives the first input differential signal inn, and the drain electrode of transistor PM2 is by resistance R2 ground connection, and the grid of transistor PM2 receives the second input differential signal inp.The drain electrode vr1 of transistor PM1 and/or the drain electrode vr2 of transistor PM2 exports the input signal amplified.
Described second pre-amplifier unit comprises PMOS transistor PM6, PM3, PM4, PM8, resistance R3, R4, wherein the source electrode of transistor PM6 is connected with the first supply voltage VDDIO, the drain electrode of transistor PM6 is connected with the source electrode of transistor PM4 with the source electrode of transistor PM3, and the grid of transistor PM6 is connected with bias voltage pbias; The source electrode of transistor PM8 is connected with the first supply voltage VDDIO, and the drain electrode of transistor PM8 is connected with the drain electrode of transistor PM6.Transistor PM6 and PM8 provides the second bias current.Described reference signal Vref is differential signal, comprises the first reference differential Vrefp and the second reference differential Vrefn.The drain electrode of transistor PM3 is by resistance R3 ground connection, and the grid of transistor PM3 receives the first reference differential Vrefp, and the drain electrode of transistor PM4 is by resistance R4 ground connection, and the grid of transistor PM4 receives the second reference differential Vrefn.The drain electrode vr3 of transistor PM3 and/or the drain electrode vr4 of transistor PM4 exports the reference signal Vref_a amplified.First supply voltage VDDIO is the supply voltage of IO (input and output) part.
The described unit 113 that automatically trims comprises trigging signal testing circuit 114, operational amplifier OPA, resistance R5 and R6.In fig. 2, although resistance R5 and R6 is arranged in the dotted line frame of 112, in fact it belong to and automatically trim unit 113.Described trigging signal testing circuit 114 is for detecting the trigging signal of described latched comparator 120, and this trigging signal is supplied to the first input end of operational amplifier OPA, such as negative-phase input, the drain electrode of transistor PM3 is connected to second input of operational amplifier OPA by resistance R5, such as normal phase input end, the drain electrode of transistor PM4 is connected to the second input of operational amplifier by resistance R6, the output of operational amplifier OPA is connected to the grid of transistor PM7 and PM8.The described unit 113 that automatically trims adjusts the first bias current and the second bias current, until the voltage of the first input end of operational amplifier OPA equals the voltage of the second input by the grid voltage of adjustment transistor PM7 and PM8.Like this, preamplifier 110 can be made effectively can to follow the tracks of the trigging signal of latched comparator 120, thus avoid the change of supply voltage, input signal, bias current, technique and/or working temperature and the deviation of the trigging signal of common mode electrical level that the preamplifier 110 that causes exports and latched comparator 120 on the impact of squelch control device 100 performance.
Described latched comparator 120 comprises one or more latch comparing unit.Fig. 3 is this latch comparing unit circuit diagram in one embodiment.As shown in Figure 3, described latch comparing unit comprises PMOS transistor PM11, PM12, PM13, NMOS (N-channel Metal Oxide Semiconductor) transistor NM11, NM12, NM13, inverter INV1.
The source electrode of transistor PM11 is connected with second source voltage vdd, and its drain electrode is connected with the source electrode of transistor PM12 and the source electrode of transistor PM13, and its grid is connected with the grid of transistor NM13.This second source voltage Vdd is the supply voltage of digital circuits section.The source ground of transistor NM13, its drain electrode is connected with the source electrode of transistor NM11 and the source electrode of transistor NM12.The drain electrode of transistor PM12 is connected with the drain electrode of transistor NM11, and its grid is connected with the grid of transistor NM11.The drain electrode of transistor PM13 is connected with the drain electrode of transistor NM12, and its grid is connected with the grid of transistor NM12.The drain electrode of transistor PM12 is connected with the grid of transistor PM11, and the drain electrode of transistor PM13 is connected with the input of inverter INV1, and the output of inverter INV1 is the output of this latch comparing unit.The grid of transistor PM12 is as the first input end latching comparing unit, and this first input end can be connected to the drain electrode of the transistor PM3 in the second pre-amplifier unit 112 or the drain electrode of transistor PM4.The grid of transistor PM13 is as the second input latching comparing unit, and this second input can be connected to the drain electrode of the transistor PM1 in the first pre-amplifier unit 111 or the drain electrode of transistor PM2.
The output signal upset of this latch comparing unit output when the voltage of first input end and the second input is equal, when overturning, the level of first input end can be known as the trigging signal of this latch comparing unit, and it is also referred to as the trigging signal of latched comparator 120.This trigging signal may change along with the change of supply voltage, input signal, bias current, technique and/or working temperature, thus there is deviation between the common mode electrical level causing preamplifier 110 to export and the trigging signal of latched comparator 120 or make this deviation become large.
In a specific embodiment, as shown in Figure 4, described latched comparator comprises the first latch comparing unit 121, second latch comparing unit 122 and logic sum gate 123.The structure of each latch comparing unit is as Fig. 3 and mentioned above.In this embodiment, first first input end latching comparing unit 121 is connected to the drain electrode vr4 of the transistor PM4 in the second pre-amplifier unit 112, and the second first input end latching comparing unit 122 is connected to the drain electrode vr4 of the transistor PM4 in the second pre-amplifier unit 112.First the second input latching comparing unit 121 is connected to the drain electrode vr1 of the transistor PM1 in the first pre-amplifier unit 111, and the second the second input latching comparing unit 122 is connected to the drain electrode vr2 of the transistor PM2 in the first pre-amplifier unit 111.The output of the first inverter INV1 latched in comparing unit 121 is connected to or an input of door 123, and the output of the second inverter INV1 latched in comparing unit 122 is connected to or another input of door 123.Output that is described or door 123 exports the compare result signal of the reference signal of input signal and the amplification of amplifying.
In the example depicted in fig. 4, when input signal is greater than reference signal, first latches comparing unit 121 output low level, and second latches comparing unit 122 output low level, and described or door 123 output low level, to represent that input signal is greater than reference signal; Otherwise the first latch comparing unit 121 or the second latch comparing unit 122 export high level, and described or door 123 exports high level, to represent that input signal is lower than reference signal.Described pulsed filter 130 starts timing at input signal lower than during reference signal, when timing time exceedes scheduled duration, just exports disable signal.
Refer again to shown in Fig. 2, described trigging signal testing circuit 114 comprises PMOS transistor PM21, PM22, nmos pass transistor NM21, NM22.
The source electrode of transistor PM21 connects second source voltage vdd, and its grid is connected with the grid of transistor NM21, and its drain electrode is connected with the source electrode of transistor PM22.The drain electrode of transistor PM22 is connected with the drain electrode of transistor NM22, and the grid of transistor PM22 is connected with the grid of transistor NM22, and the source electrode of transistor NM22 is connected to the drain electrode of transistor NM21, the source ground of transistor NM21.The grid of transistor PM22 is connected with the drain electrode of transistor PM22, and the drain electrode of transistor PM22 is connected with the grid of transistor PM21, and the voltage of the grid of transistor PM22 is exactly the trigging signal of the described latched comparator 120 detected.
In order to the trigging signal of described latched comparator 120 effectively be detected, need the following condition of size demand fulfillment to each transistor in described trigging signal testing circuit 114: the size of the transistor PM11 in described latch comparing unit and the ratio of the size of the transistor PM21 in described trigging signal testing circuit 114, equal the size sum of transistor PM12 and PM13 in described latch comparing unit and the ratio of the size of the transistor PM22 in described trigging signal testing circuit 114, also the size of the transistor NM13 in described latch comparing unit and the ratio of the size of the transistor NM21 in described trigging signal testing circuit 114 is equaled, also equal the size sum of transistor NM11 and NM12 in described latch units and the ratio of the size of the transistor NM22 in described trigging signal testing circuit 114.Owing to having carried out matched design, described trigging signal testing circuit 114 effectively can detect the trigging signal of described latched comparator 120.
In the present invention, " connection ", be connected, " companys ", " connecing " etc. represent the word be electrical connected, and if no special instructions, then represents direct or indirect electric connection, such as through connected after a resistance, a logical circuit or a functional circuit, etc.
It is pointed out that the scope be familiar with person skilled in art and any change that the specific embodiment of the present invention is done all do not departed to claims of the present invention.Correspondingly, the scope of claim of the present invention is also not limited only to previous embodiment.
Claims (6)
1. a mute control circuit, is characterized in that, it comprises:
Preamplifier, for difference amplification input signal and reference signal;
Latched comparator, for the reference signal of the input signal and amplification that compare amplification;
Pulsed filter, when the input signal of described amplification is greater than the reference signal of described amplification, output enable signal, when the input signal of described amplification is less than the reference signal of described amplification and is continued above predetermined duration, exports disable signal,
Described preamplifier comprises the first pre-amplifier unit, the second pre-amplifier unit and automatically trims unit, described first pre-amplifier unit provides the first bias current, and amplify described input signal based on the first bias current, described second pre-amplifier unit provides the second bias current, and amplify described reference signal based on the second bias current, the described trigging signal automatically trimming latched comparator described in element keeps track, and adjust the first bias current and the second bias current based on this trigging signal.
2. mute control circuit according to claim 1, is characterized in that,
Described first pre-amplifier unit, comprise transistor PM5, PM1, PM2, PM7, resistance R1, R2, wherein the source electrode of transistor PM5 is connected with the first supply voltage, the drain electrode of transistor PM5 is connected with the source electrode of transistor PM2 with the source electrode of transistor PM1, and the grid of transistor PM5 is connected with bias voltage; The source electrode of transistor PM7 is connected with the first supply voltage, the drain electrode of transistor PM7 is connected with the drain electrode of transistor PM5, transistor PM7 and PM5 provides the first bias current, the drain electrode of transistor PM1 is by resistance R1 ground connection, described input signal comprises the first input differential signal and the second input differential signal, the grid of transistor PM1 receives the first input differential signal, the drain electrode of transistor PM2 is by resistance R2 ground connection, the grid of transistor PM2 receives the second input differential signal, the drain electrode of transistor PM1 and/or the drain electrode of transistor PM2 export the input signal amplified
Described second pre-amplifier unit, comprise transistor PM6, PM3, PM4, PM8, resistance R3, R4, wherein the source electrode of transistor PM6 is connected with the first supply voltage, the drain electrode of transistor PM6 is connected with the source electrode of transistor PM4 with the source electrode of transistor PM3, and the grid of transistor PM6 is connected with bias voltage; The source electrode of transistor PM8 is connected with the first supply voltage, and the drain electrode of transistor PM8 is connected with the drain electrode of transistor PM6, and transistor PM6 and PM8 provides the first bias current, the drain electrode of transistor PM3 by resistance R3 ground connection,
Described reference signal comprises the first reference differential and the second reference differential, the grid of transistor PM3 receives the first reference differential, the drain electrode of transistor PM4 is by resistance R4 ground connection, the grid of transistor PM4 receives the second reference differential, the drain electrode of transistor PM3 and/or the drain electrode of transistor PM4 export the reference signal of amplifying
Describedly automatically trim unit, comprise trigging signal testing circuit, operational amplifier, resistance R5 and R6, described trigging signal testing circuit is for detecting the trigging signal of described latched comparator, and this trigging signal is supplied to the first input end of operational amplifier, the drain electrode of transistor PM3 is connected to the second input of operational amplifier by resistance R5, the drain electrode of transistor PM4 is connected to the second input of operational amplifier by resistance R6, the output of operational amplifier is connected to the grid of transistor PM7 and PM8
The described unit that automatically trims adjusts the first bias current and the second bias current, until the voltage of the first input end of operational amplifier equals the voltage of the second input by the grid voltage of adjustment transistor PM7 and PM8.
3. mute control circuit according to claim 2, is characterized in that, described latched comparator comprises one or more latch comparing unit, and each latch comparing unit comprises transistor PM11, PM12, PM13, NM11, NM12, NM13, inverter INV1,
The source electrode of transistor PM11 is connected with second source voltage, and its drain electrode is connected with the source electrode of transistor PM12 and the source electrode of transistor PM13, and its grid is connected with the grid of transistor NM13,
The source ground of transistor NM13, its drain electrode is connected with the source electrode of transistor NM11 and the source electrode of transistor NM12,
The drain electrode of transistor PM12 is connected with the drain electrode of transistor NM11, and its grid is connected with the grid of transistor NM11, and the drain electrode of transistor PM13 is connected with the drain electrode of transistor NM12, and its grid is connected with the grid of transistor NM12,
The drain electrode of transistor PM12 is connected with the grid of transistor PM11,
The drain electrode of transistor PM13 is connected with the input of inverter INV1, and the output of inverter INV1 is the output of this latch comparing unit,
The grid of transistor PM12 is as the first input end latching comparing unit, and this first input end is connected to the drain electrode of the transistor PM3 in the second pre-amplifier unit or the drain electrode of transistor PM4,
The grid of transistor PM13 is as the second input latching comparing unit, and this second input is connected to the drain electrode of the transistor PM1 in the first pre-amplifier unit or the drain electrode of transistor PM2.
4. mute control circuit according to claim 3, is characterized in that, described trigging signal testing circuit comprises transistor PM21, PM22, NM21, NM22,
The source electrode of transistor PM21 connects second source voltage, and its grid is connected with the grid of transistor NM21, and its drain electrode is connected with the source electrode of transistor PM22,
The drain electrode of transistor PM22 is connected with the drain electrode of transistor NM22, and the grid of transistor PM22 is connected with the grid of transistor NM22, and the source electrode of transistor NM22 is connected to the drain electrode of transistor NM21, the source ground of transistor NM21,
The grid of transistor PM22 is connected with the drain electrode of transistor PM22, and the drain electrode of transistor PM22 is connected with the grid of transistor PM21, and the voltage of the grid of transistor PM22 is exactly the trigging signal of the described latched comparator detected.
5. mute control circuit according to claim 4, is characterized in that, described latched comparator comprise the first latch comparing unit, second latch comparing unit and or door,
First first input end latching comparing unit is connected to the drain electrode of the transistor PM4 in the second pre-amplifier unit, and the second first input end latching comparing unit is connected to the drain electrode of the transistor PM4 in the second pre-amplifier unit,
First the second input latching comparing unit is connected to the drain electrode of the transistor PM1 in the first pre-amplifier unit, and the second the second input latching comparing unit is connected to the drain electrode of the transistor PM2 in the first pre-amplifier unit,
The output of the first inverter INV1 latched in comparing unit is connected to or an input of door, and the output of the second inverter INV1 latched in comparing unit is connected to or another input of door,
Output that is described or door exports the compare result signal of the reference signal of input signal and the amplification of amplifying.
6. mute control circuit according to claim 4, is characterized in that,
The size of the transistor PM11 in each latch units and the ratio of the size of the described transistor PM21 automatically trimmed in unit,
Equal the size sum of transistor PM12 and PM13 in each latch units and the ratio of the size of the described transistor PM22 automatically trimmed in unit,
Also the size of the transistor NM13 in each latch units and the ratio of the size of the described transistor NM21 automatically trimmed in unit is equaled,
Also equal the size sum of transistor NM11 and NM12 in each latch units and the ratio of the size of the described transistor NM22 automatically trimmed in unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410828572.9A CN104579185B (en) | 2014-12-23 | 2014-12-23 | High-precision mute control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410828572.9A CN104579185B (en) | 2014-12-23 | 2014-12-23 | High-precision mute control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104579185A true CN104579185A (en) | 2015-04-29 |
| CN104579185B CN104579185B (en) | 2017-10-27 |
Family
ID=53094551
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410828572.9A Active CN104579185B (en) | 2014-12-23 | 2014-12-23 | High-precision mute control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104579185B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109459622A (en) * | 2018-10-24 | 2019-03-12 | 江南大学 | A kind of Low-Power CMOS squelch detector |
| CN116488623A (en) * | 2023-06-25 | 2023-07-25 | 广芯微电子(苏州)有限公司 | Current comparator |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4117410A (en) * | 1977-10-13 | 1978-09-26 | Motorola, Inc. | Phase locked loop signal demodulator and squelch circuit |
| US20040156513A1 (en) * | 2003-02-07 | 2004-08-12 | Cable Electronics, Inc. | System and method for providing audio signals over conventional power lines |
| CN101127510A (en) * | 2006-08-17 | 2008-02-20 | 松下电器产业株式会社 | Differential input class D amplifier |
| CN101449336A (en) * | 2006-03-21 | 2009-06-03 | 剑桥模拟技术有限责任公司 | Offset cancellation for sampled-data circuits |
| JP2013017037A (en) * | 2011-07-04 | 2013-01-24 | Nippon Antenna Co Ltd | Level adjustment device |
| CN103973274A (en) * | 2014-05-20 | 2014-08-06 | 上海华力微电子有限公司 | Latch comparator |
-
2014
- 2014-12-23 CN CN201410828572.9A patent/CN104579185B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4117410A (en) * | 1977-10-13 | 1978-09-26 | Motorola, Inc. | Phase locked loop signal demodulator and squelch circuit |
| US20040156513A1 (en) * | 2003-02-07 | 2004-08-12 | Cable Electronics, Inc. | System and method for providing audio signals over conventional power lines |
| CN101449336A (en) * | 2006-03-21 | 2009-06-03 | 剑桥模拟技术有限责任公司 | Offset cancellation for sampled-data circuits |
| CN101127510A (en) * | 2006-08-17 | 2008-02-20 | 松下电器产业株式会社 | Differential input class D amplifier |
| JP2013017037A (en) * | 2011-07-04 | 2013-01-24 | Nippon Antenna Co Ltd | Level adjustment device |
| CN103973274A (en) * | 2014-05-20 | 2014-08-06 | 上海华力微电子有限公司 | Latch comparator |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109459622A (en) * | 2018-10-24 | 2019-03-12 | 江南大学 | A kind of Low-Power CMOS squelch detector |
| CN109459622B (en) * | 2018-10-24 | 2021-02-05 | 江南大学 | Low-power-consumption CMOS squelch detector |
| CN116488623A (en) * | 2023-06-25 | 2023-07-25 | 广芯微电子(苏州)有限公司 | Current comparator |
| CN116488623B (en) * | 2023-06-25 | 2023-10-20 | 广芯微电子(苏州)有限公司 | Current comparator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104579185B (en) | 2017-10-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7705573B2 (en) | Constant voltage circuit | |
| US8742819B2 (en) | Current limiting circuitry and method for pass elements and output stages | |
| CN108809278B (en) | Narrow pulse peak value sampling hold circuit | |
| US20210018541A1 (en) | Current comparator for submicron processes | |
| JP2006284577A (en) | Detection circuit | |
| US10734955B2 (en) | Audio amplifier, audio output device including the same, and electronic apparatus | |
| US7893768B2 (en) | Automatic gain control | |
| US9753472B2 (en) | LDO life extension circuitry | |
| CN104579185A (en) | High-precision muting control circuit | |
| US7372307B1 (en) | Efficient current monitoring for DC-DC converters | |
| TWI535196B (en) | Amplifier and method of operating the same | |
| US9319041B1 (en) | Squelch detector | |
| JP4855959B2 (en) | Constant current circuit | |
| US7633318B2 (en) | Data receiver of semiconductor integrated circuit and method for controlling the same | |
| JP2000306385A (en) | Complementary differential input buffer for semiconductor memory | |
| US9360505B1 (en) | Squelch detector | |
| JP5025171B2 (en) | Differential amplifier | |
| US9178499B2 (en) | Low-power offset-stored latch | |
| KR102561524B1 (en) | High-speed, low distortion receiver circuit | |
| US10794770B2 (en) | Signal detection circuit and signal detection method | |
| JP2008135834A (en) | Operational amplifier circuit | |
| CN110635790A (en) | Voltage type hysteresis comparator | |
| US20100026359A1 (en) | Interface circuit for bridging voltage domains | |
| CN117674876B (en) | RS-485 receiver circuit | |
| KR19990003173A (en) | Current Mirror Differential Amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: High-precision muting control circuit Effective date of registration: 20180420 Granted publication date: 20171027 Pledgee: Wick International Holding Co., Ltd. Pledgor: Brite Semiconductor (Shanghai) Corporation Registration number: 2018310000019 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20190416 Granted publication date: 20171027 Pledgee: Wick International Holding Co., Ltd. Pledgor: Brite Semiconductor (Shanghai) Corporation Registration number: 2018310000019 |
|
| PC01 | Cancellation of the registration of the contract for pledge of patent right | ||
| CP01 | Change in the name or title of a patent holder |
Address after: Room 409, building 1, 88 Chenhui Road, Kingdee Software Park, Zhangjiang High Tech Park, Pudong New Area, Shanghai 201203 Patentee after: Canxin semiconductor (Shanghai) Co.,Ltd. Address before: Room 409, building 1, 88 Chenhui Road, Kingdee Software Park, Zhangjiang High Tech Park, Pudong New Area, Shanghai 201203 Patentee before: BRITE SEMICONDUCTOR (SHANGHAI) Corp. |
|
| CP01 | Change in the name or title of a patent holder |