CN110635790A - Voltage type hysteresis comparator - Google Patents

Voltage type hysteresis comparator Download PDF

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CN110635790A
CN110635790A CN201911105885.0A CN201911105885A CN110635790A CN 110635790 A CN110635790 A CN 110635790A CN 201911105885 A CN201911105885 A CN 201911105885A CN 110635790 A CN110635790 A CN 110635790A
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transistor
pmos
stage
nmos
drain
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CN110635790B (en
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王映杰
黄少卿
罗永波
宣志斌
肖培磊
李现坤
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CETC 58 Research Institute
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
    • H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
    • H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage

Abstract

The invention discloses a voltage type hysteresis comparator, and belongs to the technical field of analog circuits. The circuit comprises a differential input stage, a gain stage, a hysteresis stage and an output stage. The differential input stage performs primary amplification on a double-end input differential signal and outputs the signal in a single end; the gain stage receives the differential input stage signal after the first-stage amplification and performs second-stage amplification on the differential input stage signal; the hysteresis stage is used for generating a hysteresis quantity of the comparator; the output stage outputs the result of the comparator. The invention can realize the hysteresis comparison function, wherein the rising flip threshold value is completely determined by the size proportion of the MOS tube, so the invention is very accurate and is not influenced by temperature and process change, and the falling flip threshold value only depends on the parameters of the MOS tube, so the hysteresis quantity can be conveniently set.

Description

Voltage type hysteresis comparator
Technical Field
The invention relates to the technical field of analog circuits, in particular to a voltage type hysteresis comparator.
Background
A typical comparator circuit compares the voltage values of two input signals and generates an output signal based on their relative values. In the normal case, when the two input voltages are equal, the output state switches. Thus, when the two input signals are equal or close, uncertainty in the output results, in which case the output of the comparator may switch states back and forth depending on the noise of the input stage.
To solve this problem, some comparators have hysteresis circuits to provide separate transition thresholds for the forward and reverse changes of the input signals, thereby avoiding the possibility of noise causing false triggering of the output when the voltage values of the two input signals are close.
Conventional methods for introducing hysteresis into a comparator generally involve changes in the input impedance of the comparator and require additional bias current to be applied to the hysteresis circuit, which can cause inaccuracies in the forward and reverse trip thresholds and limit the accuracy of the hysteresis comparator.
Therefore, there is a need for an integrated circuit comparator that includes a hysteresis stage and that overcomes some of the drawbacks and limitations of currently known comparators.
Disclosure of Invention
The invention aims to provide a voltage type hysteresis comparator to solve the problem that when hysteresis is introduced into a traditional comparator, a forward jump threshold and a reverse jump threshold are prone to be inaccurate, so that the accuracy of the hysteresis comparator is limited.
To solve the above technical problem, the present invention provides a voltage-type hysteresis comparator, comprising:
the differential input stage is used for carrying out primary amplification on the double-end input differential signal and outputting the signal in a single end;
the gain stage receives the differential input stage signal after the first-stage amplification and performs second-stage amplification on the differential input stage signal;
a hysteresis stage for generating a hysteresis amount of the comparator;
and an output stage outputting the result of the comparator.
Optionally, the differential input stage includes differential pair NMOS transistors MN1 and MN2, current mirror PMOS transistors MP1 and MP2, and constant current source NMOS transistor MN 3; wherein the content of the first and second substances,
the gate of the NMOS transistor MN1 is connected to the first input signal VP, the source of the NMOS transistor MN2 is connected to the drain of the NMOS transistor MN3, and the drain of the NMOS transistor MN1 is connected to the drain of the PMOS transistor MP1, both of which form a conductive path;
the grid electrode of the NMOS transistor MN2 is connected with a second input signal VM, the drain electrode of the NMOS transistor MN2 is connected with the drain electrode of the PMOS transistor MP2, and a conductive path is formed between the two;
the gates of the PMOS transistor MP1 and the PMOS transistor MP2 are connected with each other and then are connected to the drain of the PMOS transistor MP1, and the sources of the PMOS transistor MP1 and the PMOS transistor MP2 are both connected with a power voltage VDD;
the grid electrode of the NMOS transistor MN3 is connected with an external bias potential Vb, and the source electrode is grounded.
Optionally, the gain stage includes an amplifying transistor PMOS transistor MP5 and a constant current source NMOS transistor MN 4; wherein the content of the first and second substances,
the grid electrode of the PMOS tube MP5 is connected with the drain electrodes of the PMOS tube MP2 and the NMOS tube MN2, the drain electrode is connected with the drain electrode of the NMOS tube MN4, and the source electrode is connected with a power supply voltage VDD;
the grid electrode of the NMOS transistor MN4 is connected with an external bias potential Vb, and the source electrode is grounded; the PMOS pipe MP5 and the NMOS pipe MN4 are connected in series to form a conductive path.
Optionally, the hysteresis stage includes a current mirror PMOS transistor MP3 and a switching transistor PMOS transistor MP 4; wherein the content of the first and second substances,
the grid electrode of the PMOS tube MP3 is connected with the grid electrodes of the PMOS tubes MP1 and MP2, the drain electrode is connected with the drain electrode of the PMOS tube MP2 and the drain electrode of the NMOS tube MN2, and the source electrode is connected with the drain electrode of the PMOS tube MP 4;
the grid electrode of the PMOS tube MP4 is connected with the drain electrode of the PMOS tube MP5 and the drain electrode of the NMOS tube MN4, and the source electrode is connected with a power supply voltage VDD;
the PMOS transistor MP3 and the PMOS transistor MP4 are connected in series to form a conductive path.
Optionally, the output stage includes an output transistor MN5, a gate of the NMOS transistor MN5 is connected to the drain of the PMOS transistor MP5 and the drain of the NMOS transistor MN4, a source is grounded, and the drain is an open-drain output OUT.
Optionally, the channel width-to-length ratios of the PMOS transistors MP1 and MP2 are equal, and the channel width-to-length ratios of the NMOS transistors MN1 and MN2 are equal.
The invention provides a voltage-type hysteresis comparator which comprises a differential input stage, a gain stage, a hysteresis stage and an output stage. The differential input stage performs primary amplification on a double-end input differential signal and outputs the signal in a single end; the gain stage receives the differential input stage signal after the first-stage amplification and performs second-stage amplification on the differential input stage signal; the hysteresis stage is used for generating a hysteresis quantity of the comparator; the output stage outputs the result of the comparator.
The invention can realize the hysteresis comparison function, wherein the rising flip threshold value is completely determined by the size proportion of the MOS tube, so the invention is very accurate and is not influenced by temperature and process change, and the falling flip threshold value only depends on the parameters of the MOS tube, so the hysteresis quantity can be conveniently set.
Drawings
Fig. 1 is a schematic diagram of a voltage-type hysteresis comparator according to the present invention.
Detailed Description
The following describes a voltage-type hysteresis comparator in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a voltage-type hysteresis comparator, the structure of which is shown in fig. 1, comprising a differential input stage 10; a gain stage 20; a hysteresis stage 30; an output stage 40.
Specifically, with continued reference to fig. 1, the differential input stage 10 includes differential pair NMOS transistors MN1 and MN2, current mirror PMOS transistors MP1 and MP2, and constant current source NMOS transistor MN 3; the gate of the NMOS transistor MN1 is connected to the first input signal VP, the source of the NMOS transistor MN2 is connected to the drain of the NMOS transistor MN3, and the drain of the NMOS transistor MN1 is connected to the drain of the PMOS transistor MP1, which form a conductive path; the grid electrode of the NMOS transistor MN2 is connected with a second input signal VM, the drain electrode of the NMOS transistor MN2 is connected with the drain electrode of the PMOS transistor MP2, and a conductive path is formed between the two; the gates of the PMOS transistor MP1 and the PMOS transistor MP2 are connected with each other and then are connected to the drain of the PMOS transistor MP1, and the sources of the PMOS transistor MP1 and the PMOS transistor MP2 are both connected with a power voltage VDD; the grid electrode of the NMOS transistor MN3 is connected with an external bias potential Vb, and the source electrode is grounded. The PMOS transistor MP1 and the PMOS transistor MP2 together form a current mirror structure, and since the gate-source voltages of the PMOS transistor MP1 and the PMOS transistor MP2 are the same, and the channel width-to-length ratios of the two transistors are the same, the currents flowing through the two transistors are also the same.
The gain stage 20 comprises an amplifying tube PMOS tube MP5 and a constant current source NMOS tube MN 4; the grid electrode of the PMOS tube MP5 is connected with the drain electrodes of the PMOS tube MP2 and the NMOS tube MN2, the drain electrode is connected with the drain electrode of the NMOS tube MN4, and the source electrode is connected with a power supply voltage VDD; the grid electrode of the NMOS transistor MN4 is connected with an external bias potential Vb, and the source electrode is grounded; the PMOS pipe MP5 and the NMOS pipe MN4 are connected in series to form a conductive path.
The hysteresis stage 30 comprises a current mirror PMOS tube MP3 and a switch tube PMOS tube MP 4; the grid electrode of the PMOS tube MP3 is connected with the grid electrodes of the PMOS tubes MP1 and MP2, the drain electrode of the PMOS tube MP2 is connected with the drain electrode of the NMOS tube MN2, and the source electrode of the PMOS tube MP4 is connected with the drain electrode of the NMOS tube MP 4; the grid electrode of the PMOS tube MP4 is connected with the drain electrode of the PMOS tube MP5 and the drain electrode of the NMOS tube MN4, and the source electrode is connected with a power supply voltage VDD; the PMOS transistor MP3 and the PMOS transistor MP4 are connected in series to form a conductive path. When the grid potential of the switch transistor PMOS transistor MP4 is low, a path is provided for the current mirror PMOS transistor MP3, and the conductive path is parallel to the PMOS transistor MP2, so that the current flowing into the PMOS transistor MP2 is shunted, and a part of the current flows into the PMOS transistor MP 3; when the gate of the switch transistor PMOS transistor MP4 is low, the hysteresis stage 30 will not shunt from the current mirror PMOS transistor MP 2. Thus, a change in the state of the PMOS transistor MP4 can result in whether the hysteresis stage 30 is shunted away from the current mirror PMOS transistor MP 2.
The output stage comprises an output tube NMOS tube MN5, the grid electrode of the NMOS tube MN5 is connected with the drain electrode of the PMOS tube MP5 and the drain electrode of the NMOS tube MN4, the source stage is grounded, and the drain electrode is an open-drain output OUT. Preferably, the channel width-to-length ratios of the PMOS transistors MP1 and MP2 are equal, and the channel width-to-length ratios of the NMOS transistors MN1 and MN2 are equal.
Initially, assuming that the first input signal VP is smaller than the voltage value of the second input signal VM, the amplifying transistor PMOS transistor MP5 is in the on state, and the switching transistor PMOS transistor MP4 is in the off state, shielding the hysteresis stage 30 from acting. Since the channel width-to-length ratios of the NMOS transistors MN1 and MN2 are equal, and the channel width-to-length ratios of the PMOS transistors MP1 and MP2 are equal, when the voltage value of the first input signal VP rises to the voltage value of the second input signal VM, the open-drain output OUT will flip, that is, in the embodiment, the rising flip threshold is denoted as V+When the voltage of the first input signal VP rises to the voltage of the second input signal VM, the current flowing through the NMOS transistor MN2 decreases due to the increase of the current flowing through the PMOS transistor MP2, so that the PMOS transistor MP5 is turned off. It can be seen that the rising rollover threshold V+The method is only dependent on the size proportion of the MOS tube, and is independent of the process, the temperature and the voltage of the MOS tube, so that the rising and turning threshold value is very accurate.
At this time, the amplifying transistor PMOS transistor MP5 is turned off, the switching transistor PMOS transistor MP4 is turned on, and the conductive path of the hysteresis current mirror PMOS transistor MP3 is superimposed on the conductive path of the PMOS transistor MP2 to generate a shunt current, thereby changing the mirror ratio. The equation can be described as:
VHYS＝V+-V- (1)
wherein VHYSIs the hysteresis, V-is the falling transition threshold, V+Is to raise the rollover threshold.
VHYS＝VGSMN2-VGSMN1 (2)
VGSMN2Is the gate-source voltage, V, of NMOS transistor MN2GSMN1Is the gate-source voltage of NMOS transistor MN1, wherein,
Figure BDA0002271275230000051
Figure BDA0002271275230000052
wherein KNIs a process parameter of NMOS tube, VTNFor NMOS transistor turn-on threshold, IMN2Is the current, I, flowing through the NMOS transistor MN2MN1Is the current flowing through the NMOS tube MN1, (W/L)MN1，(W/L)MN2The channel width-length ratios of the NMOS transistors MN1 and MN2, respectively.
According to the mirror ratio of the current mirror, the input conditions of the falling transition threshold value V-are as follows:
(W/L)MP1、(W/L)MP2and (W/L)MP3The channel width-to-length ratios of the PMOS transistors MP1, MP2, and MP3, respectively. Assuming that all the MOS transistors in the above embodiments are ideal MOS transistors, the channel width-to-length ratio W/L of the NMOS transistors MN1 and MN2 is defined as aN：
aN＝(W/L)MN1＝(W/L)MN2 (6)
Defining the channel width-length ratio W/L of the PMOS tubes MP1 and MP2 as aP：
aP＝(W/L)MP1＝(W/L)MP2 (7)
Further defining W/L of PMOS transistor MP3 as aH：
aH＝(W/L)MP3 (8)
Then:
Figure BDA0002271275230000054
combining formula (5) and formula (9) to obtain:
Figure BDA0002271275230000055
it can be seen from fig. 1 that the current I flowing through the NMOS transistor MN3MN3：
IMN3＝IMN1+IMN2 (11)
Combining formula (11) and formula (5) to obtain:
Figure BDA0002271275230000061
bringing formula (12) into formula (10):
Figure BDA0002271275230000062
the above equation (13) proves that the hysteresis amount in the disclosed comparator is obtained by controlling the proportional relationship between the dimensions of the hysteresis transistor of the PMOS transistor MP3 and the current mirror MOS transistor, and the magnitude of the tail current flowing into the differential pair transistor.
In summary, in the disclosed embodiments, the rising transition threshold is determined by the transistor size ratio, independent of temperature and process parameters, and therefore very accurate, and the falling transition threshold is related to the tail current value, transistor size and process parameter KNIn this regard, precise control is possible.
In the present invention, the terms "connected", "connecting", and the like mean electrically connected, and mean directly or indirectly electrically connected unless otherwise specified.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (6)

1. A voltage-mode hysteretic comparator, comprising:
the differential input stage is used for carrying out primary amplification on the double-end input differential signal and outputting the signal in a single end;
the gain stage receives the differential input stage signal after the first-stage amplification and performs second-stage amplification on the differential input stage signal;
a hysteresis stage for generating a hysteresis amount of the comparator;
and an output stage outputting the result of the comparator.
2. The voltage-mode hysteretic comparator of claim 1, wherein said differential input stage comprises differential pair NMOS transistors MN1 and MN2, current mirror PMOS transistors MP1 and MP2, and constant current source NMOS transistor MN 3; wherein the content of the first and second substances,
the gate of the NMOS transistor MN1 is connected to the first input signal VP, the source of the NMOS transistor MN2 is connected to the drain of the NMOS transistor MN3, and the drain of the NMOS transistor MN1 is connected to the drain of the PMOS transistor MP1, both of which form a conductive path;
the grid electrode of the NMOS transistor MN2 is connected with a second input signal VM, the drain electrode of the NMOS transistor MN2 is connected with the drain electrode of the PMOS transistor MP2, and a conductive path is formed between the two;
the gates of the PMOS transistor MP1 and the PMOS transistor MP2 are connected with each other and then are connected to the drain of the PMOS transistor MP1, and the sources of the PMOS transistor MP1 and the PMOS transistor MP2 are both connected with a power voltage VDD;
the grid electrode of the NMOS transistor MN3 is connected with an external bias potential Vb, and the source electrode is grounded.
3. The voltage-mode hysteresis comparator of claim 2, wherein the gain stage comprises an amplifying transistor PMOS transistor MP5 and a constant current source NMOS transistor MN 4; wherein the content of the first and second substances,
the grid electrode of the PMOS tube MP5 is connected with the drain electrodes of the PMOS tube MP2 and the NMOS tube MN2, the drain electrode is connected with the drain electrode of the NMOS tube MN4, and the source electrode is connected with a power supply voltage VDD;
the grid electrode of the NMOS transistor MN4 is connected with an external bias potential Vb, and the source electrode is grounded; the PMOS pipe MP5 and the NMOS pipe MN4 are connected in series to form a conductive path.
4. The voltage-mode hysteretic comparator of claim 3, where said hysteretic stage comprises a current mirror PMOS transistor MP3 and a switching transistor PMOS transistor MP 4; wherein the content of the first and second substances,
the grid electrode of the PMOS tube MP3 is connected with the grid electrodes of the PMOS tubes MP1 and MP2, the drain electrode is connected with the drain electrode of the PMOS tube MP2 and the drain electrode of the NMOS tube MN2, and the source electrode is connected with the drain electrode of the PMOS tube MP 4;
the grid electrode of the PMOS tube MP4 is connected with the drain electrode of the PMOS tube MP5 and the drain electrode of the NMOS tube MN4, and the source electrode is connected with a power supply voltage VDD;
the PMOS transistor MP3 and the PMOS transistor MP4 are connected in series to form a conductive path.
5. The voltage-mode hysteresis comparator as claimed in claim 3, wherein the output stage comprises an output transistor MN5, the gate of the NMOS transistor MN5 is connected to the drain of the PMOS transistor MP5 and the drain of the NMOS transistor MN4, the source is grounded, and the drain is an open-drain output OUT.
6. The voltage-mode hysteresis comparator as claimed in claim 2, wherein the channel width-to-length ratios of the PMOS transistors MP1 and MP2 are equal, and the channel width-to-length ratios of the NMOS transistors MN1 and MN2 are equal.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115348129A (en) * 2022-07-20 2022-11-15 西安电子科技大学芜湖研究院 CAN transceiver receiving circuit

Citations (3)

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Publication number Priority date Publication date Assignee Title
CN102545849A (en) * 2010-12-09 2012-07-04 上海华虹集成电路有限责任公司 Self-adaptive input hysteresis comparator
CN102545848A (en) * 2010-12-09 2012-07-04 上海华虹集成电路有限责任公司 Hysteresis comparator with latching function
CN104579260A (en) * 2013-10-21 2015-04-29 上海华虹集成电路有限责任公司 Hysteresis comparator for radio frequency identification

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102545849A (en) * 2010-12-09 2012-07-04 上海华虹集成电路有限责任公司 Self-adaptive input hysteresis comparator
CN102545848A (en) * 2010-12-09 2012-07-04 上海华虹集成电路有限责任公司 Hysteresis comparator with latching function
CN104579260A (en) * 2013-10-21 2015-04-29 上海华虹集成电路有限责任公司 Hysteresis comparator for radio frequency identification

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115348129A (en) * 2022-07-20 2022-11-15 西安电子科技大学芜湖研究院 CAN transceiver receiving circuit
CN115348129B (en) * 2022-07-20 2023-08-15 西安电子科技大学芜湖研究院 CAN transceiver receiving circuit

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