CN114705904B - High-precision overcurrent detection circuit - Google Patents

High-precision overcurrent detection circuit Download PDF

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CN114705904B
CN114705904B CN202210379145.1A CN202210379145A CN114705904B CN 114705904 B CN114705904 B CN 114705904B CN 202210379145 A CN202210379145 A CN 202210379145A CN 114705904 B CN114705904 B CN 114705904B
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switching tube
tube
switch tube
current
electrode
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CN114705904A (en
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Suzhou Baker Microelectronics Co Ltd
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Suzhou Baker Microelectronics Co Ltd
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16566Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
    • G01R19/16571Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 comparing AC or DC current with one threshold, e.g. load current, over-current, surge current or fault current
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/30Structural combination of electric measuring instruments with basic electronic circuits, e.g. with amplifier

Abstract

The application includes a high accuracy overcurrent detection circuit, concretely relates to current detection technical field. The circuit comprises a power switch tube, a sampling switch tube, a target comparator and a cascode current mirror; the source electrode of the power switch tube is connected with the power input end; the drain electrode of the power switch tube is connected with the inverting input end of the target comparator; the source electrode of the sampling switch tube is connected with the power input end; the drain electrode of the sampling switch tube is connected with the non-inverting input end of the target comparator; the grid electrode of the sampling switch tube is connected with the grid electrode of the power switch tube; the power input end is grounded through the active end of the cascode current mirror; the drain electrode of the sampling switch tube is grounded through the passive end of the cascode current mirror. The circuit avoids the imbalance of the proportion of the mirror current caused by overlarge voltage difference between the drain voltages of the sampling switch tube and the power switch tube, and improves the accuracy of overcurrent detection.

Description

High-precision overcurrent detection circuit
Technical Field
The invention relates to the technical field of current detection, in particular to a high-precision overcurrent detection circuit.
Background
In the circuit structure in the prior art, current is usually required to be detected, and a control signal is generated according to the detection result of the current so as to control the circuit, thereby ensuring the stable operation of the circuit.
As shown in FIG. 1, the common overcurrent detecting device in the IC chip has Mp1 as the power tube for outputting current, ms1 sampling tube with k1 as the width ratio of Mp1 to Ms1 and k1>>1,I o1 And V o1 Output current and output voltage, respectively, I s1 And V s1 The sample current and the sample voltage, respectively. In the detection process, the output current is sampled firstly, and the obtained sampling current is i s1 Then let the sampling current i s Flows into the sampling resistor rs to generate a sampling voltage V s1 Then sample voltage V s1 A reference voltage V input to the non-inverting input of the comparator and connected to the inverting input of the comparator ref1 Comparing the output voltage of the comparator with V c1 Is a logic signal; if I o1 Large, can lead to I s1 And V s1 Also very large, when V s1 Exceeding V ref1 V at the time of c1 At high, the power circuit may be turned off, thereby protecting the power circuit and the following appliances from burning out.
However, in the above scheme, since the drain voltages of Mp1 and Ms1 are different, they are V o1 And V s1 The voltage difference between the two is large and uncontrollable, so that the mirror current proportion of Mp1 and Ms1 is not completely equal to k1:1, and the detection accuracy of the current is low.
Disclosure of Invention
The embodiment of the application provides a high-precision overcurrent detection circuit, which improves the overcurrent detection precision, and comprises a power switch tube, a sampling switch tube, a target comparator and a cascode current mirror;
the source electrode of the power switch tube is connected with the power input end; the drain electrode of the power switch tube is connected with the inverting input end of the target comparator;
the source electrode of the sampling switch tube is connected with the power input end; the drain electrode of the sampling switch tube is connected with the non-inverting input end of the target comparator; the grid electrode of the sampling switch tube is connected with the grid electrode of the power switch tube;
the power supply input end is grounded through the active end of the cascode current mirror;
the drain electrode of the sampling switch tube is grounded through the passive end of the cascode current mirror.
In one possible implementation, the passive end of the cascode current mirror includes a first switching tube and a third switching tube; and the drain electrode of the first switching tube is connected with the source electrode of the third switching tube.
In one possible implementation manner, the active end of the cascode current mirror comprises a reference current source, a second switching tube and a fourth switching tube; and the drain electrode of the second switching tube is connected with the source electrode of the fourth switching tube.
In one possible implementation, the second switching tube gate is connected to the gate of the first switching tube; the grid electrode of the second switching tube is connected with the drain electrode of the second switching tube;
the grid electrode of the fourth switching tube is connected with the grid electrode of the third switching tube; and the grid electrode of the fourth switching tube is connected with the drain electrode of the fourth switching tube.
In one possible implementation, the power supply input terminal is grounded through an active end of the cascode current mirror, including:
the source electrode of the second switching tube is grounded, so that the power input end sequentially passes through the reference current source, the fourth switching tube and the second switching tube to be grounded.
In one possible implementation, the drain of the sampling switch tube is grounded through the passive terminal of the cascode current mirror, including:
the drain electrode of the sampling switch tube is connected to the drain electrode of the third switch tube, and the source electrode of the first switch tube is grounded, so that the drain electrode of the sampling switch tube sequentially passes through the third switch tube and the first switch tube to be grounded.
In one possible implementation, the channel width ratio of the power switch tube to the sampling switch tube is k, and k is greater than 1.
In one possible implementation, the power switch tube and the sampling switch tube are PMOS tubes.
In one possible implementation, the circuit further includes a first current source and a fifth switching tube;
the power input end is connected to the drain electrode of the fourth switching tube through the first current source and the fifth switching tube in sequence;
and the grid electrode of the fifth switching tube is connected with the output end of the target comparator.
In one possible implementation manner, the power supply input terminal is connected to the drain electrode of the fourth switching tube through the first current source and the fifth switching tube in sequence, and includes:
the power input end is connected to the source electrode of the fifth switching tube through a first current source, and the drain electrode of the fifth switching tube is connected with the drain electrode of the fourth switching tube, so that the power input end is connected to the drain electrode of the fourth switching tube through the first current source and the fifth switching tube in sequence;
the fifth switching tube is a PMOS tube.
The technical scheme that this application provided can include following beneficial effect:
in the current detection circuit, through the characteristics of the target comparator, the common-source common-gate current mirror structure and the common-source amplifier structure formed by the passive end in the common-source common-gate current mirror and the sampling switch tube, the value of the sampling voltage is accurately equal to the output voltage value in a critical state, so that the ratio of the sampling current to the output current is accurately equal to the mirror current proportion, meanwhile, the current value of the active end in the common-source common-gate current mirror can be accurately copied to the passive end, and the current flowing through the passive end is equal to the sampling current on the sampling switch tube, so that the value of the sampling current is accurately controlled, and in the current detection process, the drain voltage of the sampling switch tube is accurately equal to the drain voltage of the power switch tube in the critical state, the mirror current proportion imbalance caused by overlarge voltage difference between the sampling switch tube and the drain voltage of the power switch tube is avoided, and the over-current detection accuracy is improved. And by adding a delay control circuit in the judgment of overcurrent and non-overcurrent, the oscillation of the circuit is reduced, and the accuracy of current detection is further improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of an overcurrent detecting device commonly used in an integrated circuit chip.
Fig. 2 is a schematic diagram showing a structure of a high-precision overcurrent detection circuit according to an exemplary embodiment of the present application.
Fig. 3 is a schematic diagram showing a structure of a high-precision overcurrent detection circuit according to an exemplary embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
In the description of the embodiments of the present application, the term "corresponding" may indicate that there is a direct correspondence or an indirect correspondence between the two, or may indicate that there is an association between the two, or may indicate a relationship between the two and the indicated, configured, or the like.
Fig. 2 is a schematic diagram showing a structure of a high-precision overcurrent detection circuit according to an exemplary embodiment of the present application. As shown in fig. 2, the circuit includes a power switch tube Mp, a sampling switch tube Ms, a target comparator A1 and a cascode current mirror;
the source electrode of the power switch tube Mp is connected with the power input end; the drain electrode of the power switch tube Mp is connected with the inverting input end of the target comparator A1;
the source electrode of the sampling switch tube Ms is connected with the power input end; the drain electrode of the sampling switch tube Ms is connected with the non-inverting input end of the target comparator A1; the grid electrode of the sampling switch tube Ms is connected with the grid electrode of the power switch tube Mp;
the power supply input end V dd An active ground (gnd) through the cascode current mirror;
the drain of the sampling switch tube Ms is grounded through the passive end of the cascode current mirror.
Optionally, as shown in fig. 2, the passive end of the cascode current mirror includes a first switching tube M1 and a third switching tube M3; the drain electrode of the first switching tube M1 is connected with the source electrode of the third switching tube M3.
Optionally, as shown in fig. 2, the active end of the cascode current mirror includes a reference current source I ref A second switching tube M2 and a fourth switching tube M4; the drain electrode of the second switching tube M2 is connected with the source electrode of the fourth switching tube M4.
Optionally, as shown in fig. 2, the gate of the second switching tube M2 is connected to the gate of the first switching tube M1; the grid electrode of the second switching tube M2 is connected with the drain electrode of the second switching tube M2;
the grid electrode of the fourth switching tube M4 is connected with the grid electrode of the third switching tube M3; the grid electrode of the fourth switching tube M4 is connected with the drain electrode of the fourth switching tube M4.
Optionally, as shown in fig. 2, the source of the second switching tube M2 is grounded, so that the power input terminal V dd Sequentially through the reference current source I ref The fourth switching tube M4 and the second switching tube M2 are grounded.
Optionally, as shown in fig. 2, the drain electrode of the sampling switch tube Ms is connected to the drain electrode of the third switch tube, and the source electrode of the first switch tube M1 is grounded, so that the drain electrode of the sampling switch tube Ms sequentially passes through the third switch tube M3 and the first switch tube M1 to be grounded.
Alternatively, as shown in fig. 2, the channel width ratio of the power switching transistor Mp to the sampling switching transistor Ms is k, and k is greater than 1.
Optionally, as shown in fig. 2, the power switch tube Mp and the sampling switch tube Ms are PMOS tubes.
The operation principle of the overcurrent detection circuit shown in fig. 2 is explained below.
On the other hand, when the current in the power switch tube in the over-current detection circuit is in a non-over-current state, as shown in fig. 2, the gate control voltages V on the power switch tube Mp and the sampling switch tube Ms g Is equal to the power supply input voltage V dd At this time, the voltage V between the gate sources of the power switch tube Mp and the sampling switch tube Ms gs1 All are 0, the power switch tube Mp and the sampling switch tube Ms are in the cut-off state, and the current I on the power switch tube is at the moment o And current I on sampling switch tube s Satisfy I o =I s The drain currents of the third switching tube M3 and the first switching tube M1 are zero, so the voltage V on the drain of the sampling switching tube Ms s Must be 0, otherwise, there must be current flowing in the cascode current mirror due to V s 0, so when V s When input to the non-inverting input terminal of the target comparator A1, the output of the target comparator A1, namely the output signal V of the overcurrent detection circuit c Is low, representing that the output current in the power switch tube Mp is not excessiveAnd (3) flow.
On the other hand, when the current in the power switching tube Mp in the overcurrent detection circuit is in a critical state, i.e. when the gate control voltage V g From power supply input voltage V dd When the voltage is reduced, the voltage between the grid sources of the power switch tube Mp is increased, so that the output current I on the power switch tube o Increase, so the sampling current I on the sampling switch tube s Also increases; at the same time, due to the fourth switching tube M4 and the second switching tube M2 and the reference current source I ref Is connected in series, so that the current flowing in the fourth switching tube M4 and the second switching tube M2 is unchanged and always is the reference current source I ref Thus, the voltage V between the gate sources of the fourth switching tube M4 and the second switching tube M2 gs2 The grid voltages of the fourth switching tube M4 and the second switching tube M2 are always unchanged, the source electrode of the second switching tube M2 is grounded, the grid voltages of the third switching tube M3 and the first switching tube M1 are always unchanged because the third switching tube M3 is connected with the grid electrode of the fourth switching tube M4 and the first switching tube M1 is connected with the grid electrode of the second switching tube M2;
so when sampling current I s There are several possibilities for increasing:
1. if the voltage V is sampled s The gate voltages of the third switching tube M3 and the first switching tube M1 are unchanged, so that the current flowing through the third switching tube M3 and the first switching tube M1 is unchanged at this time; meanwhile, since the non-inverting input terminal and the inverting input terminal of the comparator cannot flow current, the current I is sampled s All flow into the third switching tube M3 and the first switching tube M1, thus sampling the current I s Current I flowing through the third switching tube m3 Current I flowing through the first switching tube m1 Satisfy I s =I m3 =I m1 Obviously, it is not possible to sample the current I s The current flowing through the third switching tube M3 and the first switching tube M1 is unchanged;
2. if the voltage V is sampled s Since the gate voltages of the third switching tube M3 and the first switching tube M1 are constant, the current flowing through the third switching tube M3 and the first switching tube M1 is reducedThe flow is reduced; meanwhile, since the non-inverting input terminal and the inverting input terminal of the comparator cannot flow current, the current I is sampled s All flow into the third switching tube M3 and the first switching tube M1, thus sampling the current I s Current I flowing through the third switching tube m3 Current I flowing through the first switching tube m1 Satisfy I s =I m3 =I m1 Obviously, it is not possible to sample the current I s Increases while the current through the third switching tube M3 and the first switching tube M1 decreases;
3. if the voltage V is sampled s Since the gate voltages of the third switching tube M3 and the first switching tube M1 are constant, the current flowing through the third switching tube M3 and the first switching tube M1 increases at this time; meanwhile, since the non-inverting input terminal and the inverting input terminal of the comparator cannot flow current, the current I is sampled s All flow into the third switching tube M3 and the first switching tube M1, thus sampling the current I s Current I flowing through the third switching tube m3 Current I flowing through the first switching tube m1 Satisfy I s =I m3 =I m1 Obviously, at this time, the current I is sampled s And the current flowing through the third switching tube M3 increases simultaneously with the first switching tube M1.
As can be seen from the above analysis, the first switching tube M1, the second switching tube M2, the third switching tube M3 and the fourth switching tube M4 together form a common-source common-gate current mirror structure, and the sampling switching tube Ms, the third switching tube M3 and the first switching tube M1 form a common-source amplifier structure, so that the grid control voltage V g Reduction, output current I o When increasing, sampling current I s Increase, sampling voltage V s And also increases.
When sampling voltage V s To an output voltage V o At this time, the sampling current I in the sampling switch tube Ms s Can be very precisely equal to the output current I o 1/k of (I) s =I o K; and at this time due to V s =V o And assume V at this time o (e.g. V o >0.5V) can enable four MOS tubes (first switch tube M1, second switch tube) of the cascode current mirrorThe switching tube M2, the third switching tube M3 and the fourth switching tube M4) all operate in the saturation region, so that the reference current source I ref The current value can be very precisely copied into the third switching tube M3, and the current I flowing through the third switching tube M3 m3 Equal to the sampling current I at the sampling switch tube Ms s Thus sampling the current I s Current I flowing through the third switching tube m3 Current I flowing through the first switching tube m1 Satisfy I s =I m3 =I ref
In summary, in the critical state, V s =V o ,I ref =I o The threshold voltage of the grid control voltage is V g0
Thus, if the gate control voltage V g From the critical voltage V g0 Increase the output current I o When decreasing, sampling current I s Reducing, sampling voltage V s Also decreases; if the grid electrode is controlled to be at voltage V g From the critical voltage V g0 Reduction, output current I o When increasing, sampling current I s Increase the sampling voltage V s And also increases.
On the other hand, when the current in the power switching tube in the overcurrent detection circuit is in an overcurrent state, i.e. when the gate control voltage V g Continuing to decrease, the output current I o When continuing to increase, sampling current I s Also continue to increase, sampling voltage V s And also continue to increase; therefore at this time V s >V o The output of the target comparator A1, i.e. the output signal V of the over-current detection circuit c Is high, representing the output current in the power switch tube Mp in an overcurrent state.
Specifically, suppose I ref =20ma, k=20; thus, when I o =k*I ref When=400 mA, V o =V s The threshold voltage of the grid control voltage is V g0
When I o Below 400mA, V g Greater than the critical voltage V g0 And because the first switching tube M1, the second switching tube M2, the third switching tube M3 and the fourth switching tube M4 jointly form a common-source common-gateA current mirror structure, and the sampling switch tube Ms, the third switch tube M3 and the first switch tube M1 form a common source amplifier structure, thus, V g Is increased to result in V s So that V is s <V o Output signal V of overcurrent detection circuit c Low, no circuit overcurrent;
when I o Above 400mA, V g Less than the critical voltage V g0 The first switching tube M1, the second switching tube M2, the third switching tube M3 and the fourth switching tube M4 form a common-source common-gate current mirror structure, and the sampling switching tube Ms, the third switching tube M3 and the first switching tube M1 form a common-source amplifier structure, thus V g Is reduced to V s So that at this time V s >V o Output signal V of overcurrent detection circuit c Is high and the circuit is over-current.
In summary, in the current detection circuit, through the characteristics of the target comparator, the cascode current mirror structure and the common source amplifier structure formed by the passive end in the cascode current mirror and the sampling switch tube, the value of the sampling voltage is precisely equal to the output voltage value in the critical state, so that the ratio of the sampling current to the output current is precisely equal to the mirror current proportion, meanwhile, the current value of the active end in the cascode current mirror can be precisely copied to the passive end, and the current flowing through the passive end is equal to the sampling current on the sampling switch tube, so that the value of the sampling current can be precisely controlled.
Fig. 3 is a schematic diagram showing a structure of a high-precision overcurrent detection circuit according to an exemplary embodiment of the present application. As shown in fig. 3, the circuit includes a first current source I in addition to the structure of the high-precision overcurrent detection circuit shown in fig. 2 h A fifth switching tube M5;
the power input end sequentially passes through a first current source I h And the fifth switching tube M5 is connected to the drain electrode of the fourth switching tube M4;
the gate of the fifth switching tube M5 is connected to the output terminal of the target comparator A1.
Optionally, the power supply input is connected to the first current source I h Is connected to the source of the fifth switch tube M5, and the drain of the fifth switch tube M5 is connected to the drain of the fourth switch tube M4, so that the power input end sequentially passes through the first current source I h And the fifth switching tube M5 is connected to the drain electrode of the fourth switching tube M4;
the fifth switching tube is a PMOS tube.
As can be seen from the description of the embodiment shown in fig. 2, in the high-precision overcurrent detection circuit shown in fig. 2, the output current is either over-current or not over-current, which is k×i ref Is determined by the limit, so that when the output current reaches k.times.I ref Nearby, the over-current detection circuit will switch between outputting over-current signal and over-current signal, so that the output current is k×i ref Nearby vibration occurs, and the accuracy of the overcurrent detection circuit is affected;
therefore, at this time, a delay control circuit can be added in the high-precision overcurrent detection circuit shown in fig. 2 to form the high-precision overcurrent detection circuit shown in fig. 3, so that the oscillation of the output current is improved, and the detection accuracy is improved;
the operation principle of the high-precision overcurrent detection circuit shown in fig. 3 is as follows:
1. when the output current of the circuit does not flow excessively, the output signal V of the overcurrent detection circuit c Is low, and at the moment, the fifth switch tube M5 is controlled to be turned on in a delayed manner, and the first current source I h Flows into the fourth switching tube M4, so that the current flowing in the fourth switching tube M4 is I ref +I h Thus, when outputting current I o Up to k (I) ref +I h ) When the overcurrent detection circuit judges overcurrent, the output signal V of the overcurrent detection circuit c Becomes high;
2. when the output current of the circuit flows through it,output signal V of overcurrent detection circuit c To become high, the delay controls the fifth switch tube M5 to be turned off, and the first current source I h Cannot flow into the fourth switching tube M4, so that the current flowing in the fourth switching tube M4 is I ref So that the current I is output o Is lower than k.times.I ref When the overcurrent detection circuit judges that the overcurrent is not flowing, the output signal V of the overcurrent detection circuit c Becomes low;
from the analysis, the delay control circuit is added in the judgment of overcurrent and non-overcurrent, so that the oscillation of the circuit is reduced, and the detection accuracy is improved.
In summary, in the current detection circuit, through the characteristics of the target comparator, the cascode current mirror structure and the common source amplifier structure formed by the passive end in the cascode current mirror and the sampling switch tube, the value of the sampling voltage is precisely equal to the output voltage value in the critical state, so that the ratio of the sampling current to the output current is precisely equal to the mirror current proportion, meanwhile, the current value of the active end in the cascode current mirror can be precisely copied to the passive end, and the current flowing through the passive end is equal to the sampling current on the sampling switch tube, so that the value of the sampling current can be precisely controlled, therefore, in the current detection process, the circuit structure ensures that the drain voltage of the sampling switch tube is precisely equal to the drain voltage of the power switch tube in the critical state, the mirror current proportion imbalance caused by overlarge differential pressure between the sampling switch tube and the drain voltage of the power switch tube is avoided, and the over-current detection precision is improved. And by adding a delay control circuit in the judgment of overcurrent and non-overcurrent, the oscillation of the circuit is reduced, and the accuracy of current detection is further improved.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (8)

1. The high-precision overcurrent detection circuit is characterized by comprising a power switch tube, a sampling switch tube, a target comparator and a cascode current mirror;
the source electrode of the power switch tube is connected with the power input end; the drain electrode of the power switch tube is connected with the inverting input end of the target comparator;
the source electrode of the sampling switch tube is connected with the power input end; the drain electrode of the sampling switch tube is connected with the non-inverting input end of the target comparator; the grid electrode of the sampling switch tube is connected with the grid electrode of the power switch tube, and the drain electrode of the power switch tube outputs output voltage;
the power supply input end is grounded through the active end of the cascode current mirror;
the drain electrode of the sampling switch tube is grounded through the passive end of the cascode current mirror;
when the grid control voltage is in the critical voltage, the output voltage is the same as the drain voltage of the sampling switch tube, and the ratio of the current flowing through the power switch tube to the current flowing through the passive end of the cascode current mirror is k; k is the channel width ratio of the power switch tube to the sampling switch tube, and k is larger than 1;
the circuit also comprises a first current source and a fifth switching tube;
the power input end is connected to the drain electrode of the fourth switching tube through the first current source and the fifth switching tube in sequence;
and the grid electrode of the fifth switching tube is connected with the output end of the target comparator.
2. The circuit of claim 1, wherein the passive end of the cascode current mirror comprises a first switching tube and a third switching tube; and the drain electrode of the first switching tube is connected with the source electrode of the third switching tube.
3. The circuit of claim 2, wherein the active terminal of the cascode current mirror comprises a reference current source, a second switching tube, and a fourth switching tube; and the drain electrode of the second switching tube is connected with the source electrode of the fourth switching tube.
4. A circuit according to claim 3, wherein the second switching tube gate is connected to the gate of the first switching tube; the grid electrode of the second switching tube is connected with the drain electrode of the second switching tube;
the grid electrode of the fourth switching tube is connected with the grid electrode of the third switching tube; and the grid electrode of the fourth switching tube is connected with the drain electrode of the fourth switching tube.
5. The circuit of claim 4, wherein the power supply input is grounded through an active end of the cascode current mirror, comprising:
the source electrode of the second switching tube is grounded, so that the power input end sequentially passes through the reference current source, the fourth switching tube and the second switching tube to be grounded.
6. The circuit of claim 4, wherein the drain of the sampling switch tube is grounded through the passive terminal of the cascode current mirror, comprising:
the drain electrode of the sampling switch tube is connected to the drain electrode of the third switch tube, and the source electrode of the first switch tube is grounded, so that the drain electrode of the sampling switch tube sequentially passes through the third switch tube and the first switch tube to be grounded.
7. The circuit of any of claims 1-6, wherein the power switch tube and the sampling switch tube are PMOS tubes.
8. The circuit of claim 1, wherein the power input is connected to the drain of the fourth switching tube via a first current source and a fifth switching tube in sequence, comprising:
the power input end is connected to the source electrode of the fifth switching tube through a first current source, and the drain electrode of the fifth switching tube is connected with the drain electrode of the fourth switching tube, so that the power input end is connected to the drain electrode of the fourth switching tube through the first current source and the fifth switching tube in sequence;
the fifth switching tube is a PMOS tube.
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CN115528787B (en) * 2022-11-29 2023-05-02 苏州贝克微电子股份有限公司 Control loop accelerating circuit
CN116047147B (en) * 2023-01-28 2023-06-20 苏州贝克微电子股份有限公司 High-precision current detecting circuit
CN116207949B (en) * 2023-04-25 2023-07-11 拓尔微电子股份有限公司 Current sampling circuit and DC-DC converter

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