CN112242823B - Differential input circuit, control method thereof and differential amplifier - Google Patents
Differential input circuit, control method thereof and differential amplifier Download PDFInfo
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- CN112242823B CN112242823B CN201910655121.2A CN201910655121A CN112242823B CN 112242823 B CN112242823 B CN 112242823B CN 201910655121 A CN201910655121 A CN 201910655121A CN 112242823 B CN112242823 B CN 112242823B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45376—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using junction FET transistors as the active amplifying circuit
Abstract
The application discloses differential input circuit, differential input circuit's control method and differential amplifier, differential input circuit includes: the first differential input stage is connected between the positive power supply end and the negative power supply end in series with the first switch; the second differential input stage is connected between the positive power supply end and the negative power supply end in series with the second switch; and the differential detection circuit is used for switching on one of the first switch and the second switch according to the first input signal and the second input signal, wherein positive input ends of the first differential input stage and the second differential input stage receive the first input signal, negative input ends of the first differential input stage and the second differential input stage receive the second input signal, the size of a differential transistor pair in the first differential input stage is different from that of a differential transistor pair in the second differential input stage, and the increase of input offset voltage caused by asymmetry of the transistor pair of a single input stage under the long-time large differential signal operation can be avoided, so that the precision of the amplifier is further influenced.
Description
Technical Field
The invention relates to the technical field of integrated circuit testing, in particular to a differential input circuit, a control method thereof and a differential amplifier comprising the differential input circuit.
Background
A differential amplifier is a circuit that can amplify a difference between two input voltages, and is also called a differential amplifier. Fig. 1 shows a schematic structure of a conventional differential amplifier, and as shown in fig. 1, a differential amplifier 100 includes a differential input circuit 110, an intermediate stage circuit 120, an output stage circuit 130, and a bias circuit 140. The differential input circuit 110 is also called a pre-stage circuit, and is generally a two-terminal input high-performance differential amplifier circuit, and its input terminal is used to input a pair of differential signals. The intermediate stage circuit 120 is a main amplifying circuit of the amplifier, and functions to make the differential amplifier have a strong amplifying capability, and a common emitter (common source) amplifying circuit is often used. The output stage circuit 130 is used for outputting the amplified signal. The bias circuit is used for setting the static operating point of each stage of amplifying circuit in the differential amplifier.
With the development of technology, a differential amplifier is widely used in various circuits, and a differential signal input at an input terminal thereof is also developed from a small differential signal to a large differential signal such as a positive power terminal. However, when a large differential signal is input at the input end of the conventional differential amplifier, the transistor pair in the differential input circuit 110 operates in a biased state for a long time, and the long-time asymmetric operation of the transistor pair may cause asymmetry of device characteristics of the transistor pair in the differential input circuit, which causes the differential amplifier to generate an offset voltage and reduces the accuracy of the differential amplifier.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a differential input circuit, a control method thereof, and a differential amplifier including the differential input circuit, which can avoid the variation of the device characteristics of the transistor pair in the differential input circuit caused by the asymmetric operation of the transistor pair for a long time, and reduce the input offset voltage of the differential amplifier while ensuring the accuracy of the differential amplifier.
According to a first aspect of embodiments of the present invention, there is provided a differential input circuit, including: the first differential input stage is connected between the positive power supply end and the negative power supply end in series with the first switch; the second differential input stage is connected between the positive power supply end and the negative power supply end in series with the second switch; and a differential detection circuit, configured to turn on one of the first switch and the second switch according to a first input signal and a second input signal, where positive input ends of the first differential input stage and the second differential input stage receive the first input signal, negative input ends of the first differential input stage and the second differential input stage receive the second input signal, and sizes of a differential transistor pair in the first differential input stage are different from sizes of a differential transistor pair in the second differential input stage.
Preferably, the differential detection circuit compares the first input signal and the second input signal to obtain a difference signal therebetween, compares the difference signal with a reference signal, and turns on one of the first switch and the second switch according to a comparison result.
Preferably, the size of the differential transistor pair in the first differential input stage is much larger than the size of the differential transistor pair in the second differential input stage, wherein the differential detection circuit turns on the first switch when the difference signal is smaller than the reference signal, and turns on the second switch when the difference signal is greater than/equal to the reference signal.
Preferably, the differential detection circuit includes: the amplifying unit is used for obtaining a first difference signal and a second difference signal according to the first input signal and the second input signal; and a control unit for comparing the first and second difference signals with the reference signal and turning on one of the first and second switches according to a comparison result.
Preferably, the amplifying unit includes a first differential amplifying circuit and a second differential amplifying circuit, the first differential amplifying circuit includes a first inverting terminal, a first non-inverting terminal, and a first output terminal, the first inverting terminal receives the first input signal, the first non-inverting terminal receives the second input signal, the first output terminal is configured to output the first difference signal, the second differential amplifying circuit includes a second inverting terminal, a second non-inverting terminal, and a second output terminal, the second inverting terminal receives the second input signal, the second non-inverting terminal receives the first input signal, and the second output terminal is configured to output the second difference signal.
Preferably, the first switch and the second switch have the same conductivity type, the control unit generates a first switch signal and a second switch signal that are opposite in phase to each other according to the comparison result, and the first switch signal and the second switch signal respectively control the on and off of the first switch and the second switch.
Preferably, the control unit includes: the grid electrodes of the first transistor and the second transistor respectively receive the first difference signal and the second difference signal, the source electrodes of the first transistor and the second transistor are connected with the negative power supply end through a second constant current source, and the drain electrodes of the first transistor and the second transistor are connected with each other; a third transistor, a gate of which is used for receiving the reference signal, and a source of which is connected with a negative power supply terminal through the second constant current source; a fourth transistor and a fifth transistor, which form a current mirror, a power supply terminal of the current mirror is connected to a positive power supply terminal, a drain of the fourth transistor is connected to drains of the first transistor and the second transistor, and a drain of the fifth transistor is connected to a drain of the third transistor; a sixth transistor and a third constant current source connected in series between the positive power supply terminal and the negative power supply terminal, a gate of the sixth transistor being connected to an intermediate node of the third transistor and the fifth transistor, a drain of the sixth transistor being used for providing the first switching signal; and an inverter having an input terminal connected to the drain of the sixth transistor to receive the first switching signal and an output terminal for providing the second switching signal.
Preferably, the first transistor, the second transistor, and the third transistor are N-type metal oxide semiconductor field effect transistors, respectively, and the fourth transistor, the fifth transistor, and the sixth transistor are P-type metal oxide semiconductor field effect transistors, respectively.
Preferably, the first switch and the second switch are different in conductivity type, and the control unit generates a third switch signal that turns on one of the first switch and the second switch and turns off the other of the first switch and the second switch according to the comparison result.
Preferably, the control unit includes: a seventh transistor and an eighth transistor, gates of which receive the first difference signal and the second difference signal, respectively, sources of which are connected to a negative power supply terminal through a fourth constant current source, and drains of which are connected to each other; a ninth transistor, a gate of which is used for receiving the reference signal, and a source of which is connected with a negative power supply terminal through the second constant current source; a tenth transistor and an eleventh transistor, wherein the tenth transistor and the eleventh transistor form a current mirror, a power supply terminal of the current mirror is connected to a positive power supply terminal, a drain of the tenth transistor is connected to drains of the seventh transistor and the eighth transistor, and a drain of the eleventh transistor is connected to a drain of the ninth transistor; a twelfth transistor and a fifth constant current source connected in series between the positive power supply terminal and the negative power supply terminal, a gate of the twelfth transistor being connected to a middle node of the eleventh transistor and the ninth transistor, and a drain of the twelfth transistor being used for providing the third switching signal.
Preferably, the seventh transistor, the eighth transistor, and the ninth transistor are N-type metal oxide semiconductor field effect transistors, respectively, and the tenth transistor, the eleventh transistor, and the twelfth transistor are P-type metal oxide semiconductor field effect transistors, respectively.
Preferably, the first switch and the second switch are selected from one of an electromechanical switch, a metal oxide semiconductor field effect transistor, a complementary metal oxide semiconductor or a bipolar transistor.
According to a second aspect of the embodiments of the present invention, there is provided a control method of the differential input circuit described above, wherein the control method includes: comparing the first input signal with the second input signal to obtain a difference signal; and comparing the difference signal with a reference signal, and turning on one of the first switch and the second switch according to a comparison result.
Preferably, the size of the differential transistor pair in the first differential input stage is larger than the size of the differential transistor pair in the second differential input stage, and the comparing the difference signal with the reference signal, and turning on one of the first switch and the second switch according to the comparison result includes: the first switch is turned on when the difference signal is less than the reference signal, and the second switch is turned on when the difference signal is greater than/equal to the reference signal.
Preferably, the comparing the difference signal with a reference signal, and turning on one of the first switch and the second switch according to the comparison result further includes: obtaining a first difference signal and a second difference signal according to the first input signal and the second input signal; the first switch is turned on when both the first difference signal and the second difference signal are less than the reference signal, and the second switch is turned on when one of the first difference signal and the second difference signal is greater than/equal to the reference signal.
According to a third aspect of embodiments of the present invention, there is provided a differential amplifier including the differential input circuit described above.
The differential input circuit, the control method of the differential input circuit and the differential amplifier provided by the embodiment of the invention have the advantages that: the first differential input stage is connected between the positive power supply end and the negative power supply end in series with the first switch; the second differential input stage is connected between the positive power supply end and the negative power supply end in series with the second switch; and the differential detection circuit is used for switching on one of the first switch and the second switch according to the first input signal and the second input signal, wherein positive input ends of the first differential input stage and the second differential input stage receive the first input signal, negative input ends of the first differential input stage and the second differential input stage receive the second input signal, the size of a differential transistor pair in the first differential input stage is different from that of a differential transistor pair in the second differential input stage, the increase of input offset voltage caused by asymmetry of the transistor pair of a single input stage under long-time large differential signal operation can be avoided, and the precision of the amplifier is reduced.
Furthermore, the size of the differential transistor pair in the first differential input stage is larger than that of the differential transistor pair in the second differential input stage, when the differential input signal is a small signal, the first differential input stage operates, and when the differential input signal is a large signal, the second differential input stage operates, so that the transistor pair in the first differential input stage can be prevented from operating in a bias state for a long time under the action of the differential input signal of the large signal, the change of the device characteristics of the transistor pair in the differential input circuit caused by the long-time asymmetric operation of the transistor pair can be avoided, the accuracy of the differential amplifier can be ensured, and the input offset voltage of the differential amplifier can be reduced.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 shows a schematic diagram of a differential amplifier according to the prior art;
fig. 2 shows a schematic configuration diagram of a differential input circuit according to a first embodiment of the present invention;
FIG. 3 shows a schematic diagram of the differential detection circuit of FIG. 2;
FIG. 4 shows a schematic view of the structure of the amplification unit of FIG. 3;
FIG. 5 is a schematic diagram showing the structure of the control unit in FIG. 3;
fig. 6 shows a schematic configuration diagram of a differential input circuit according to a second embodiment of the present invention;
FIG. 7 shows a schematic diagram of the differential detection circuit of FIG. 6;
fig. 8 shows a schematic diagram of the structure of the control unit in fig. 7.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
In the following description, numerous specific details are set forth, such as configurations of components, materials, dimensions, processing techniques and techniques, in order to provide a more thorough understanding of the present invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
It should be understood that in the following description, a "circuit" refers to a conductive loop formed by at least one element or sub-circuit through an electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.
In this application, the MOSFET comprises a first terminal, a second terminal and a control terminal, and in the on-state of the MOSFET a current flows from the first terminal to the second terminal. The first end, the second end and the control end of the P-type MOSFET are respectively a source electrode, a drain electrode and a grid electrode, and the first end, the second end and the control end of the N-type MOSFET are respectively a drain electrode, a source electrode and a grid electrode.
The invention is further illustrated by the following figures and examples.
Fig. 2 shows a schematic configuration diagram of a differential input circuit of a differential amplifier according to a first embodiment of the present invention. As shown in fig. 2, the differential input circuit 200 includes a first differential input stage 210, a second differential input stage 220, a first switch 230 and a second switch 240, a constant current source 250, and a differential detection circuit 260.
The first differential input stage 210 includes P-type MOSFETs Mp1 and Mp2 having a first transistor size and a resistor R1 and a resistor R2. The P-type MOSFETs Mp1 and Mp2 form a differential transistor pair, i.e., the first terminals and the substrates of the P-type MOSFETs Mp1 and Mp2 are connected to each other, and the substrates of the P-type MOSFETs Mp1 and Mp2 are both connected to the positive power supply terminal VDD. The control terminal of the P-type MOSFET Mp1 is used for receiving a differential input signal V IP The control terminal of the P-type MOSFET Mp2 is used for receiving a differential input signal V IN . The resistor R1 has a first terminal connected to the second terminal of the P-type MOSFET Mp1 and a second terminal connected to the negative power supply terminal VSS. The resistor R2 has a first terminal connected to the second terminal of the P-type MOSFET Mp2 and a second terminal connected to the negative power supply terminal VSS. The first differential input stage 210 is arranged to be operated in response to a differential input signal V IP And V IN Obtain a differential output signal V OP And V ON 。
The second differential input stage 220 includes P-type MOSFETs Mp3 and Mp4 and resistors R3 and R4 having a second transistor size. The P-type MOSFETs Mp3 and Mp4 form a differential transistor pair, i.e., the first terminals and the substrates of the P-type MOSFETs Mp3 and Mp4 are connected to each other, and the substrates of the P-type MOSFETs Mp3 and Mp4 are both connected to the positive power supply terminal VDD. The control terminal of the P-type MOSFET Mp3 is used for receiving a differential input signal V IP The control terminal of the P-type MOSFET Mp4 is used for receiving a differential input signal V IN . The resistor R3 has a first terminal connected to the second terminal of the P-type MOSFET Mp3 and a second terminal connected to the negative power supply terminal VSS. The resistor R4 has a first terminal connected to the second terminal of the P-type MOSFET Mp4, and a second terminal connected to the negative power supplyTerminal VSS. The second differential input stage 220 is for receiving the differential input signal V when in an operational state IP And V IN Obtain a differential output signal V OP And V ON 。
The first switch 230 is connected in series between the supply terminal of the P-type MOSFETs Mp1 and Mp2 forming a differential transistor pair and the constant current source 250, i.e., the first terminals of the P-type MOSFETs Mp1 and Mp2 are both connected to the first switch 230, and the other terminal of the first switch 230 is connected to the constant current source 250. The constant current source 250 is used to provide a bias current to the first differential input stage 210 according to the positive power supply terminal VDD. The second switch 240 is connected in series between the supply terminal of the P-type MOSFETs Mp3 and Mp4 forming a differential transistor pair and the constant current source 250, i.e., the first terminals of the P-type MOSFETs Mp3 and Mp4 are both connected to the second switch 240, and the other terminal of the second switch 240 is connected to the constant current source 250. The constant current source 250 is used to provide a bias current to the second differential input stage 220 according to the positive power supply terminal VDD.
The differential detection circuit 260 is used for detecting the differential input signal V IP And V IN One of the first switch 230 and the second switch 240 is controlled to be conductive so that one of the first differential input stage 210 and the second differential input stage 220 is in an operating state.
Further, the first transistor size of the P-type MOSFETs Mp1 and Mp2 forming the differential transistor pair is much larger than the second transistor size of the P-type MOSFETs Mp3 and Mp4 forming the differential transistor pair. When the differential input signal is a small signal, the differential detection circuit 260 turns on the first switch 230, and the first differential input stage 210 is in a working state; when the differential input signal is a large signal, the differential detection circuit 260 turns on the second switch 240, and the second differential input stage 220 is in a working state, so that the occurrence of asymmetry of the parameter characteristics of the transistor pair in the first differential input stage 210 due to long-time working in a bias state can be avoided, the input offset voltage of the differential amplifier can be reduced, and the precision of the differential amplifier can be improved.
Further, the differential detection circuit 260 converts the differential input signal V IP And a differential input signal V IN Comparing the difference signal with a reference signal to obtain a difference signal, and controlling the first switch 230 and the second switch according to the comparison resultOne of the two switches 240 is turned on.
Further, the first switch 230 and the second switch 240 are selected from one of an electromechanical switch, a metal oxide semiconductor field effect transistor, a complementary metal oxide semiconductor, or a bipolar transistor. Further, the first switch 230 and the second switch 240 are metal oxide semiconductor field effect transistors having the same conductivity type.
As shown in fig. 3, the differential detection circuit 260 includes an amplification unit 261 and a control unit 262. The amplifying unit 261 is used for generating a differential input signal V IP And V IN Resulting in a first difference signal S1 and a second difference signal S2. The control unit 262 is configured to compare the first difference signal S1 and the second difference signal S2 with the reference signal REF, and generate a first switch signal SW1 and a second switch signal SW2 according to the comparison result, wherein the first switch signal SW1 is configured to control the first switch 230 to be turned on and off, and the second switch signal SW2 is configured to control the second switch 240 to be turned on and off.
Fig. 4 shows a schematic view of the structure of the amplification unit in fig. 3. As shown in fig. 4, the amplifying unit 261 includes a differential amplifying circuit OP1, a differential amplifying circuit OP2, a resistor R11 to a resistor R14, and a resistor R21 to a resistor R24. The resistor R11 is connected in series between the inverting terminal and the output terminal of the differential amplification circuit OP 1. The differential amplification circuit OP1 and the differential amplification circuit OP2 are, for example, fully differential amplification circuits. A first terminal of the resistor R12 is for receiving a differential input signal V IN And a second terminal is connected to an inverting terminal of the differential amplification circuit OP 1. A first terminal of the resistor R13 is for receiving a differential input signal V IP And the second terminal is connected to the positive phase terminal of the differential amplification circuit OP 1. The resistor R14 has a first terminal connected to the non-inverting terminal of the differential amplifier circuit OP1 and a second terminal connected to the negative power supply terminal VSS. The output terminal of the differential amplification circuit OP1 is used for outputting a first difference signal S1. The resistor R21 is connected in series between the inverting terminal and the output terminal of the differential amplification circuit OP 2. A first terminal of resistor R22 is for receiving a differential input signal V IP And a second terminal is connected to an inverting terminal of the differential amplification circuit OP 2. A first terminal of the resistor R23 is for receiving a differential input signal V IN And the second terminal is connected to the positive phase terminal of the differential amplification circuit OP 2. Resistor R24Is connected to the non-inverting terminal of the differential amplifying circuit OP2, and is connected to the negative power source terminal VSS. The output terminal of the differential amplifying circuit OP2 is used for outputting a second difference signal S2.
The differential input signal in this embodiment is a semi-differential signal, so that when the differential input signal V is IN Greater than the differential input signal V IP When, the first difference signal S1 is negative and the second difference signal S2 is positive; when differential input signal V IN Less than differential input signal V IP The first difference signal S1 is positive and the second difference signal S2 is negative. The structure of the amplifying unit can ensure the differential input signal V IN And a differential input signal V IP The difference signal of (a) is always positive, which facilitates comparison of the difference signal with a reference signal in a subsequent circuit.
Fig. 5 shows a schematic diagram of the structure of the control unit in fig. 3. As shown in fig. 5, the control unit 262 includes N-type MOSFETs Mn1 to Mn3, a constant current source 2621, a constant current source 2622, an inverter 2623, a current mirror 2624, and a P-type MOSFET Mp 7. The current mirror 2624 includes P-type MOSFETs Mp5 and Mp6, and the power supply terminal of the current mirror 2624 is connected to the positive power supply terminal VDD, i.e., the first terminals of the P-type MOSFETs Mp5 and Mp6 are connected to the positive power supply terminal VDD. An output terminal of the current mirror 2624 is connected to the N-type MOSFETs Mn1 and Mn2, i.e., the second terminal of the P-type MOSFET Mp5 is connected to the first terminals of the N-type MOSFETs Mn1 and Mn 2. The other output terminal of the current mirror 2624 is connected to the N-type MOSFET Mn3, i.e., the second terminal of the P-type MOSFET Mp6 is connected to the first terminal of the N-type MOSFET Mn 3. The control terminal of the N-type MOSFET Mn1 is configured to receive the first difference signal S1, the control terminal of the N-type MOSFET Mn2 is configured to receive the second difference signal S2, and the second terminals of the N-type MOSFETs Mn1 and Mn2 are connected to each other and to the negative power supply terminal VSS through the constant current source 2621. The control terminal of the N-type MOSFET Mn3 is used for receiving the reference signal REF, and the second terminal is connected to the negative power supply terminal VSS through the constant current source 2621. The control terminal of the P-type MOSFET Mp7 is connected to the second terminal of the P-type MOSFET Mp6, the first terminal is connected to the positive power supply terminal VDD, and the second terminal is connected to the negative power supply terminal VSS through the constant current source 2622. An intermediate node of the P-type MOSFET Mp7 and the constant current source 2622 is used to provide the first switch signal SW 1. The inverter 2623 has an input terminal connected to the intermediate node between the P-type MOSFET Mp7 and the constant current source 2622 to receive the first switch signal SW1, and an output terminal for providing a second switch signal SW2 that is inverted with respect to the first switch signal SW 1.
The width-to-length ratios of the P-type MOSFETs Mp5 and Mp6 are set to be equal to ensure equal currents flow.
When both the first difference signal S1 and the second difference signal S2 are less than the reference signal REF, the first switch signal SW1 is asserted, the second switch signal SW2 is de-asserted, and the first switch 230 is turned on and the second switch 240 is turned off. When one of the first difference signal S1 and the second difference signal S2 is greater than the reference signal REF, the output of the P-type MOSFET Mp7 flips, the first switch signal SW1 is inactive, the second switch signal SW2 is active, and the first switch 230 is turned off and the second switch 240 is turned on.
Fig. 6 shows a schematic configuration diagram of a differential input circuit of a differential amplifier according to a second embodiment of the present invention. The differential input circuit 300 of the present embodiment is different from the differential input circuit 200 of the first embodiment in that: in the differential input circuit 300 of the present embodiment, the first switch 230 and the second switch 240 have different conductivity types, and the differential detection circuit 360 detects the differential input signal V IN And V IP The third switch signal SW3 is generated, one of the first switch 230 and the second switch 240 is turned on and the other of the first switch 230 and the second switch 240 is turned off according to the third switch signal SW 3. In addition, other structures of the differential input circuit 300 are substantially the same as those of the differential input circuit 200, and are not described herein again.
Fig. 7 shows a schematic diagram of the structure of the differential detection circuit in fig. 6. As shown in fig. 7, the differential detection circuit 360 includes an amplification unit 361 and a control unit 362. The amplifying unit 361 is for generating a differential input signal V IP And V IN Resulting in a first difference signal S1 and a second difference signal S2. The control unit 362 is configured to compare the first difference signal S1 and the second difference signal S2 with the reference signal REF, and generate a third switch signal SW3 according to the comparison result, wherein the third switch signal SW3 is configured to control the first switch 230 and the second switch 240 to be turned on and off.
The structure of the amplifying unit 361 is the same as that of the amplifying unit 261 in the first embodiment, and is not described herein again.
Fig. 8 shows a schematic diagram of the structure of the control unit in fig. 7. As shown in fig. 8, the control unit 362 includes N-type MOSFETs Mn1 to Mn3, a constant current source 3621, a constant current source 3622, a current mirror 3624, and a P-type MOSFET Mp 7. The current mirror 3624 includes P-type MOSFETs Mp5 and Mp6, and the power supply terminal of the current mirror 3624 is connected to the positive power supply terminal VDD, i.e., the first terminals of the P-type MOSFETs Mp5 and Mp6 are connected to the positive power supply terminal VDD. An output terminal of the current mirror 3624 is connected to the N-type MOSFETs Mn1 and Mn2, i.e., the second terminal of the P-type MOSFET Mp5 is connected to the first terminals of the N-type MOSFETs Mn1 and Mn 2. The other output terminal of the current mirror 3624 is connected to the N-type MOSFET Mn3, i.e., the second terminal of the P-type MOSFET Mp6 is connected to the first terminal of the N-type MOSFET Mn 3. A control terminal of the N-type MOSFET Mn1 is configured to receive the first difference signal S1, a control terminal of the N-type MOSFET Mn2 is configured to receive the second difference signal S2, and second terminals of the N-type MOSFETs Mn1 and Mn2 are connected to each other and to the negative power supply terminal VSS via the constant current source 3621. A control terminal of the N-type MOSFET Mn3 is configured to receive the reference signal REF, and a second terminal is connected to the negative power supply terminal VSS through the constant current source 3621. The control terminal of the P-type MOSFET Mp7 is connected to the second terminal of the P-type MOSFET Mp6, the first terminal is connected to the positive power supply terminal VDD, and the second terminal is connected to the negative power supply terminal VSS through the constant current source 3622. An intermediate node of the P-type MOSFET Mp7 and the constant current source 2622 is used to provide the third switching signal SW 3.
Similarly, in the control unit 362, when the first difference signal S1 and the second difference signal S2 are both smaller than the reference signal REF, the third switch signal SW3 is asserted, the first switch 230 is turned on, the second switch 240 is turned off, and when the input differential signal is a small signal, the first differential input stage 210 operates, thereby improving the accuracy of the differential amplifier differential input circuit. When one of the first difference signal S1 and the second difference signal S2 is greater than the reference signal REF, the output of the P-type MOSFET Mp7 is inverted, the third switch signal SW3 is inactive, the first switch 230 is turned off, the second switch 240 is turned on, and when the differential input signal is a large signal, the second differential input stage 220 operates to prevent the transistor pair in the first differential input stage from operating in a biased state for a long time and prevent the variation of the device characteristics of the transistor pair in the differential input circuit due to the long-time asymmetric operation of the transistor pair, which is beneficial to reducing the input offset voltage of the differential amplifier and improving the accuracy of the differential amplifier.
Further, according to another aspect of the present invention, there is provided a differential amplifier including: the differential input circuit can solve the problem of device characteristic change of a transistor pair in the differential input circuit caused by long-time asymmetric work of a main input stage transistor pair, is beneficial to reducing the input offset voltage of the differential amplifier and improving the precision of the differential amplifier.
In summary, in the differential input circuit, the control method of the differential input circuit, and the differential amplifier provided in the embodiments of the present invention, the differential input circuit includes: the first differential input stage is connected between the positive power supply end and the negative power supply end in series with the first switch; the second differential input stage is connected between the positive power supply end and the negative power supply end in series with the second switch; and the differential detection circuit is used for switching on one of the first switch and the second switch according to the first input signal and the second input signal, wherein positive input ends of the first differential input stage and the second differential input stage receive the first input signal, negative input ends of the first differential input stage and the second differential input stage receive the second input signal, the size of a differential transistor pair in the first differential input stage is different from that of a differential transistor pair in the second differential input stage, the increase of input offset voltage caused by asymmetry of the transistor pair of a single input stage under long-time large differential signal operation can be avoided, and the precision of the amplifier is reduced.
Furthermore, the size of the differential transistor pair in the first differential input stage is larger than that of the differential transistor pair in the second differential input stage, when the differential input signal is a small signal, the first differential input stage operates, and when the differential input signal is a large signal, the second differential input stage operates, so that the transistor pair in the first differential input stage can be prevented from operating in a bias state for a long time under the action of the differential input signal of the large signal, the change of the device characteristics of the transistor pair in the differential input circuit caused by the long-time asymmetric operation of the transistor pair can be avoided, the accuracy of the differential amplifier can be ensured, and the input offset voltage of the differential amplifier can be reduced.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.
Claims (16)
1. A differential input circuit, comprising:
the first differential input stage is connected between the positive power supply end and the negative power supply end in series with the first switch;
the second differential input stage is connected between the positive power supply end and the negative power supply end in series with the second switch; and
a differential detection circuit for turning on one of the first switch and the second switch in accordance with a first input signal and a second input signal,
the positive input ends of the first differential input stage and the second differential input stage receive the first input signal, the negative input ends of the first differential input stage and the second differential input stage receive the second input signal, and the size of the differential transistor pair in the first differential input stage is different from the size of the differential transistor pair in the second differential input stage.
2. The differential input circuit of claim 1, wherein the differential detection circuit compares the first input signal and the second input signal to obtain a difference signal therebetween, compares the difference signal with a reference signal, and turns on one of the first switch and the second switch according to the comparison result.
3. The differential input circuit of claim 2, wherein the size of the differential transistor pair in the first differential input stage is substantially larger than the size of the differential transistor pair in the second differential input stage,
wherein the differential detection circuit turns on the first switch when the difference signal is less than the reference signal, an
When the difference signal is greater than or equal to the reference signal, the differential detection circuit turns on the second switch.
4. The differential input circuit of claim 3, wherein the differential detection circuit comprises:
the amplifying unit is used for obtaining a first difference signal and a second difference signal according to the first input signal and the second input signal; and
and the control unit is used for comparing the first difference signal and the second difference signal with the reference signal and conducting one of the first switch and the second switch according to a comparison result.
5. The differential input circuit according to claim 4, wherein the amplification unit includes a first differential amplification circuit and a second differential amplification circuit,
the first differential amplifier circuit includes a first inverting terminal, a first non-inverting terminal, and a first output terminal, the first inverting terminal receives the first input signal, the first non-inverting terminal receives the second input signal, the first output terminal is configured to output the first difference signal,
the second differential amplifying circuit includes a second inverting terminal, a second non-inverting terminal, and a second output terminal, the second inverting terminal receives the second input signal, the second non-inverting terminal receives the first input signal, and the second output terminal is configured to output the second difference signal.
6. The differential input circuit of claim 4, wherein the first switch and the second switch are of the same conductivity type,
and the control unit generates a first switching signal and a second switching signal which are opposite in phase according to the comparison result, and the first switching signal and the second switching signal respectively control the on and off of the first switch and the second switch.
7. The differential input circuit of claim 6, wherein the control unit comprises:
the grid electrodes of the first transistor and the second transistor respectively receive the first difference signal and the second difference signal, the source electrodes of the first transistor and the second transistor are connected with the negative power supply end through a second constant current source, and the drain electrodes of the first transistor and the second transistor are connected with each other;
a third transistor, a gate of which is used for receiving the reference signal, and a source of which is connected with a negative power supply terminal through the second constant current source;
a fourth transistor and a fifth transistor which form a current mirror, a power supply terminal of the current mirror is connected with a positive power supply terminal,
a drain of the fourth transistor is connected to drains of the first transistor and the second transistor,
a drain of the fifth transistor is connected to a drain of the third transistor;
a sixth transistor and a third constant current source connected in series between the positive power supply terminal and the negative power supply terminal, a gate of the sixth transistor being connected to an intermediate node of the third transistor and the fifth transistor, a drain of the sixth transistor being used for providing the first switching signal; and
and the input end of the inverter is connected to the drain electrode of the sixth transistor to receive the first switching signal, and the output end of the inverter is used for providing the second switching signal.
8. The differential input circuit of claim 7, wherein the first transistor, the second transistor, and the third transistor are each an N-type metal oxide semiconductor field effect transistor,
the fourth transistor, the fifth transistor and the sixth transistor are P-type metal oxide semiconductor field effect transistors respectively.
9. The differential input circuit of claim 4, wherein the first switch and the second switch are of different conductivity types,
the control unit generates a third switching signal that turns on one of the first switch and the second switch and turns off the other of the first switch and the second switch according to the comparison result.
10. The differential input circuit of claim 9, wherein the control unit comprises:
a seventh transistor and an eighth transistor, gates of which respectively receive the first difference signal and the second difference signal, sources of which are connected to a negative power supply terminal through a fourth constant current source, and drains of which are connected to each other;
a ninth transistor, a gate of which is used for receiving the reference signal, and a source of which is connected with a negative power supply terminal through a second constant current source;
a tenth transistor and an eleventh transistor which constitute a current mirror having a power supply terminal connected to a positive power supply terminal,
a drain of the tenth transistor is connected to drains of the seventh transistor and the eighth transistor,
a drain of the eleventh transistor is connected to a drain of the ninth transistor;
a twelfth transistor and a fifth constant current source connected in series between the positive power supply terminal and the negative power supply terminal, a gate of the twelfth transistor being connected to a middle node of the eleventh transistor and the ninth transistor, and a drain of the twelfth transistor being used for providing the third switching signal.
11. The differential input circuit of claim 10, wherein the seventh transistor, the eighth transistor, and the ninth transistor are each an N-type metal oxide semiconductor field effect transistor,
the tenth transistor, the eleventh transistor, and the twelfth transistor are P-type metal oxide semiconductor field effect transistors, respectively.
12. The differential input circuit of claim 1, wherein the first switch and the second switch are selected from one of an electromechanical switch, a metal oxide semiconductor field effect transistor, a complementary metal oxide semiconductor, or a bipolar transistor.
13. A control method of the differential input circuit according to any one of claims 1 to 12, characterized in that the control method comprises:
comparing the first input signal with the second input signal to obtain a difference signal of the first input signal and the second input signal;
and comparing the difference signal with a reference signal, and turning on one of the first switch and the second switch according to a comparison result.
14. The method of claim 13, wherein the size of the differential transistor pair in the first differential input stage is larger than the size of the differential transistor pair in the second differential input stage, wherein comparing the difference signal with a reference signal, and wherein turning on one of the first switch and the second switch according to the comparison comprises:
when the difference signal is less than the reference signal, turning on the first switch, an
And when the difference signal is greater than or equal to the reference signal, turning on the second switch.
15. The method of claim 14, wherein comparing the difference signal to a reference signal and turning on one of the first switch and the second switch based on the comparison further comprises:
obtaining a first difference signal and a second difference signal according to the first input signal and the second input signal;
the first switch is turned on when both the first difference signal and the second difference signal are less than the reference signal, and the second switch is turned on when one of the first difference signal and the second difference signal is greater than/equal to the reference signal.
16. A differential amplifier comprising the differential input circuit of any of claims 1-12.
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| CN101411059A (en) * | 2006-03-23 | 2009-04-15 | Nxp股份有限公司 | Converter with parallel coupled differential input pairs |
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