JP2003142962A - Differential amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that large currents need to be supplied to differential input transistors, a differential amplifier circuit needs to be formed with high accuracy, and the gate width W and gate length L of the transistors of the differential pair should be made large to shorten the convergence time of an output signal. SOLUTION: When transistors 2 and 5 for a switch are turned on, large currents flow to the differential input transistors 3 and 6, so the differential output voltage reaches a target voltage in a short time. When the transistors 2 and 5 are turned off, the differential output voltage converges only through the operation of differential input transistors 4 and 7 having long gate length L for reducing variance in offset, and hence variance among differential output voltages of a plurality of differential amplifier circuits is reducible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier circuit which reduces offset variation in a device (for example, a liquid crystal driving device) having a plurality of DACs incorporated therein.

[0002]

2. Description of the Related Art A conventional differential amplifier circuit is constructed as shown in FIGS. As shown in FIG. 5, a conventional differential amplifier circuit has a drain of a P-type transistor 20 having a gate applied with a bias voltage, a source of a P-type transistor 21 having a first input signal IN1 as a gate, and a second input. The source of the P-type transistor 22 having the gate of the signal IN2 is connected in parallel, the drain of the P-type transistor 21 is connected to the gate and drain of the N-type transistor 23, and the gate of the N-type transistor 24, and the P-type transistor is connected. The drain of the transistor 22 is connected to the drain of the N-type transistor 24, and a differential output signal is output from the connection point between the drain of the P-type transistor 22 and the drain of the N-type transistor 24.

According to this, the first input signal I shown in FIG.
When N1 and the second input signal IN2 are input, the differential output signal shown in FIG. 6 can be obtained at the drain of the N-type transistor 24.

In a circuit in which a plurality of differential amplifier circuits having the above-mentioned configuration are arranged, variations in output voltage offset of differential output signals due to variations in dimensions of transistor gate width W and transistor gate length L become large. .

[0005]

In such a conventional configuration, in order to reduce the offset variation of the differential output voltage between the plurality of differential amplifier circuits and shorten the convergence time, the P-type transistor 21 is used. , 22 the transistor gate width W and the transistor gate length L must be increased.

The present invention solves the above-mentioned conventional problems and provides a differential amplifier circuit in which the convergence time of differential output signals is shortened and the variation in the differential output voltage of a plurality of differential amplifier circuits is reduced. The purpose is to provide.

[0007]

SUMMARY OF THE INVENTION A differential amplifier circuit of the present invention is a switch in which a differential input signal is connected to the gates of a plurality of transistors, and one of the differential input transistors is connected in series with a switch control signal as a gate. The switching transistor is connected, and the switching transistor is turned off during the rising of the output signal.

[0008]

A differential amplifier circuit according to claim 1 of the present invention connects a first input signal to input circuits of first and second transistors having different gate lengths, and One of the output circuits of the first transistor having the smaller gate length is connected to one side of the power source through the output circuit of the third transistor controlled by the switch control signal,
One of the output circuits of the second transistor having the larger gate length of the first and second transistors is connected to one side of the power supply without passing through the third transistor, and the second input signal has a different gate length. The output of the sixth transistor connected to the input circuits of the fourth and fifth transistors, and one of the output circuits of the fourth transistors having the smaller gate length among the fourth and fifth transistors is controlled by the switch control signal. Connected to one side of the power source via a circuit, and connecting one of the output circuits of the fifth and the fifth transistors having the larger gate length among the fourth and fifth transistors without passing through the sixth transistor. To the other side of the output circuit of the first and second transistors, or the fourth and fifth transistors by differentially amplifying the first and second input signals by the first, second, fourth and fifth transistors. In the course of rising of the output signal taken out from the other output circuit of data, characterized by being configured to turn off the third, sixth transistor.

According to this structure, the switching transistor is turned on in the initial stage of the operation of the differential amplifier circuit, and the first and fourth transistors having a small gate length for allowing a large current to flow are operated, whereby a short period of time is achieved. Reached near the differential output voltage,
By turning off the third and sixth transistors after a certain period of time, no current flows in the first and fourth transistors connected in series and having a small gate length for flowing a large current, which causes offset variation. The differential output voltage quickly reaches the target voltage only by the operation of the second and fifth transistors having a large gate length to reduce the gate length.

A differential amplifier circuit according to claim 2 of the present invention is
The output drive control circuit according to claim 1, wherein an output drive control circuit that detects that the input signal level has reached a specified value and inverts the output level is provided, and the output circuit of the first and second transistors is provided at the input of the output drive control circuit. Of the output circuit of the other of the output circuits of the fourth and fifth transistors,
The output driving control circuit is configured to control the third and sixth transistors.

Hereinafter, each embodiment of the present invention will be described with reference to FIGS.
It will be described based on. (Embodiment 1) FIGS. 1 and 2 show (Embodiment 1) of the present invention.

1, 2, 3, 4, 5, 5, 6 and 7 are P-type transistors, and 8 and 9 are N-type transistors. The drain of the P-type transistor 1 having the gate of the bias voltage is connected to the drains of the P-type transistors 2 and 5 having the gate of the switch control signal.
, The source of the P-type transistor 4 having the gate of the first input signal IN1 and the source of the P-type transistor 7 having the gate of the second input signal IN2 are connected in parallel.

The drain of the P-type transistor 2 is connected to the source of the P-type transistor 3 having the first input signal IN1 as its gate, and the drain of the P-type transistor 5 and the P-type transistor 6 having its second input signal IN2 as its gate are connected. Connect with the source of.

The drains of the P-type transistors 3 and 4 are connected to N
The gate and drain of the N-type transistor 8 and the gate of the N-type transistor 9 are connected. The drains of the P-type transistors 6 and 7 are connected to the drain of the N-type transistor 9,
A differential output signal is output from the drain of the N-type transistor 9.

In the differential amplifier circuit having such a configuration, the bias voltage is applied to the gate of the P-type transistor 1 and the L-level switch control signal SW is connected to the gates of the P-type transistors 2 and 5, and The first input signal IN1 is input to the gates of the P-type transistor 3 having a small gate length for flowing a large current and the P-type transistor 4 having a large gate length for reducing the offset variation, and the second input signal I
When N2 is input to the gates of the P-type transistor 6 having a small gate length for allowing a large current to flow and the P-type transistor 7 having a large gate length for reducing the offset variation, the current is supplied to the P-type transistors 3, 4, 6, 7. And the differential output signal tries to reach the target voltage in a short time.

Then, the P-type transistors 2 and 5 are turned off by changing the switch control signal SW from the L level to the H level after a lapse of a certain time after the differential amplifier circuit starts operating.
To do. With the P-type transistors 2 and 5 turned off,
Since no current flows in the P-type transistors 3 and 6 having a small gate length for allowing a large current to flow, the differential output signal is only operated by the P-type transistors 4 and 7 having a large gate length in order to reduce offset variation. It converges to the target voltage.
FIG. 2 shows a signal waveform of the differential amplifier circuit of this embodiment.

(Second Embodiment) FIGS. 3 and 4 show a second embodiment of the present invention. FIG. 3 shows a differential amplifier circuit of (Embodiment 2), and components having the same operations as those of FIG. 1 showing (Embodiment 1) will be described with the same reference numerals.

The output drive control circuit 10 detects that the input signal level has reached the specified value and inverts the output level. The differential output signal OUT is applied to the input of the output drive control circuit 10. The output signal of the output drive control circuit 10 is P
It is applied to the gates of the type transistors 2 and 5. FIG. 4 shows a signal waveform of the differential amplifier circuit of this embodiment.

According to this structure, a differential input signal is connected to a plurality of P-type transistors, and a P-type transistor for switching is connected in series to a P-type transistor having a small gate length for flowing a large current. By configuring the differential amplifier circuit, it is possible to converge the differential output voltage at high speed and reduce variations in the differential output voltage among the plurality of differential amplifier circuits.

[0020]

As described above, according to the differential amplifier circuit of the present invention, the first input signal is connected to the input circuits of the first and second transistors having different gate lengths, and one of the first and second transistors is connected. One of the output circuits of the first transistor having the smaller gate length is connected to one side of the power supply through the output circuit of the third transistor controlled by the switch control signal, and the gate of the first and second transistors is connected. One of the output circuits of the longer second transistor is connected to one side of the power supply without passing through the third transistor, and the second input signal is input to the input circuits of the fourth and fifth transistors having different gate lengths. One of the output circuits of the fourth transistor having the smaller gate length of the fourth and fifth transistors is connected to the power source via the output circuit of the sixth transistor controlled by the switch control signal. One of the output circuits of the fifth transistor having the larger gate length among the fourth and fifth transistors is connected to one side of the power source without passing through the sixth transistor. , The second, fourth and fifth transistors differentially amplify the first and second input signals and take them out from the other output circuit of the first and second transistors or the other output circuit of the fourth and fifth transistors. Since the third and sixth transistors are turned off during the rising of the output signal, the first and fourth transistors having a small gate length for flowing a large current are initially used during the operation of the differential amplifier circuit. Since a large current can flow, the differential output voltage can reach near the target voltage in a short time. After that, when the differential output voltage converges, the third and sixth transistors for switching are turned off. By and,
A differential amplifier circuit capable of converging the differential output voltage to the target voltage can be realized only by the operation of the second and fifth transistors having a large gate length for reducing the offset variation.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a differential amplifier circuit according to a first embodiment of the present invention.

FIG. 2 is a signal waveform diagram of the same embodiment.

FIG. 3 is a circuit diagram of a differential amplifier circuit according to (Embodiment 1) of the present invention.

FIG. 4 is a signal waveform diagram of the same embodiment.

FIG. 5 is a circuit diagram of a conventional differential amplifier circuit.

FIG. 6 is a signal waveform diagram of the differential amplifier circuit of the same embodiment.

[Explanation of symbols]

IN1 First input signal IN2 Second input signal 1 P-type transistor 2 P-type transistor (third transistor) 3 P-type transistor with smaller gate length (first transistor) 4 P-type transistor with larger gate length (first 2 transistors) 5 P-type transistor (sixth transistor) 6 P-type transistor with the smaller gate length (fourth transistor) 7 P-type transistor with the larger gate length (fifth transistor) 8 N-type transistor 9 N-type transistor 10 Output drive control circuit SW switch control signal

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5J066 AA01 AA12 CA11 CA13 CA65                       FA15 HA09 HA17 HA39 KA06                       KA09 MA19 MA21 ND04 ND14                       ND22 ND23 PD01 TA06                 5J500 AA01 AA12 AC11 AC13 AC65                       AF15 AH09 AH17 AH39 AK06                       AK09 AM19 AM21 AT06 DN04                       DN14 DN22 DN23 DP01

Claims (2)

[Claims] 1. A first input signal is connected to input circuits of first and second transistors having different gate lengths, and one of output circuits of first transistors having the smaller gate length of the first and second transistors is connected. Is connected to one side of the power supply through the output circuit of the third transistor controlled by the switch control signal, and one of the output circuits of the second transistors having the larger gate length of the first and second transistors is connected. The second input signal is connected to one side of the power supply without passing through the third transistor, and the second input signal is connected to the input circuits of the fourth and fifth transistors having different gate lengths. One of the output circuits of the smaller fourth transistors is connected to one side of the power source through the output circuit of the sixth transistor controlled by the switch control signal, and the fourth and fifth transistors are connected. One of the output circuits of the fifth transistor having the larger gate length is connected to one side of the power supply without passing through the sixth transistor, and the first, second, fourth and fifth transistors are used to The first and second input signals are differentially amplified and output from the other of the output circuits of the first and second transistors or the other of the output circuits of the fourth and fifth transistors. A differential amplifier circuit configured to turn off 6 transistors. 2. An output drive control circuit for inverting an output level upon detecting that an input signal level has reached a specified value, wherein the output drive control circuit is provided with an input circuit for the first and second transistors. 3. The differential according to claim 1, wherein an output signal taken out from the other of the output circuits of the fourth and fifth transistors is applied to control the third and sixth transistors by the output of the output drive control circuit. Amplifier circuit.