JP3498451B2 - Semiconductor storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a differential amplifier that amplifies data read from a memory cell.

[0002]

2. Description of the Related Art In a semiconductor memory device, an amplifier circuit is provided between a data line for transmitting data from a memory cell and an output circuit in order to reduce the time required for reading data from the memory cell. Is speeding up.

The circuit diagram shown in FIG. 3 shows a conventional current mirror type differential amplifier. P-channel transistors (hereinafter referred to as PchTr) 501 and 502 in FIG. 3 are load transistors, and the gate of the PchTr 501 is connected to its drain to serve as a constant current source. Pc
The gate of hTr502 is connected to the drain of PchTr501, and positive feedback is applied to PchTr502. N-channel transistors (hereinafter referred to as NchTr) 503 and 504 are input transistors. Nch
Tr40 is an operation control transistor which is also a constant current source, and controls the operation / non-operation of the circuit of FIG. 3 by the activation signal SA1.

The operation of FIG. 3 will be described. Now, Di in FIG.
VDD-ΔV is applied to n, VDD voltage is applied to bDin (that is, the input data is Low), and NchTr4
It is assumed that 0 is ON (operating state). Here, VDD is the power supply potential, VSS is the ground potential, and ΔV is the potential difference between Din and bDin generated by the data read from the memory cell. At this time, NchTr 503 and 504 are O
In the N state, both nodes a and b drop in voltage toward the VSS side. PchTr501 is a constant current source and is always on,
The PchTr 502 receives the potential of the node a and turns on. However, the current flowing through the NchTr 504 is smaller than that of the NchTr 503 because the voltage applied to the gate thereof is lower than that of the NchTr 503 by ΔV. Therefore, the voltage of the node b becomes higher than that of the node a, and the voltage of the node a is fed back to the PchTR 502. Therefore, the node b is further raised to the VDD side. So finally Do
High data is output to ut, and Low data is transmitted to the output circuit via an inverter or the like.

In FIG. 3, VDD is input to Din and VDD-ΔV is input to bDin (that is, input data is High).
In the case of h), the NchTrs 503 and 504 are in the ON state and the nodes a and b start to drop to the VSS side as in the case described above, but this time, the current flowing through the NchTr 503 becomes smaller than that of the NchTr 504. For this reason,
The voltage of node a becomes higher than that of node b, and node a
The voltage of 2 reduces the current flowing through the PchTr 502, so that the node b is further lowered to the VSS side. Therefore, the Low data is finally output, and the High data is transmitted to the output circuit via the inverter or the like.

FIG. 4 is a circuit diagram showing a double-ended differential amplifier as another example of the conventional differential amplifier. This uses a pair of current mirror type differential amplifiers and is a technique disclosed in Japanese Patent Laid-Open No. 59-139193. The circuit 60 and the circuit 70 of FIG. 4 are current mirror type differential amplifiers, and the NchTr 40 performs the same function as that of FIG. The circuit of FIG. 4 is operationally the same as the current mirror type differential amplifier, but is characterized in that complementary output signals can be produced.

FIG. 5 shows a circuit diagram of a positive feedback load control type differential amplifier (hereinafter referred to as a positive feedback type differential amplifier). This technique is a technique disclosed in Japanese Examined Patent Publication No. 57-54878. The operation of this circuit is as follows.

VDD in FIG. 5 and VDD in bVin
It is assumed that a voltage of −ΔV is applied (that is, High data is input). By this, NchTr 803, 804
Turns on. Therefore, the voltages of the nodes c and d in FIG. 5 start to drop to the VSS side. However, NchTr803
Since the current flowing through is lower than that of the NchTr 804 (the gate voltage is lower by ΔV), the voltage of the node c becomes higher than the voltage of the node d. The voltage of the node c is PchTr802, and the voltage of the node d is PchTr80.
Each one will be returned. As a result, PchTr8
The current flowing through 02 becomes smaller, and the node d becomes more VSS.
The voltage drops to the side, the current flowing through the PchTr 801 increases in response to this, and the voltage of the node c increases to the VDD side. Repeating the above, finally Lo to Dout
High is output to w and bDout. With such feedback, the positive feedback differential amplifier is
With high amplification, the period during which the through current flows is very short and the current consumption is low.

The block diagram shown in FIG. 6 is a combination of a conventional double end current mirror type differential amplifier and a positive feedback type differential amplifier and is disclosed in Japanese Patent Laid-Open Nos. 2-276094 and 6-12879. It is a technology. This is configured such that a minute potential difference is first amplified with high sensitivity by a double end current mirror type differential amplifier, and then is amplified at high speed by a crossing type differential amplifier.

[0010]

The conventional differential amplifier has the following advantages and disadvantages.

The current mirror type differential amplifier has the advantages of high sensitivity and wide input level, but has one output, so it is necessary to create a complementary signal by an external circuit and input it to the output circuit. Furthermore, since one of the load transistors is a constant current source, a through current flows and the current consumption increases.
There is a disadvantage.

The double-ended current mirror type has the advantages of the current mirror type and can generate complementary signals, but has the disadvantage of increasing the current consumption due to the flow of through current.

The positive feedback type differential amplifier has the advantages of high speed and high amplification and a small through current, but has the disadvantage of having a narrow input level when the potential difference between input signals is very small.

The combination of the double end current mirror type and the positive feedback type has the advantages of the double end current mirror type and the positive feedback type, but has the disadvantage of increasing the layout area because the number of elements increases.

Therefore, an object of the present invention is to provide a differential amplifier which has the advantages of the above-mentioned differential amplifier but can overcome the disadvantages thereof.

[0016]

A semiconductor memory device of the present invention is a memory cell array in which a plurality of memory cells are arranged and data read from the memory cells is amplified by a differential amplifier via a data line, In a semiconductor memory device configured to transmit to an output circuit, the differential amplifier is configured by symmetrically arranging two sets of current mirror type differential amplifiers, and a load element serving as a constant current source of the two sets of current mirror type amplifiers. By providing the operation mode switching circuit for controlling the current supply to the current mirror type differential amplifier, the current mirror type differential amplifier operates as a positive feedback load control type differential amplifier, and the mode switching signal for controlling the operation mode switching circuit is It is characterized in that it is activated after the amplifier activation signal.

In another semiconductor memory device of the present invention, a memory cell array in which a plurality of memory cells are arranged and data read from the memory cells are amplified by a differential amplifier via a data line, and an output circuit is provided. In a semiconductor memory device configured to transmit to a load element serving as a constant current source of the two sets of current mirror type differential amplifiers, the differential amplifier is configured to be symmetrical with respect to two sets of current mirror type differential amplifiers. By providing the operation mode switching circuit for controlling the current supply, the current mirror type differential amplifier operates as a positive feedback load control type differential amplifier, the output signal of the differential amplifier is detected, and the mode switching signal is activated. It is characterized in that it is provided with an output signal detection circuit for converting the signal into a signal.

[0018]

The SA2 is in the inactive state at the initial stage of operation, so that the SA2 operates as a double end current mirror type. When SA2 is activated after the output is output, it operates as a positive feedback type. When the output signal detection circuit is provided, the output signal detection circuit detects that a signal appears at the output of the differential amplifier and controls the operation mode switching circuit.
The double end current mirror type operation and the positive feedback type operation can be automatically switched at an appropriate timing.

[0019]

1 is a circuit diagram showing an embodiment of a semiconductor memory device of the present invention. In the figure, a circuit 10 is an operation mode switching circuit, circuits 20 and 30 are current mirror type differential amplifiers, and a transistor 40 is an operation control transistor which is also a constant current source.

Circuit 2 which is a current mirror type differential amplifier
0 is composed of input transistors 203 and 204 connected in series to the drains of the load transistors 201 and 202, respectively, and the gates of the load transistors 201 and 202 have 20 gates.
2 connected to the drain. Similarly, the circuit 30 similarly includes each of the load transistors 301 and 302 and the input transistor 3.
03 and 304 are connected in series, and the load transistor 30
The gates of 1,302 are connected to the drain of 301.
The gates of the input transistors 203 and 303 are commonly connected, and the gates of 204 and 304 are commonly connected to provide the same input. Two outputs, one from the drains of the PchTrs 201 and 302 and one from the drains of the PchTrs 202 and 301, have a complementary relationship. The sources of the input transistors are all commonly connected, and VSS is connected through the drain / source path of the operation control transistor 40.
It is connected to the. SA1 is input to the gate of the operation control transistor 40. The sources of the load transistors 201 and 302 are directly connected to VDD.
Reference numerals 2, 301 are connected to VDD via the drain / source paths of the PchTrs 101, 102 constituting the operation mode switching circuit. PchTr 101, 102
SA2 is input to the gate of.

The operation of FIG. 1 will be described. First, when the activation signal SA1 is Low, the circuit of FIG. 1 does not operate. SA1
When the read operation of the memory cell is started, goes to High level to activate the circuit of FIG. At this time, the mode switching signal SA2 is at a low level to deactivate the operation mode switching circuit 10 (that is, PchTr101, 1).
Both 02 are turned on. In this state, the circuit of FIG. 1 operates as a double end current mirror type differential amplifier. Next, when data is output to the output of the circuit of FIG. 1, SA2 is set to High level. Then, the PchTrs 101, 10 forming the operation mode switching circuit 10
Both 2 are turned off. Therefore, PchTr101
Current does not flow through the path of the load transistor 202 and the input transistor 204 connected in series with the load transistor 301 and the input transistor 303 connected in series with the PchTr 102. Therefore, the circuit of FIG. 1 is substantially the same as the load transistors 201 and 302 and the input transistor 2.
03, 304, and the gate of the load transistor 201 and the gate of the load transistor 302 are connected to their respective drains to form a positive feedback differential amplifier.

FIG. 2 is a graph showing the operating state of the circuit of FIG. Din, which is also output data from the memory cell, is divided into High and Low from the start of reading, but the differential amplifier operation signal SA1 is activated (High level) when the difference becomes a certain amount (50 mV in FIG. 2, for example). It begins to amplify the input. At this time, it operates as a high-amplification double-end current mirror type differential amplifier. When the operation mode switching signal SA2 is activated after Dout is determined, high-speed amplification is started as the positive feedback differential amplifier, so that the potential difference of Dout rapidly increases. The current consumption is lower than that of the conventional double end current mirror type because the through current stops flowing when SA2 is activated.

FIG. 7 is a circuit diagram showing another embodiment of the semiconductor memory device of the present invention. This is a case where the operation mode switching circuit in FIG. 7 is configured by one PchTr 103.
The operation of FIG. 7 is the same as that of FIG. If the current drive capability of the PchTr 103 is necessary and sufficient, it is a circuit with a small number of element configurations.

FIG. 8 is a circuit diagram showing another embodiment of the semiconductor memory device of the present invention, which shows an example in which the operation mode switching circuit is controlled by the output detection circuit. A circuit 90 in FIG. 8 is an output signal detection circuit, and a circuit 10 is an operation mode switching circuit. The input of the output signal detection circuit 90 is connected to the output of the differential amplifier, and the output of the output signal detection circuit 90 is the mode switching signal SA2.

Explaining the operation of FIG. 8, the data to be amplified is input to the inputs Din and bDin of the differential amplifier, and at first, the double end current mirror type is used to perform highly sensitive amplification. The amplified signal appears at the output and the output Do
When the potentials of ut and bDout decrease, the output signal detection circuit detects it and activates SA2 (in this case, High level). Thereby, the operation mode switching circuit 10
Is activated and the PchTr 104 is turned off, so that the operation of the double end current mirror type is switched to the operation of the positive feedback type. When the output signal detection circuit is provided in this way, the operation mode switching circuit can always be activated at an appropriate timing, and a high-speed, low-current-consumption differential circuit that does not malfunction even with fluctuations in process parameters and power supply voltage An amplifier can be obtained.

Although the above-mentioned differential amplifier is composed of CMOS, it is not limited to this, and the input transistors 203, 204, 303 and 304 may be composed of bipolar transistors or the like.

[0027]

As is apparent from the above description, by using the present invention, high speed, high sensitivity, high amplification, low current consumption,
A space-saving differential amplifier can be configured, and when an output signal detection circuit is further provided, it is possible to obtain a highly stable differential amplifier that does not malfunction even with variations in process parameters and power supply voltage.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a graph showing an operating state of the semiconductor memory device of the present invention.

FIG. 3 is a circuit diagram showing an example of a current mirror type differential amplifier of a conventional semiconductor memory device.

FIG. 4 is a circuit diagram showing an example of a double end current mirror type differential amplifier of a conventional semiconductor memory device.

FIG. 5 is a circuit diagram showing an example of a positive feedback type differential amplifier of a conventional semiconductor memory device.

FIG. 6 is a block diagram showing an example in which a double-end current mirror type differential amplifier and a positive feedback type differential amplifier of a conventional semiconductor memory device are connected in series.

FIG. 7 is a circuit diagram showing another embodiment of the semiconductor memory device of the present invention.

FIG. 8 is a circuit diagram showing another embodiment of the semiconductor memory device of the present invention.

[Explanation of symbols]

10 ... Mode switching circuit 101 ・ ・ ・ PchTr 102 ・ ・ ・ PchTr 103 ・ ・ ・ PchTr 104 ・ ・ ・ PchTr 20, 30, 60, 70 ・ ・ ・ Current mirror type differential amplifier 201, 202, 301, 302・ ・ ・ Load transistors (PchTr) 203, 204, 303, 304 ・ ・ ・ Input transistors (NchTr) 40 ・ ・ ・ Operation control transistor 90 ・ ・ ・ Output signal detection circuit SA1 ・ ・ ・ Differential amplifier activation signal SA2 ... Mode switching signals

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G11C 11/41-11/419

Claims (3)

(57) [Claims] 1. A semiconductor memory device having a memory cell array in which a plurality of memory cells are arranged, and data read from the memory cells is amplified by a differential amplifier via a data line and transmitted to an output circuit. And the differential amplifier is
A double-ended amplifier consisting of a pair of Tomiller differential amplifiers
Decurrent mirror type differential amplifier and the double end
The load element and the electric current which are the constant current source of the non-mirror type differential amplifier.
And an operation mode switching circuit provided between the source potential and the source potential.
When the operation mode switching circuit is inactive, the double error
And operates as a current mirror type differential amplifier.
Positive feedback load control differential increase when the mode switching circuit is active
A semiconductor memory device having a differential amplifier that operates as a width device. 2. The semiconductor memory device according to claim 1, wherein the mode switching signal for controlling the operation mode switching circuit is activated after the differential amplifier activation signal. 3. The semiconductor memory device according to claim 1, further comprising an output signal detection circuit for detecting an output signal of the differential amplifier and activating the mode switching signal.