JPH08147976A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To provide a semiconductor integrated circuit increasing an operation margin and stably sensing/amplifying a minute difference voltage signal at a high speed by connecting a capacitor between an output end and a low potential power source end of an inverter of a current drive latch circuit. CONSTITUTION: The output end and the low potential power source end of a pair of inverters consisting of PMOS transistors 20a, 20b and NMOS transistors 22a, 22b of a current drive latch circuit 12 are precharged to the same high potential by a precharge circuit 16. Thereafter, charges precharged on the low potential power source end of a pair of the inverters are discharged according to the potential of a pair of the minute difference voltage signals inputted to a current drive circuit 14 through a data line and an inversion data line. Further, the potential of the output ends through capacitors 18a, 18b are dropped by capacity coupling according to the potential of the low potential power source end, too. Thus, the operation margin of the circuit 12 is enlarged, and a malfunction is eliminated even in any minute difference voltage signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit which senses and amplifies a minute difference voltage signal at high speed, and more specifically, detects any minute difference voltage signal at high speed without malfunctioning. The present invention relates to a current detection type sense amplifier that can be amplified.

[0002]

2. Description of the Related Art Various types of sense amplifiers have been conventionally used as semiconductor integrated circuits for detecting and amplifying minute differential voltage signals at high speed. Especially, DRAM, SRAM, C
Since sense amplifiers used for memories such as AM (content address memory) are required to operate at high speed and have high sensitivity, there are generally differential sense amplifiers that use complementary signals. There are two types of differential sense amplifiers: synchronous type and asynchronous type. Typical synchronous type differential sense amplifiers are latch type sense amplifiers and typical asynchronous type differential sense amplifiers. Has a current mirror type sense amplifier. Next, these differential sense amplifiers will be described using the illustrated example.

FIG. 5 is a configuration circuit diagram of an example of a latch type sense amplifier. The latch-type sense amplifier 50 includes a P-type MOS transistor (hereinafter referred to as PMOS) 52.
a and 52b and an N-type MOS transistor (hereinafter referred to as NMO
S) 54a, 54b, and the PMOS 52
a and NMOS 54a, and PMOS 52b and NM
Together with the OS 54b, it constitutes a CMOS inverter.
The input and output ends of these inverters are cross-coupled to each other, that is, the PMOS 52b and the NMOS 52b.
54b gate end and PMOS 52a and NMOS 54
The drain ends of a are short-circuited to each other and connected to the data line. Similarly, the gate ends of the PMOS 52a and the NMOS 54a and the drain ends of the PMOS 52b and the NMOS 54b are short-circuited to each other and connected to the inversion data line.
The source ends of the PMOSs 52a and 52b are both connected to the sense line, and the source ends of the NMOSs 54a and 54b are both connected to the inverted sense line.

Next, the operation of reading data using the latch type sense amplifier 50 will be described. First, the sense line is set to the low level and the inverted sense line is set to the high level, and then both the data line and the inverted data line are precharged to the same potential, for example, the power supply potential, and set to the floating high state. In this state, the PMOS 52a, 52b and N
Both the MOS 54a and 54b are in the off state. Then, the complementary data signals, that is, the data signal and the inverted data signal, are read from the predetermined memory cell to the data line and the inverted data line, respectively. At this time, the potentials of the data line and the inverted data line change according to the data signal and the inverted data signal, and if the high level and the low level are read as the data signal and the inverted data signal, the inverted data line is read. Is lower than the potential of the data line. Then, when the inversion sense line is gradually set to the low level, when the potential difference between the gate end (data line) and the source end (inversion sense line) of the NMOS 54b exceeds the threshold value, the NMOS 54b is turned on, The drain end, that is, the gate end of the PMOS 52a becomes low level. On the other hand, the potential difference between the gate end and the source end of the NMOS 54a is lower than that of the gate end of the NMOS 54b as compared with the potential of the gate end of the NMOS 54b. It is in an off state at the potential, and its drain end, that is, the gate end of the PMOS 52b becomes high level. Finally, the potentials of the sense line and the inverted sense line are
By setting the power supply potential and the ground potential respectively, P
Since the gate ends of the MOSs 52a and 52b are at the low level and the high level, respectively, and are in the ON state and the OFF state, respectively, the data signal and the inverted data signal which are the minute difference voltage signals read from the predetermined memory cell are
Amplify and latch to power supply potential and ground potential,
It can be output to the data line and the inverted data line, respectively.

Since the above-mentioned data line and inverted data line are commonly connected to the same bit of a plurality of word memories, a drive for outputting a data signal and an inverted data signal read from a memory cell, that is, a minute difference voltage signal. In the case of an element having a small capacity, the potentials of the data line and the inverted data line cannot be changed instantaneously. Therefore, the latch-type sense amplifier 50 may malfunction, that is, latch wrong data unless the operation is started after a sufficient potential difference is generated between the data line and the inverted data line. It is necessary to provide a time margin from the reading of the inverted data signal to the operation of the sense amplifier.

FIG. 6 is a circuit diagram showing an example of a current mirror type sense amplifier. The current mirror type sense amplifier 60 is a PMO which is a current mirror type load.
S62a, 62b and NMO for inputting a minute difference voltage signal
It has S64a and S64b and an NMOS 66 which serves as a constant current source. Here, the source ends of the PMOSs 62a and 62b are both connected to the power supply potential, their gate ends are short-circuited to each other and connected to the drain end of the PMOS 62a, and the data output line is connected to the drain end of the PMOS 62b. A data line and an inverted data line are input to the gate ends of the NMOSs 64a and 64b, the drain ends of the NMOSs 64a and 64b are connected to the drain ends of the PMOSs 62a and 62b, and the source ends of the NMOSs 64a and 64b are short-circuited to each other.
It is connected to the drain end of 66. Also, NMOS6
A sense line is connected to the gate end of 6, and its source end is connected to the ground potential.

In the current mirror type sense amplifier 60, the drain currents of the PMOSs 62a and 62b, which are loads, are made equal by applying the same bias voltage to the gate ends thereof. Further, the sense line is always at high level, and the NMOS 66 is always on. In addition, the precharge level of the data line and the inverted data line is at a high level slightly lower than the power supply potential in terms of the gain of the sense amplifier, and the data amplified at a high speed due to the minute voltage difference between the data line and the inverted data line is It is output to the data output line asynchronously. In the current mirror type sense amplifier 60 shown in FIG. 6, since the output logical level does not reach the power supply potential to the ground potential, it is usually configured in multiple stages or a level shifter or the like is used. In general, the current mirror type sense amplifiers 60 shown in FIG. 6 are generally used as a pair, and the data line and the inverted data line of the other sense amplifier are exchanged to obtain an inverted data output line.

Next, the operation of reading a data signal using the current mirror type sense amplifier 60 will be described. First, when the potential of the inverted data line starts to fall below the potential of the data line (precharge level), the NMOS 64b
Current driving capability g _m (which may be the drain current) decreases due to the decrease in the gate voltage, the potential of the data output line increases, and the potential of the drain end of the NMOS 66 decreases. The potential of the data line does not change, but the NMOS64
Since the gate-source voltage V _GS of a increases, its drain current increases and the potential at its drain end drops.
Therefore, the current drive capability g _m of the PMOS 62b is increased, the amplification is further accelerated, and the potential of the data output line is rapidly increased. Similarly, when the potential of the data line starts to fall below the potential of the inverted data line (precharge level), N
The current drive capability g _m of the MOS 64a is reduced, and the NMOS 6
Since the potential at the drain end of 4a rises, the PMOS 62
The current drivability g _{m of} b decreases. Also, the NMOS 66
Since the potential of the drain end of the
The gate-source voltage V _{GS of} 4b increases and its drain current increases. The potential of the data output line is PMOS 62
b, the NMOS 64b, and the current flowing through the NMOS 66 (the ratio of the current drivability g _m of each transistor or the resistance ratio), the potential thereof decreases. Further, when the potential of the data line drops, the amplification is accelerated.

This currant mirror type sense amplifier 60
Unlike the above-described latch type sense amplifier 50, since the input signal to the sense amplifier, that is, the data signal and the inverted data signal are not latched, there is no fear of malfunction. However, even if the amplitude of the input signal is small, there is an advantage that the current value of the NMOS 66, which is the constant current source, enables high-speed operation, but on the other hand, as described above, the current constantly flows and the current consumption becomes large. If bits are read at the same time, power consumption increases, which is not preferable.

In order to solve the above-mentioned drawbacks of the latch type sense amplifier 50 and the current mirror type sense amplifier 60, there is a current detection type sense amplifier disclosed in, for example, Japanese Patent Application Laid-Open No. 5-242686.

FIG. 7 is a circuit diagram of an example of the current detection type sense amplifier disclosed in the publication. The current detection type sense amplifier 70 includes PMOSs 20a, 20b and N.
Current-driven latch circuit 1 having MOS 22a, 22b
2 and a current drive circuit 14 having NMOSs 24a, 24b, 24c. Here, the PMOS 20a and the NMOS 22 which form the current drive type latch circuit 12
a and the PMOS 20b and the NMOS 22b are both C
A MOS inverter is configured, and the input terminal and the output terminal of the inverter are cross-coupled to each other, that is, the PMOS2.
0a and the gate end of the NMOS 22a and the PMOS 20b
The drain ends of the NMOS and the NMOS 22b are short-circuited to each other and connected to the data output line. Similarly, the gate ends of the PMOS 20b and the NMOS 22b and the drain ends of the PMOS 20a and the NMOS 22a are short-circuited to each other and connected to the inverted data output line. Also, the PMOS 20
The source ends of a and 20b are short-circuited and connected to the power supply potential. In addition, the NMOS 24a, 2 of the current drive circuit 14
The gate end of 4b is connected to the data line and the inverted data line, the drain end thereof is connected to the drain ends of the NMOSs 22a and 22b of the current drive type latch circuit 12, and the source ends thereof are short-circuited to each other to form the NMOS 24.
It is connected to the drain end of c. Also, the NMOS 24
The gate end of c is connected to the sense line, and its source end is connected to the ground potential. The NMOSs 22a, 22
The drain ends of b are contacts A and B, the source ends thereof are contacts a and b, respectively.
The following description will be made with the drain end of the contact c as the contact c.

Next, the operation of reading a data signal using the current detection type sense amplifier 70 will be described with reference to the graph shown in FIG. Note that in FIG. 8, the potential difference ΔV (= V _b −V _a ) between the contacts a and b at the sense amplifier operation start point is shown larger than it actually is, for ease of explanation. First, after setting the sense line to the low level, both the data line and the inverted data line are discharged to the same potential, for example, the ground potential to be in the floating low state, and the contacts A and B and the contacts a and b are both precharged to the power supply potential. The floating high state. In this state, PMOS 20a, 20b, NM
OS 22a, 22b and NMOS 24a, 24b, 2
All 4c are off. Then, the data signal and the inverted data signal are read from the predetermined memory cell to the data line and the inverted data line, respectively. At this time, the potentials of the data line and the inverted data line change according to the data signal and the inverted data signal, respectively. Then, when the sense line is set to the high level, the NMOS 24c is turned on, and the drain currents according to the potentials of the data line and the inverted data line flow in the NMOSs 24a and 24b, respectively, and the potentials of the drain ends (contact points a and b) of the NMOSs 24a and 24b. Is pulled out. For example, if the high level and the low level are read as the data signal and the inverted data signal, respectively, the potential of the drain end of the NMOS 24a drops earlier than that of the NMOS 24b, and the gate end (contact B) and the source end (contact a) of the NMOS 22a. When the potential difference between the two) exceeds the threshold value, the NMOS 22a is turned on, and the potential of the inverted data output line (contact A) becomes low level. When the contact A goes low, the NMOS
22b is turned off, so data output line (contact B)
The potential of is maintained at high level. In this way, the data signal and the inverted data signal, which are the minute difference voltage signals read from the predetermined memory cell, are amplified and latched to the power supply potential and the ground potential, respectively, and output to the data output line and the inverted data output line, respectively. can do.

This current detection type sense amplifier 70 is superior to the above-mentioned latch type sense amplifier 50 and current mirror type sense amplifier 60 in terms of high speed detection, amplification and power consumption of a minute difference voltage signal. However, the difference between the potential difference between the gate end and the source end of the NMOS 22a and the potential difference between the gate end and the source end of the NMOS 22b, that is, the operating margin of the current drive type latch circuit 12, is as shown in the graph of FIG. Since it is determined only by the minute difference voltage ΔV between the contacts a and b, and because the data signal and the inverted data signal are latched as in the case of the latch type sense amplifier 50, the data line and the inverted data line If the operation of the sense amplifier is not started after a sufficient potential difference is generated, that is, the NMOS 22
If a sufficient voltage difference is not applied to the contacts a and b when either a or 22b is turned on, there is a possibility of malfunction due to the operation timing of the sense amplifier or under the influence of noise or the like. I couldn't say there wasn't any.

[0014]

In view of various problems based on the above-mentioned prior art, an object of the present invention is to distinguish between a minute difference voltage signal and a data output signal which is amplified and latched and output. By connecting a capacitor to the capacitor and changing the potential of the data output signal according to the potential of the minute difference voltage signal, the operation margin can be increased, and the minute difference voltage signal can be sensed and amplified quickly and stably. An object of the present invention is to provide a semiconductor integrated circuit that can be manufactured.

[0015]

In order to achieve the above object, the present invention has a pair of inverters whose input terminals and output terminals are cross-coupled to each other, and the high potential power source terminals of these inverters are connected to each other. A current drive type latch circuit which is short-circuited and connected to a high-potential power supply, which amplifies and latches a pair of minute difference voltage signals input to a low-potential power supply terminal, and outputs the amplified minute difference voltage signals to a data output line and an inverted data output line, respectively. , The above 1
A precharge circuit for precharging the output end and the low potential power supply end of the pair of inverters to the same high potential, and a precharge circuit for precharging the low potential power supply end of the pair of inverters in accordance with the potentials of the data line and the inverted data line, respectively. A current drive circuit for discharging the generated electric charges and supplying the pair of minute difference voltage signals to the low potential power supply terminals of the pair of inverters, and an output terminal and a low potential power supply terminal for each of the pair of inverters. The present invention provides a semiconductor integrated circuit having a capacitor connected between them.

Here, the precharge circuit for precharging the output terminals of the pair of inverters has a voltage drop means between the output terminals of the pair of inverters and the high potential power source, It is preferable to precharge the precharge potential at the output end of the inverter to a potential lower than the precharge potential at the low potential power supply end.

[0017]

The semiconductor integrated circuit of the present invention is a current detection type sense amplifier which senses and amplifies a pair of minute difference voltage signals output to the data line and the inverted data line. The precharge circuit precharges the output end and the low potential power supply end of the pair of inverters of the current drive type latch circuit to the same high potential, and then inputs them to the current drive circuit via the data line and the inverted data line. In accordance with the potentials of the pair of minute difference voltage signals, the charges precharged at the low potential power supply terminals of the pair of inverters of the current drive type latch circuit are discharged, and the pair of current drive type latch circuit is The potential at the output end of the inverter is also dropped by the coupling according to the potential at the low-potential power supply end. That is, in the pair of inverters of the current drive type latch circuit, the potential difference between the low potential power supply end of one inverter and the output end of the other inverter, and the potential difference between the output end of one inverter and the low potential power supply end of the other inverter. It is possible to increase the difference from the potential difference between the two, that is, the operating margin of the current drive type latch circuit, and therefore, at the stage when one inverter starts operating, there is a time margin until the other inverter can start operating. is there. Therefore, according to the semiconductor integrated circuit of the present invention, any minute difference voltage signal can be sensed and amplified at high speed without malfunction. Further, by providing the voltage drop means between the output end of the pair of inverters of the current drive type latch circuit and the high potential power supply, the precharge potential at the output end of the pair of inverters is precharged at the low potential power supply end. It can be precharged to a potential lower than the potential. Therefore, the operating margin of the current drive type latch circuit can be further increased, and the semiconductor integrated circuit of the present invention can be operated more stably.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The semiconductor integrated circuit of the present invention will be described below in detail with reference to the preferred embodiments shown in the accompanying drawings.

FIG. 1 is a configuration circuit diagram of an embodiment of a semiconductor integrated circuit of the present invention. Semiconductor integrated circuit 10 shown in FIG.
Is a current detection type sense amplifier, and includes a current drive type latch circuit 12, a current drive circuit 14, and a precharge circuit 1.
6 and capacitors 18a and 18b.

Here, the current drive type latch circuit 12 has P
It has MOSs 20a and 20b and NMOSs 22a and 22b, and PM and PMOS 20a and NMOS 22a.
The OS 20b and the NMOS 22b together form a CMOS inverter. The input and output ends of these inverters are cross-coupled to each other, that is, P
Gate ends of the MOS 20a and the NMOS 22a and the PMO
The drain ends of S20b and NMOS 22b are short-circuited to each other and connected to the data output line.
20b and gate end of NMOS 22b and PMOS 20
The drain ends of a and the NMOS 22a are short-circuited to each other and connected to the inverted data output line. Also, PMO
The source ends (high-potential power supply ends) of S20a and S20b are short-circuited and connected to the power supply potential.

The current drive circuit 14 is an NMOS 24.
a, 24b, 24c, and these NMOS 24a,
The gate end of 24b is connected to the data line and the inverted data line, respectively, and the drain ends of these are connected to the drain ends (low potential power supply end) of the NMOSs 22a and 22b of the current drive type latch circuit 12, respectively, and the source ends of these are connected. They are short-circuited to each other and connected to the drain end of the NMOS 24c. The gate end of the NMOS 24c is connected to the sense line, and the source end thereof is connected to the ground potential.
Here, two NMOSs 24c are used to perform NMO.
It may be configured to connect to S22a and S22b. Note that the following description will be continued assuming that the drain ends of the NMOSs 22a and 22b are contacts A and B, the source ends thereof are contacts a and b, and the drain end of the NMOS 24c is contact c.

Further, the precharge circuit 16 is a PMOS 2
6a, 26b, 28a, 28b and their PMO
The gate ends of S26a, 26b, 28a, 28b are all connected to the sense line, their source ends are all connected to the power supply potential, and their drain ends are contacts A, B, respectively.
It is connected to a and b. In addition, the capacitors 18a, 18
One terminal of b is connected to the drain ends of the NMOSs 22a and 22b of the current drive type latch circuit 12, and the other terminals are connected to the source ends of the NMOSs 22a and 22b, respectively.

Next, the operation of reading data using this current detection type sense amplifier will be described with reference to the graph shown in FIG. 3, the potential difference ΔV ₁ (= V _B −V _A ) between the contacts A and B at the sense amplifier operation starting point and the contacts a and b are shown in FIG.
A large potential difference ΔV ₂ (= V _b −V _a ) is shown.

First, when the sense line is set to the low level, the PMOSs 26a, 26b, 28a, 2 of the current drive circuit 14 are set.
Since all 8b are turned on, the contacts A, B, a and b are all precharged to the power supply potential, and at the same time, the capacitance 18
a and 18b are also precharged to the power supply potential. Further, the data line and the inverted data line are discharged to the same potential, for example, the ground potential. Note that, conversely, the data line and the inverted data line may be precharged to the power supply potential.
In this state, the PMOS 20 of the current drive type latch circuit 12 is
a, 20b, NMOSs 22a, 22b, and NMOSs 24a, 24b, 24c of the current drive circuit 14 are all in the off state.

Then, after the discharge of the data line and the inverted data line is completed and these are set to the floating row state, the data signal and the inverted data signal are read from the predetermined memory cell to the data line and the inverted data line, respectively. At this time, the potentials of the data line and the inverted data line change according to the potentials of the data signal and the inverted data signal, respectively, and a minute difference voltage is generated between the data line and the inverted data line.

Then, when the sense line is set to the high level,
PMOS 26a, 26b, 28 of the precharge circuit 16
Since a and 28b are all turned off, contacts A, B and a
And b are all in the floating high state. At the same time, since the NMOS 24c of the current drive circuit 14 is turned on, drain currents flow through the NMOSs 24a and 24b in accordance with the potentials of the data line and the inverted data line, respectively, and the contacts a and b are respectively in contact with the drain currents.
The charges pre-charged to are discharged, and these potentials drop. Further, since the contacts A and B are connected to the contacts a and b via a capacitance, respectively,
The potentials of the contacts a and b drop, and the potentials of the contacts A and B also drop by capacitive coupling in accordance with the potentials of the contacts a and b.

For this reason, one NMOS gate end and
And the potential difference between the source end exceeds the threshold,
The potential difference between the gate and source ends of the other NMOS
It can be made smaller, and the operation of the current drive type latch circuit 12 can be reduced.
As for the work allowance, as shown in the graph of FIG.
Difference voltage ΔV between₁And the voltage difference ΔV between the contacts a and b ₂
It is decided by and. Therefore, the semiconductor integrated circuit 10 of the present invention
In comparison with the conventional current detection type sense amplifier,
The difference voltage ΔV between the contacts A and B₁Just increase the operating margin
Can be added to prevent malfunction.
More stable operation is possible.

For example, if the high level and the low level are read as the data signal and the inverted data signal, respectively, the potential of the data line becomes higher than the potential of the inverted data line by a minute voltage. Therefore, the charge precharged on the contact a is discharged earlier than the charge precharged on the contact b, and the potential of the contact a is changed to the contact b.
The potential of the contact A drops faster than the potential of the contact B, and the potential difference between the contacts B and a increases faster than the potential difference between the contacts A and b.

As described above, the potential difference between the gate end (contact B) and the source end (contact a) of the NMOS 22a is
The potential difference between the gate end (contact A) and the source end (contact b) of the NMOS 22b becomes faster than the potential difference.
The potential difference between the gate end and the source end of the OS 22a exceeds the threshold value faster than the potential difference between the gate end and the source end of the NMOS 22b, and the NMOS 22a has the N difference.
It is turned on earlier than the MOS 22b. The potential difference between the gate end and the source end of the NMOS 22b at this time can be made smaller than that in the case of the conventional current detection type sense amplifier shown in FIG. 7 because the potential of the contact A is lowered. . Therefore, it can be seen that if the capacitors 18a and 18b are connected between the contacts A and a and between the contacts B and b, respectively, the operational margin of the sense amplifier can be increased and malfunction can be prevented.

Then, when the NMOS 22a is turned on, the potential of the inverted data output line becomes low level.
The PMOS 20b and the NMOS 22b are turned on and off, respectively, and the potential of the data output line becomes high level.
The off state and the on state are determined respectively, and the data reading is completed. In this way, the data signal and the inverted data signal, which are the minute difference voltage signals read from the predetermined memory cell, are amplified and latched to the power supply potential and the ground potential, respectively, and output to the data output line and the inverted data output line, respectively. can do. The case where the high level and the low level are read as the data signal and the inverted data signal has been described as an example.
On the contrary, as a data signal and an inverted data signal,
Since the operations when the low level and the high level are read are exactly the same, the description thereof will be omitted.

Next, FIG. 2 shows a constitutional circuit diagram of another embodiment of the semiconductor integrated circuit of the present invention. The only difference between the semiconductor integrated circuit 30 shown in the same figure and the semiconductor integrated circuit 10 shown in FIG. 1 is that the semiconductor integrated circuit 30 shown in FIG. , Its detailed description is omitted. That is, in the semiconductor integrated circuit 10 shown in FIG. 1, the PMOS 20a, 20b, 26 of the current drive type latch circuit 12 and the precharge circuit 16 are provided.
Although the source terminals of a and 26b are all connected to the power supply potential, in the semiconductor integrated circuit 30 shown in FIG. 2, PM of the current drive type latch circuit 12 and the precharge circuit 16 is
The source ends of the OSs 20a, 20b, 26a, 26b are all connected to the source end of the NMOS 32, and the gate and drain ends of the NMOS 32 are both connected to the power supply potential.

Needless to say, the semiconductor integrated circuit 30 shown in FIG. 2 operates exactly like the semiconductor integrated circuit 10 shown in FIG. 1, but since the gate end of the NMOS 32 is connected to the power supply potential, it is always in the ON state. And NMOS3
The potential at the source end of 2 becomes a value lower than the power supply potential by the threshold value of the NMOS 32. Therefore, in the semiconductor integrated circuit 30 shown in FIG. 2, the precharged potentials of the contacts A and B are the semiconductor integrated circuit 10 shown in FIG.
Compared with the above, the value is lowered by the threshold value of the NMOS 32. Therefore, by providing the NMOS 32, the NMOS 22a or NMO of the current drive type latch circuit 12 is provided.
Since the timing at which S22b is turned on is delayed and the difference between the potential difference between the contacts A and b and the potential difference between the contacts B and a is further increased, the operational margin of the sense amplifier can be further increased. In addition, NM
The purpose of the OS 32 is to lower the precharge potential of the contacts A and B, and any element or circuit such as a transistor, a resistance element, or a diode may be used as long as this purpose can be achieved.

Finally, the operation source of the semiconductor integrated circuit of the present invention.
I will explain the reason. FIG. 4 shows a semiconductor integrated circuit of the present invention.
3 is an equivalent circuit diagram of the main part of FIG. This equivalent circuit is
NMOS that constitutes the inverter of the drive type latch circuit 12
22 and the drain end (contact A) of this NMOS 22 and
And the capacitance 18 connected between the source end (contact a) and the NM
Load on the drain end of OS22, that is, the inverted data output line
And a capacity 34. In addition, capacity 18 and load capacity
The capacitance value of the quantity 34 is C_LAnd C _BIs
I shall.

In the equivalent circuit shown in the figure, the potentials V _A and V _a of the contacts A and a before the operation of the sense amplifier, that is, at the time t = 0, are V _A = V _A (0) = V _cc ( Power supply potential) V _a = V _a (0) = V _cc , and therefore the charge Q at the contact A is Q = C _L · V _A (0) + C _B · (V _A (0) −V _a (0 )) = C _L · V _cc (Equation 1) Similarly, during operation of the sense amplifier, that is, NMO
The electric potentials V _A and V _a of the contacts A and a at the time t immediately before S22 is turned on are V _A = V _A (t) V _a = V _a (t), and therefore the electric charge at the contact A is Q is _{Q = C L · V a (} t) + C B · (V a (t) -V a (t)) ··· ( equation 2).

Until just before the NMOS 22 is turned on, the above equations 1 and 2 are equivalent from the law of conservation of charge, so that C _L · V _A (t) + C _B · (V _A (t) − V _a (t)) = C _L
・_Vcc holds. Therefore, the potential V _A of the contact A at the time t just before the NMOS 22 is turned on is

[Equation 1] Becomes Therefore, the difference potential ΔV _A of the contact A after the lapse of time t is

[Equation 2] Is.

For example, the power source potential V _cc is 5 V, the NMOS2
When the gate voltage when the 2 is turned on is assumed to be 1.5V, the potential V _a of the contact a at time _{t, V a (t) = 5V} (V cc) -1.5V ( gate voltage) =
Since it is 3.5 V, the potential difference ΔV _A of the contact A after the lapse of time t is

(Equation 3) Becomes As a result, when it is desired to add an extra differential voltage of 150 mV at the contact A before the NMOS 22 is turned on, that is, before the sense amplifier starts operating, the capacitance value C _B of the capacitor 18 is set to the load capacitance 34. It can be seen that it may be set to about 1/10 of the electrostatic capacitance value C _L. In this way, the operating margin of the sense amplifier is determined by the ratio of the capacitance values of the capacitance 18 and the load capacitance 34.

Although the semiconductor integrated circuit of the present invention has been described above based on the embodiments, the semiconductor integrated circuit of the present invention is not limited to the above-described embodiments. The problem of the conventional technique is that a sufficient differential voltage is not applied between the pair of minute differential voltage signals (contact points a and b in the embodiment) during the operation of the sense amplifier. Therefore, a solution to the problem of the prior art is to add a sufficient differential voltage between the pair of minute differential voltage signals before the sense amplifier starts to operate, for example, to prevent the sense amplifier from malfunctioning. The following improvement measures are possible. (1) Shield the minute difference voltage signal line to prevent coupling noise due to other signal lines. (2) The precharge potential at the output ends of the pair of inverters is set lower than the precharge potential at the low potential power supply end, or 1
The threshold value of the NMOS constituting the pair of inverters is set to another P
Sufficient differential voltage is applied between the minute differential voltage signals by setting the voltage higher than that of the MOS and NMOS to delay the operation timing of the sense amplifier. (3) Before starting the operation of the sense amplifier, a difference voltage according to the minute difference voltage signal is applied to the output terminals of the pair of inverters to increase the substantial difference voltage.

[0038]

As described in detail above, the semiconductor integrated circuit of the present invention comprises a current detection type latch circuit, a precharge circuit, a current drive circuit and a capacitor, and a pair of minute difference voltage signals. It is a current detection type sense amplifier that senses and amplifies. By connecting a capacitor between the output terminal and the low-potential power supply terminal of each pair of inverters in the current-driven latch circuit, the operating margin of the current-driven latch circuit can be increased. Therefore, according to the semiconductor integrated circuit of the present invention, any minute difference voltage signal can be sensed and amplified at high speed without malfunction. Further, according to the semiconductor integrated circuit of the present invention, by providing the voltage drop means between the output terminals of the pair of inverters of the current drive type latch circuit and the high potential power supply, the operating margin of the current drive type latch circuit is provided. The size can be further increased, and the semiconductor integrated circuit of the present invention can be operated more stably.

[Brief description of drawings]

FIG. 1 is a configuration circuit diagram of an embodiment of a semiconductor integrated circuit of the present invention.

FIG. 2 is a configuration circuit diagram of another embodiment of the semiconductor integrated circuit of the present invention.

FIG. 3 is a graph of an example showing the operation of the semiconductor integrated circuit of the present invention shown in FIG.

FIG. 4 is an equivalent circuit diagram of a main part of an embodiment of a semiconductor integrated circuit of the present invention.

FIG. 5 is a configuration circuit diagram of an example of a conventional latch type sense amplifier.

FIG. 6 is a configuration circuit diagram of an example of a conventional current mirror type sense amplifier.

FIG. 7 is a configuration circuit diagram of an example of a conventional current detection type sense amplifier.

8 is an exemplary graph showing an operation of the conventional current detection type sense amplifier shown in FIG.

[Explanation of symbols]

 10, 30 semiconductor integrated circuit 12 current drive type latch circuit 14 current drive circuit 16 precharge circuit 18, 18a, 18b capacitance 20a, 20b PMOS (P type MOS transistor) 26a, 26b, 28a, 28b PMOS 22a, 22b NMOS (N Type MOS transistor) 24a, 24b, 32 NMOS 34 load capacitance 50 latch type sense amplifier 52a, 52b PMOS 54a, 54b NMOS 60 current mirror type sense amplifier 62a, 62b PMOS 64a, 64b, 66 NMOS 70 current detection type sense amplifier

Claims (2)

[Claims] 1. A pair of inverters having input terminals and output terminals cross-coupled to each other, the high potential power source terminals of these inverters being short-circuited and connected to the high potential power source, and inputting to the low potential power source terminal. A current drive type latch circuit for amplifying and latching a pair of minute difference voltage signals to be output and outputting them to a data output line and an inverted data output line, respectively.
A precharge circuit for precharging the output end and the low potential power supply end of the pair of inverters to the same high potential, and a precharge circuit for precharging the low potential power supply end of the pair of inverters in accordance with the potentials of the data line and the inverted data line, respectively. A current drive circuit for discharging the generated electric charges and supplying the pair of minute difference voltage signals to the low potential power supply terminals of the pair of inverters, and an output terminal and a low potential power supply terminal for each of the pair of inverters. A semiconductor integrated circuit, comprising: a capacitor connected between them. 2. A precharge circuit for precharging the output terminals of the pair of inverters has a voltage drop means between the output terminals of the pair of inverters and a high-potential power supply, and the precharge circuit comprises the pair of inverters. 2. The semiconductor integrated circuit according to claim 1, wherein the precharge potential at the output end of the device is precharged to a potential lower than the precharge potential at the low potential power supply end.