CN114545063A - High-precision interval current detection circuit - Google Patents
High-precision interval current detection circuit Download PDFInfo
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- CN114545063A CN114545063A CN202210424390.XA CN202210424390A CN114545063A CN 114545063 A CN114545063 A CN 114545063A CN 202210424390 A CN202210424390 A CN 202210424390A CN 114545063 A CN114545063 A CN 114545063A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
Abstract
The application comprises a high-precision interval current detection circuit, and particularly relates to the technical field of current detection. In the circuit, the drain electrode of the MOS tube to be tested is connected with the inverting input end of a first comparator; the drain electrode of the MOS tube to be tested is connected with the inverting input end of the second comparator; the drain electrode of the first detection switch tube is connected with the non-inverting input end of the first comparator; the drain electrode of the second detection switch tube is connected with the non-inverting input end of the second comparator; the grid electrode of the MOS tube to be detected is connected with the grid electrode of the first detection switch tube; the grid electrode of the MOS tube to be detected is connected with the grid electrode of the second detection switch tube; the drain electrode of the first detection switching tube is grounded through a first branch of the first detection current mirror; the drain electrode of the second detection switch tube is grounded through the first branch of the second detection current mirror. Through the circuit structure, the current section is detected more accurately, and the current in each section is controlled accurately.
Description
Technical Field
The invention relates to the technical field of current detection, in particular to a high-precision interval current detection circuit.
Background
In a circuit structure in the prior art, it is generally necessary to detect a current and generate a control signal according to a detection result of the current to control a circuit, so as to ensure stable operation of the circuit.
As shown in FIG. 1, a current detection device commonly used in an integrated circuit chip is shown, wherein Mp0 is a power tube and is responsible for outputting current, Ms0 is a sampling tube, k0 is the width ratio of Mp0 to Ms0, and k0 is>>1，Io0And Vo0Respectively an output current and an output voltage, Is0And Vs0Are respectively provided withAre the sampled current and the sampled voltage. In the current detection process, the output current is sampled firstly, and the obtained sampling current is is0Then let the sampling current isFlows into the sampling resistor rs to generate a sampling voltage Vs0Then the voltage V is sampleds0A non-inverting input terminal of the comparator, and a reference voltage V connected to an inverting input terminal of the comparatorref0The comparison is carried out, the output voltage of the comparator is Vc0Is a logic signal.
However, in the above scheme, the drain voltages of Mp0 and Ms0 are different and are respectively Vo0And Vs0The voltage difference between the two is large and uncontrollable, so that the mirror current proportion of Mp0 and Ms0 is not completely equal to k0:1, and the current detection accuracy is low; meanwhile, the current detection circuit in the prior art can only detect current with a single numerical value, and interval current detection cannot be realized, so that the current in a specific interval cannot be controlled.
Disclosure of Invention
The embodiment of the application provides a high-precision interval current detection circuit, which improves the current detection precision and comprises an MOS tube to be detected, a first detection switch tube, a second detection switch tube, a first comparator, a first detection current mirror, a second comparator, a second detection current mirror, a first reference current source and a second reference current source;
the source electrode of the MOS tube to be tested is connected with the power supply input end; the source electrode of the first detection switch tube is connected with the power supply input end; the drain electrode of the MOS tube to be tested is connected with the inverting input end of the first comparator;
the source electrode of the second detection switch tube is connected with the power supply input end; the drain electrode of the MOS tube to be tested is connected with the inverting input end of the second comparator;
the drain electrode of the first detection switch tube is connected with the non-inverting input end of the first comparator; the drain electrode of the second detection switch tube is connected with the non-inverting input end of the second comparator;
the grid electrode of the MOS tube to be detected is connected with the grid electrode of the first detection switch tube; the grid electrode of the MOS tube to be detected is connected with the grid electrode of the second detection switch tube;
the drain electrode of the first detection switching tube is grounded through a first branch of the first detection current mirror; the drain electrode of the second detection switching tube is grounded through a first branch of the second detection current mirror;
the power supply input end is grounded through the first reference current source and a second branch of the first detection current mirror in sequence; and the power supply input end is grounded through the second reference current source and a second branch of the second detection current mirror in sequence.
In a possible implementation manner, the first branch of the first detection current mirror includes a first switching tube and a third switching tube; the drain electrode of the first switching tube is connected with the source electrode of the third switching tube;
the second branch of the first detection current mirror comprises a second switching tube and a fourth switching tube; and the drain electrode of the second switching tube is connected with the source electrode of the fourth switching tube.
In a possible implementation manner, the grounding of the power input terminal sequentially passes through the first reference current source and the second branch of the first detection current mirror, and includes:
the source electrode of the second switch tube is grounded, so that the power supply input end is grounded through the first reference current source, the fourth switch tube and the second switch tube in sequence;
the first detection switch tube is grounded through a first branch of the first detection current mirror, and comprises:
the drain electrode of the first detection switch tube is connected to the drain electrode of the third switch tube, and the source electrode of the first switch tube is grounded, so that the drain electrode of the first detection switch tube is grounded through the third switch tube and the first switch tube in sequence.
In a possible implementation manner, the first branch of the second detection current mirror includes a sixth switching tube and an eighth switching tube; the drain electrode of the sixth switching tube is connected with the source electrode of the eighth switching tube;
the second branch of the second detection current mirror comprises a seventh switching tube and a ninth switching tube; the drain electrode of the seventh switching tube is connected with the source electrode of the ninth switching tube.
In a possible implementation manner, the grounding of the power input end sequentially passes through a second reference current source and a second branch of the second detection current mirror, and includes:
the source electrode of the seventh switching tube is grounded, so that the second detection switching tube is grounded through the second reference current source, the ninth switching tube and the seventh switching tube in sequence;
the second detection switch tube is grounded through the first branch of the second detection current mirror, and comprises:
the drain electrode of the second detection switch tube is connected to the drain electrode of the eighth switch tube, and the source electrode of the sixth switch tube is grounded, so that the drain electrode of the second detection switch tube is grounded through the eighth switch tube and the sixth switch tube in sequence.
In a possible implementation manner, the channel width ratio of the MOS transistor to be tested to the first detection switch transistor is k1, and k1 is greater than 1.
In a possible implementation manner, the channel width ratio of the MOS transistor to be tested to the second detection switch transistor is k2, and k2 is greater than 1.
In a possible implementation manner, the MOS transistor to be detected, the first detection switch transistor, and the second detection switch transistor are PMOS transistors.
In a possible implementation manner, the circuit further includes a first current source, a second current source, a fifth switching tube and a tenth switching tube;
the power supply input end is connected to the drain electrode of the fourth switching tube through the first current source and the fifth switching tube in sequence;
the grid electrode of the fifth switching tube is connected with the output end of the first comparator;
the power supply input end is connected to the drain electrode of the ninth switching tube through the second current source and the tenth switching tube in sequence;
and the grid electrode of the tenth switching tube is connected with the output end of the second comparator.
In a possible implementation manner, the power input terminal is connected to the drain of the fourth switching tube sequentially through the first current source and the fifth switching tube, and the method includes:
the power input end is connected to the source electrode of the fifth switching tube through a first current source, and the drain electrode of the fifth switching tube is connected with the drain electrode of the fourth switching tube, so that the power input end is connected to the drain electrode of the fourth switching tube through the first current source and the fifth switching tube in sequence;
the power input end loops through second current source and tenth switch tube and is connected to the drain electrode of ninth switch tube, includes:
the power input end is connected to the source electrode of the tenth switching tube through a second current source, and the drain electrode of the tenth switching tube is connected with the drain electrode of the ninth switching tube, so that the power input end is connected to the drain electrode of the ninth switching tube through the second current source and the tenth switching tube in sequence.
The technical scheme provided by the application can comprise the following beneficial effects:
in the current detection circuit, through the characteristics of a comparator, a detection current mirror structure and a common source amplifier structure consisting of a detection switch tube and a first branch in the detection current mirror, the value of detection voltage is accurately equal to the value of output voltage in a critical state, the ratio of the detection current to the output current is accurately equal to the ratio of mirror image current, meanwhile, the current value on a second branch in the detection current mirror can be accurately copied to the first branch, and the current flowing through the first branch is equal to the detection current on the detection switch tube, so that the value of the detection current is accurately controlled; when the circuit has the first detection current mirror and the second detection current mirror, different critical states can be set so as to detect the specific region of the current through the output of the first comparator and the second comparator, so that the drain voltage of the detection switch tube is accurately equal to the drain voltage of the MOS tube to be detected when the circuit structure is in the critical state in the current detection process, and the current detection precision is improved; meanwhile, under the condition that the proportion of the mirror current is not adjusted due to overlarge voltage difference between the drain voltages of the detection switch tube and the MOS tube to be detected, the region where the current is located is accurately determined, so that the current in each region is accurately controlled according to the determined multiple current regions; in addition, the hysteresis module is added in the current detection circuit, so that the oscillation of the circuit is reduced, and the accuracy of current detection is further improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a current detection device commonly used in an integrated circuit chip.
Fig. 2 is a schematic diagram illustrating a high-precision interval current detection circuit according to an exemplary embodiment of the present application.
Fig. 3 is a schematic diagram illustrating a high-precision interval current detection circuit according to an exemplary embodiment of the present application.
Detailed Description
The technical solutions of the present application will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 2 is a schematic diagram illustrating a high-precision interval current detection circuit according to an exemplary embodiment of the present application. As shown in fig. 2, the circuit includes a to-be-tested MOS transistor Mp, a first detection switch transistor Ms1, a second detection switch transistor Ms2, a first comparator a1, a first detection current mirror, a second comparator a2, a second detection current mirror, and a first reference current source Iref1And a second reference current source Iref2；
The source electrode of the MOS tube Mp to be tested is connected with the power input end; the source electrode of the first detection switch tube Ms1 is connected with the power supply input end; the drain electrode of the MOS tube to be tested Mp is connected with the inverting input end of the first comparator A1;
the source electrode of the second detection switch tube Ms2 is connected with the power supply input end; the drain electrode of the MOS tube to be tested Mp is connected with the inverting input end of the second comparator A2;
the drain of the first detecting switch Ms1 is connected to the non-inverting input of the first comparator a 1; the drain of the second detecting switch Ms2 is connected to the non-inverting input terminal of the second comparator a 2;
the grid electrode of the MOS tube Mp to be detected is connected with the grid electrode of the first detection switch tube Ms 1; the grid electrode of the MOS tube Mp to be detected is connected with the grid electrode of the second detection switch tube Ms 2;
the power input terminal VddSequentially passes through the first reference current source Iref1And the second branch of the first detection current mirror is grounded (gnd); the power input terminal VddSequentially passes through a second reference current source Iref2And a second branch of the second detection current mirror is grounded;
the drain of the first detecting switch tube Ms1 is grounded through the first branch of the first detecting current mirror;
the drain of the second sensing switch Ms2 is grounded through the first branch of the second sensing current mirror.
Optionally, as shown in fig. 2, the first branch of the first detection current mirror includes a first switching tube M1 and a third switching tube M3; the drain of the first switch transistor M1 is connected to the source of the third switch transistor M3.
Optionally, as shown in fig. 2, the second branch of the first detection current mirror includes a second switching tube M2 and a fourth switching tube M4; the drain of the second switching tube M2 is connected to the source of the fourth switching tube M4.
Optionally, as shown in fig. 2, the gate of the second switch transistor M2 is connected to the gate of the first switch transistor M1; the gate of the second switch transistor M2 is connected to the drain of the second switch transistor M2;
the grid electrode of the fourth switching tube M4 is connected with the grid electrode of the third switching tube M3; the gate of the fourth switching transistor M4 is connected to the drain of the fourth switching transistor M4.
Optionally, as shown in fig. 2, the source of the second switch transistor M2 is grounded, so that the power input terminal V is connected to the groundddSequentially passes through the first reference current source Iref1The fourth switching tube M4 and the second switching tube M2 are grounded.
Optionally, as shown in fig. 2, the drain of the first detecting switch tube Ms1 is connected to the drain of the third switch tube, and the source of the first switch tube M1 is grounded, so that the drain of the first detecting switch tube Ms1 is grounded through the third switch tube M3 and the first switch tube M1 in sequence.
Optionally, as shown in fig. 2, a channel width ratio of the MOS transistor Mp to be tested to the first detection switch transistor Ms1 is k1, and k1 is greater than 1.
Optionally, as shown in fig. 2, the MOS transistor Mp to be tested and the first detection switch transistor Ms1 are PMOS transistors.
Optionally, as shown in fig. 2, the first branch of the second detection current mirror includes a sixth switching tube M6 and an eighth switching tube M8; the drain of the sixth switch transistor M6 is connected to the source of the eighth switch transistor M8.
Optionally, as shown in fig. 2, the second branch of the second detection current mirror includes a seventh switch tube M7 and a ninth switch tube M9; the drain of the seventh switch transistor M7 is connected to the source of the ninth switch transistor M9.
Optionally, as shown in fig. 2, the gate of the seventh switching tube M7 is connected to the gate of the sixth switching tube M6; the gate of the seventh switch transistor M7 is connected to the drain of the seventh switch transistor M7;
the gate of the ninth switching tube M9 is connected to the gate of the eighth switching tube M8; the gate of the ninth switch transistor M9 is connected to the drain of the ninth switch transistor M9.
Optionally, as shown in fig. 2, the source of the seventh switch transistor M7 is grounded, so that the power input terminal V is connected to the groundddSequentially passes through the second reference current source Iref2The ninth switch tube M9 and the seventh switch tube M7 are grounded.
Optionally, as shown in fig. 2, the drain of the second detecting switch tube Ms2 is connected to the drain of the eighth switch tube, and the source of the sixth switch tube M6 is grounded, so that the drain of the second detecting switch tube Ms2 is grounded through the eighth switch tube M8 and the sixth switch tube M6 in sequence.
Optionally, as shown in fig. 2, a channel width ratio of the MOS transistor Mp to be tested to the second detection switch transistor Ms2 is K2, and K2 is greater than 1.
Optionally, as shown in fig. 2, the MOS transistor Mp to be tested and the second detection switch transistor Ms2 are PMOS transistors.
The operation principle of the section current detection circuit shown in fig. 2 is explained below.
Output current IoThe output current I is the current flowing on the MOS tube Mp to be measuredoThrough the first detection current mirror and the second detection current mirror, a first detection current I is respectively generated in the first detection switch tube Ms1 and the second detection switch tube Ms2s1And a second detection current Is2；
Meanwhile, the first detection switch tube Ms1, the third switch tube M3 and the first switch tube M1 in the first detection current mirror form a first common source amplifier, and the second detection switch tube Ms2, the eighth switch tube M8 and the sixth switch tube M6 in the second detection current mirror form a second common source amplifier.
First consider the detection of the current in the MOS transistor under test by a first detection current mirror (i.e., as in block 1 of fig. 2).
On the one hand, as shown in fig. 2, when the MOS transistor Mp under test and the gate control voltage V on the first detecting switch Ms1 are both appliedg1Is equal to power input terminal VddAt the voltage of (3), the voltage V between the MOS tube Mp to be detected and the gate source of the first detection switch tube Ms1gs1Is 0, the MOS tube Mp to be tested and the first detection switch tube Ms1 are both in a cut-off state, and the current I on the MOS tube to be tested is at the momentoAnd a first detection current I on the first detection switch tubes1Satisfy Io=Is1=0, so the drain currents of the third switch tube M3 and the first switch tube M1 are also zero, so the voltage V on the drain of the first detection switch tubes1Is inevitably 0, otherwise, the first detection current mirror is inevitably provided with current, and V is useds1Is 0, so thatVs1When the output signal V is input to the non-inverting input terminal of the first comparator A1, the output signal V of the first comparator A1c1The low value indicates that the output current of the MOS transistor Mp to be detected does not exceed the current interval preset by the first detection current mirror.
On the other hand, when the current in the MOS transistor Mp to be tested in the current detection circuit is about to exceed the current range, i.e. the first comparator is in the critical state, i.e. when the gate control voltage V is appliedg1From the mains input voltage VddWhen the voltage is reduced, the voltage between the Mp gates and the sources of the MOS transistor to be tested is increased, so that the output current I on the MOS transistor to be tested is increasedoIncreasing, so that the first detection current I on the first detection switch tubes1Is also increased; meanwhile, the fourth switching tube M4 and the second switching tube M2 are connected with the first reference current source Iref1The current flowing through the fourth switching tube M4 and the second switching tube M2 is constant and always the first reference current source Iref1So that the voltage V between the gate and the source of the fourth switching tube M4 and the second switching tube M2gs2The grid voltages of the fourth switching tube M4 and the second switching tube M2 are also unchanged all the time, and the grid voltages of the third switching tube M3 and the first switching tube M1 are also unchanged all the time because the third switching tube M3 is connected with the grid of the fourth switching tube M4 and the first switching tube M1 is connected with the grid of the second switching tube M2;
so that when the first detection current Is1There are three possibilities for increase:
1. if the first detection voltage Vs1The gate voltages of the third switching tube M3 and the first switching tube M1 are not changed, so that the current flowing through the third switching tube M3 and the first switching tube M1 is also not changed; meanwhile, since the non-inverting input terminal and the inverting input terminal of the first comparator cannot flow current, the first detection current Is1All flows into the third switch tube M3 and the first switch tube M1, so the first detection current Is1Current I flowing through the third switching tubem3And a current I flowing through the first switching tubem1Satisfy Is = Im3= Im1Obviously, it is impossible to firstDetecting the current Is1Increasing the current flowing through the third switch tube M3 and the first switch tube M1;
2. if the first detection voltage Vs1The gate voltages of the third switching tube M3 and the first switching tube M1 are always unchanged, so that the current flowing through the third switching tube M3 and the first switching tube M1 is reduced at this time; meanwhile, since the non-inverting input terminal and the inverting input terminal of the comparator cannot flow current, the first detection current IsAll flows into the third switch tube M3 and the first switch tube M1, so the first detection current IsA current I flowing through the third switching tubem3And a current I flowing through the first switching tubem1Satisfy Is1= Im3= Im1It is obvious that the first detection current I is not possibles1The current flowing through the third switch tube M3 and the first switch tube M1 is increased, but decreased;
3. if the first detection voltage Vs1The gate voltages of the third switching tube M3 and the first switching tube M1 are always unchanged, so that the current flowing through the third switching tube M3 and the first switching tube M1 is increased; meanwhile, since the non-inverting input terminal and the inverting input terminal of the comparator cannot flow current, the first detection current Is1All flows into the third switch tube M3 and the first switch tube M1, so the first detection current Is1Current I flowing through the third switching tubem3And a current I flowing through the first switching tubem1Satisfy Is = Im3= Im1It is apparent that, at this time, the first detection current Is1And the current flowing through the third switching tube M3 increases simultaneously with the current flowing through the first switching tube M1.
As can be seen from the above analysis, the first switch transistor M1, the second switch transistor M2, the third switch transistor M3 and the fourth switch transistor M4 together form a detection current mirror structure, and the first detection switch transistor Ms1, the third switch transistor M3 and the first switch transistor M1 form a common source amplifier structure, so that the gate control voltage V is enabled to be the same as the gate control voltage Vg1Decrease, output current IoWhen increasing, the first detection current Is1Increasing the first detection voltage Vs1And also increases.
When the first detection voltage Vs1Increase to an output voltage VoAt first, a first detection current I in the first detection switch tube Ms1s1Can be exactly equal to the output current Io1/k1, i.e. Is1=Io/k 1; and at this time, due to Vs1=VoAnd assume V at this timeo(e.g. V)o>0.5V) enables the four MOS transistors (the first switch transistor M1, the second switch transistor M2, the third switch transistor M3, and the fourth switch transistor M4) of the first detection current mirror to all work in the saturation region, so that the first reference current source I is in this stateref1The current value can be accurately copied to the third switch tube M3, and the current I flowing through the third switch tube M3m3Equal to the first detection current I on the first detection switch tube Ms1s1Thus the first detection current Is1Current I flowing through the third switching tubem3And a current I flowing through the first switching tubem1Satisfy Is = Im3=Iref1；
In summary, when the first comparator A1 is in the threshold state, Vs1=VoThe gate control voltage has a threshold voltage of Vg10(ii) a At this time, the first detection current I of the first detection switch tube Ms1s1Can be exactly equal to i o1/k1, i.e. Is1=ioThe first detection current mirror formed by the first current mirror is a cascode structure, and the first reference current source I is a first reference current sourceref1Can be accurately copied to the third switch tube M3, and the current on the third switch tube M3 is equal to the current on the first detection switch tube Ms1, i.e. Is1 =Im3=Iref1Therefore, at this time, Iref1=Io/k1。
Furthermore, consider the detection of the current in the MOS transistor under test by the second detection current mirror (i.e., as shown in block 2 of fig. 2).
Because the principle of detecting the current in the to-be-detected MOS tube through the second detection current mirror is similar to the above-mentioned principle of detecting the current in the to-be-detected MOS tube through the first detection current mirror, the details are not repeated here. And when the second comparator A2 is in the critical state, Vs2=VoThe gate control voltage has a threshold voltage of Vg20(ii) a At this time, the second detection current I of the second detection switch tube Ms2s2Can be exactly equal to i o1/k2, i.e. Is2=ioThe second detection current mirror is a cascode-structured current mirror, and the second reference current source I is formed by M6-M9ref2Can be accurately copied to the eighth switch tube M8, and the current I on the eighth switch tube M8m8Equal to the current on the second detection switch Ms2, i.e. Is2=Im8=Iref2Therefore, at this time, Iref2=Io/k2。
In particular, assume Iref1=30mA，Iref2=60mA, k1= k2= 10; therefore, when Io=k1* Iref1When =300mA, Vo=Vs1When I iso=k2* Iref2When =600mA, Vo=Vs2；
When outputting current IoWhen the voltage is lower than 300mA, the grid voltage V of the MOS tube to be testedg1> Vg10At this time, since the first detecting switch Ms1, the third switch M3 and the first switch M1 in the first detecting current mirror form the first common source amplifier, V isg1Is increased to result in Vs1So that V is reduceds1< VoFirst current detection output signal Vc1Is low;
in the same way, when the output current IoWhen the voltage is lower than 300mA, the grid voltage V of the MOS tube to be testedg1> Vg10> Vg20At this time, since the second detection MOS transistor Ms2 and the eighth switching transistor M8 and the sixth switching transistor M6 in the second detection current mirror form a second common source amplifier, V iss2< VoSecond current detection output signal Vc2Is low;
when outputting current IoWhen the voltage is higher than 300mA and lower than 600mA, the grid voltage V of the MOS tube to be testedg1< Vg10And V isg1> Vg20At this time, since the first detecting switch Ms1, the third switch M3 and the first switch M1 in the first detecting current mirror form the first common source amplifier, V iss1> VoFirst current detection output signal Vc1Is high;
when outputting current IoWhen the voltage is higher than 300mA and lower than 600mA, the grid voltage V of the MOS tube to be testedg1< Vg10And V isg1> Vg20At this time, since the second detection switch tube Ms2 and the eighth switch tube M8 and the sixth switch tube M6 in the second detection current mirror constitute a second common source amplifier, V iss2< VoSecond current detection output signal Vc2Still low;
when outputting current IoWhen the voltage is higher than 600mA, the grid voltage V of the MOS tube to be testedg1< Vg20< Vg10At this time, since the first detecting switch Ms1, the third switch M3 and the first switch M1 in the first detecting current mirror form the first common source amplifier, V iss1> VoFirst current detection output signal Vc1Is high;
in the same way, when the output current IoWhen the voltage is higher than 600mA, the grid voltage V of the MOS tube to be testedg1< Vg20< Vg10At this time, since the second detection switch tube Ms2 and the eighth switch tube M8 and the sixth switch tube M6 in the second detection current mirror constitute a second common source amplifier, V iss2> VoSecond current detection output signal Vc2Is high;
thus, the output signal V is detected by detecting the first currentc1And a second current detection output signal Vc2It can be obtained in which interval the output current is located, i.e. if Vc1And Vc2If all are low, the output current IoBelow 300 mA; if Vc1Is high, Vc2Is low, then the current I is outputoBetween 300mA-600 mA; if Vc1And Vc2All are high, then the current I is outputoAbove 600 mA; therefore, according to the obtained current interval, the current in the specific interval is controlled, such as average current control, overcurrent protection or short-circuit protection.
In summary, in the current detection circuit, through the characteristics of the comparator, the detection current mirror structure, and the common source amplifier structure formed by the detection switch tube and the first branch in the detection current mirror, the value of the detection voltage is accurately equal to the value of the output voltage in the critical state, at this time, the ratio of the detection current to the output current is accurately equal to the mirror current ratio, meanwhile, the current value on the second branch in the detection current mirror can be very accurately copied to the first branch, and the current flowing through the first branch is equal to the detection current on the detection switch tube, so that the value of the detection current is accurately controlled; when the circuit has the first detection current mirror and the second detection current mirror, different critical states can be set so as to detect the specific region of the current through the output of the first comparator and the second comparator, so that the drain voltage of the detection switch tube is accurately equal to the drain voltage of the MOS tube to be detected when the circuit structure is in the critical state in the current detection process, and the current detection precision is improved; meanwhile, under the condition that the proportion of the mirror current is not adjusted due to overlarge voltage difference between the drain voltages of the detection switch tube and the MOS tube to be detected, the region where the current is located is accurately determined, and therefore the current in each region is accurately controlled according to the determined multiple current regions.
Fig. 3 is a schematic diagram illustrating a high-precision interval current detection circuit according to an exemplary embodiment of the present application. As shown in FIG. 3, the circuit includes a first current source I in addition to the structure of the high-precision interval current detection circuit shown in FIG. 2h1A second current source Ih2A fifth switch tube M5 and a tenth switch tube M10;
the power input end passes through the first current source I in turnh1The fifth switching tube M5 is connected to the drain of the fourth switching tube M4;
the gate of the fifth switch transistor M5 is connected to the output terminal of the target comparator a 1;
the power input end passes through the second current source I in turnh2And the tenth switching tube M10 is connected to the drain of the ninth switching tube M9;
the gate of the tenth switching transistor M10 is connected to the output terminal of the second comparator a 2.
Optionally, the power input terminal passes through a first current source Ih1Is connected to the firstA source of the fifth switching transistor M5, and a drain of the fifth switching transistor M5 is connected to a drain of the fourth switching transistor M4, so that the power input terminal sequentially passes through the first current source Ih1The fifth switching tube M5 is connected to the drain of the fourth switching tube M4;
optionally, the power input terminal passes through a second current source Ih2Is connected to the source of the tenth switching transistor M10, and the drain of the tenth switching transistor M10 is connected to the drain of the ninth switching transistor M9, so that the power input terminal passes through the second current source I in sequenceh2And the tenth switching tube M10 is connected to the drain of the ninth switching tube M9;
the fifth switch transistor M5 and the tenth switch transistor M10 are both PMOS transistors.
As can be seen from the description of the embodiment shown in fig. 2, the high-precision interval current detection circuits shown in fig. 2 are all k1 × Iref1And k 2Iref2Judged for the limit, but this judgment easily leads to the output current at k1ref1And k2 xiref2Nearby oscillation, so at this time, a hysteresis module needs to be added to improve the oscillation, so that the hysteresis type high-precision interval current detection circuit in fig. 3 is obtained, and the precision of the current detection circuit is further improved;
the operation principle of the hysteresis-type high-precision interval current detection circuit shown in fig. 3 is as follows:
when outputting current IoLess than k1ref1When, Vc1When the voltage is low, the fifth switch transistor M5 is turned on, and the current flowing into the fourth switch transistor M4 is Iref1+ Ih1So when the output current io reaches k1 (I)ref1+ Ih1) When, Vc1Becomes high; vc1After the voltage goes high, the fifth switch tube M5 is turned off, and the current flowing into the fourth switch tube M4 becomes Iref1So when the output current IoLess than k1ref1When, Vc1Is low and therefore is detected by adding a k 1I to the current sensing circuith1Thereby reducing the oscillation of the circuit;
in particular, assume Iref1=30mA，Iref2=60mA，k1=k2=10，Ih1=1mA，Ih2=1mA；
Therefore, as can be seen from the above analysis, the output signal V is detected by detecting the first currentc1And a second current detection output signal Vc2It can be obtained in which interval the output current is located, i.e. if Vc1And Vc2If all are low, the output current IoBelow 300 mA; if Vc1Is high, Vc2Is low, then the current I is outputoBetween 310mA-600 mA; if Vc1And Vc2All are high, then the current I is outputoAbove 610 mA;
in fig. 2 and 3, only the high-precision interval current detection circuit composed of two current detection modules (frame 1 and frame 2) is illustrated, and the output current is divided into three segments for detection, each of which is Vc1And Vc2To reflect the interval and the magnitude of the output current; however, in actual use, n current detection modules can be used to generate n VcSignal Vc1- VcnN +1 current intervals are obtained, and these VcThe signals are all output of the comparator and belong to logic signals, so that n V arecAnd inputting the signals into a logic control circuit, and accurately controlling the current in each interval according to the obtained n +1 current intervals.
In summary, in the current detection circuit, through the characteristics of the comparator, the detection current mirror structure, and the common source amplifier structure formed by the detection switch tube and the first branch in the detection current mirror, the value of the detection voltage is accurately equal to the value of the output voltage in the critical state, at this time, the ratio of the detection current to the output current is accurately equal to the mirror current ratio, meanwhile, the current value on the second branch in the detection current mirror can be very accurately copied to the first branch, and the current flowing through the first branch is equal to the detection current on the detection switch tube, so that the value of the detection current is accurately controlled; when the circuit has the first detection current mirror and the second detection current mirror, different critical states can be set so as to detect the specific region of the current through the output of the first comparator and the second comparator, so that the drain voltage of the detection switch tube is accurately equal to the drain voltage of the MOS tube to be detected when the circuit structure is in the critical state in the current detection process, and the current detection precision is improved; meanwhile, under the condition that the proportion of the mirror current is not adjusted due to overlarge voltage difference between the drain voltages of the detection switch tube and the MOS tube to be detected, the region where the current is located is accurately determined, so that the current in each region is accurately controlled according to the determined multiple current regions; in addition, the hysteresis module is added in the current detection circuit, so that the oscillation of the circuit is reduced, and the accuracy of current detection is further improved.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (10)
1. A high-precision interval current detection circuit is characterized by comprising an MOS tube to be detected, a first detection switch tube, a second detection switch tube, a first comparator, a first detection current mirror, a second comparator, a second detection current mirror, a first reference current source and a second reference current source;
the source electrode of the MOS tube to be tested is connected with the power supply input end; the source electrode of the first detection switch tube is connected with the power supply input end; the drain electrode of the MOS tube to be tested is connected with the inverting input end of the first comparator;
the source electrode of the second detection switch tube is connected with the power supply input end; the drain electrode of the MOS tube to be tested is connected with the inverted input end of the second comparator;
the drain electrode of the first detection switch tube is connected with the non-inverting input end of the first comparator; the drain electrode of the second detection switch tube is connected with the non-inverting input end of the second comparator;
the grid electrode of the MOS tube to be detected is connected with the grid electrode of the first detection switch tube; the grid electrode of the MOS tube to be detected is connected with the grid electrode of the second detection switch tube;
the drain electrode of the first detection switching tube is grounded through a first branch of the first detection current mirror; the drain electrode of the second detection switching tube is grounded through a first branch of the second detection current mirror;
the power supply input end is grounded through the first reference current source and a second branch of the first detection current mirror in sequence; and the power supply input end is grounded through the second reference current source and a second branch of the second detection current mirror in sequence.
2. The circuit of claim 1, wherein the first branch of the first detection current mirror comprises a first switch tube and a third switch tube; the drain electrode of the first switching tube is connected with the source electrode of the third switching tube;
the second branch of the first detection current mirror comprises a second switching tube and a fourth switching tube; and the drain electrode of the second switching tube is connected with the source electrode of the fourth switching tube.
3. The circuit of claim 2, wherein the power input terminal is connected to ground through the first reference current source and the second branch of the first detection current mirror in sequence, comprising:
the source electrode of the second switch tube is grounded, so that the power supply input end is grounded through the first reference current source, the fourth switch tube and the second switch tube in sequence;
the first detection switch tube is grounded through a first branch of the first detection current mirror, and comprises:
the drain electrode of the first detection switch tube is connected to the drain electrode of the third switch tube, and the source electrode of the first switch tube is grounded, so that the drain electrode of the first detection switch tube is grounded through the third switch tube and the first switch tube in sequence.
4. The circuit of claim 1, wherein the first branch of the second detection current mirror comprises a sixth switching tube and an eighth switching tube; the drain electrode of the sixth switching tube is connected with the source electrode of the eighth switching tube;
the second branch of the second detection current mirror comprises a seventh switching tube and a ninth switching tube; the drain electrode of the seventh switching tube is connected with the source electrode of the ninth switching tube.
5. The circuit of claim 4, wherein the power input terminal is connected to ground through a second reference current source and a second branch of the second detection current mirror in sequence, comprising:
the source electrode of the seventh switch tube is grounded, so that the power input end is grounded through the second reference current source, the ninth switch tube and the seventh switch tube in sequence;
the second detection switch tube is grounded through the first branch of the second detection current mirror, and comprises:
the drain electrode of the second detection switch tube is connected to the drain electrode of the eighth switch tube, and the source electrode of the sixth switch tube is grounded, so that the drain electrode of the second detection switch tube is grounded through the eighth switch tube and the sixth switch tube in sequence.
6. The circuit as claimed in claim 2 or 3, wherein the ratio of the channel width of the MOS transistor under test to the channel width of the first detection switch transistor is k1, and k1 is greater than 1.
7. The circuit as claimed in claim 4 or 5, wherein the channel width ratio of the MOS transistor to be tested to the second detection switch transistor is k2, and k2 is greater than 1.
8. The circuit of claim 7, wherein the MOS transistor to be tested, the first detection switch transistor and the second detection switch transistor are PMOS transistors.
9. The circuit according to any one of claims 1 to 4, wherein the circuit further comprises a first current source, a second current source, a fifth switch tube and a tenth switch tube;
the power supply input end is connected to the drain electrode of the fourth switching tube through the first current source and the fifth switching tube in sequence;
the grid electrode of the fifth switching tube is connected with the output end of the first comparator;
the power supply input end is connected to the drain electrode of the ninth switching tube sequentially through a second current source and the tenth switching tube;
and the grid electrode of the tenth switching tube is connected with the output end of the second comparator.
10. The circuit of claim 9, wherein the power input terminal is connected to the drain of the fourth switching tube sequentially through the first current source and the fifth switching tube, and the circuit comprises:
the power input end is connected to the source electrode of the fifth switching tube through a first current source, and the drain electrode of the fifth switching tube is connected with the drain electrode of the fourth switching tube, so that the power input end is connected to the drain electrode of the fourth switching tube through the first current source and the fifth switching tube in sequence;
the power input end loops through second current source and tenth switch tube and is connected to the drain electrode of ninth switch tube, includes:
the power input end is connected to the source electrode of the tenth switching tube through a second current source, and the drain electrode of the tenth switching tube is connected with the drain electrode of the ninth switching tube, so that the power input end is connected to the drain electrode of the ninth switching tube through the second current source and the tenth switching tube in sequence.
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