JP2008140113A - Voltage regulator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To test the electric characteristics of an evaluation object element without installing any exclusive terminal for test. <P>SOLUTION: This voltage regulator is provided with: a voltage dividing circuit 13; a reference voltage circuit 4; an error amplifier 12; an output transistor 11; a voltage dictator 14 to which a second output of the voltage dividing circuit 13 is input; a first switch whose opening/closing is controlled by the output of the voltage dictator 14; and an evaluation object element 19, which is installed serially with a first switch, whose electric characteristics are evaluated by using an output terminal 3 and a ground terminal 2 according to the opening/closing of the first switch. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a voltage regulator (VR) equipped with a function for testing the characteristics of internal elements.

VR tends to be highly accurate year by year. Therefore, a method of adjusting circuit characteristics so that the product specifications to be guaranteed can be satisfied after initial evaluation of the element characteristics of the manufactured IC is generally used. In the evaluation, it is necessary to bring the probe of the measuring instrument into contact with a terminal installed in the IC from the outside. However, a terminal (test terminal) for use in a test is not desirable because it increases the chip area of the IC. In consideration of these points, techniques disclosed in Patent Documents 1 and 2 are disclosed as methods for performing a test without providing a dedicated test terminal for the IC.
JP 2001-053232 A JP 2006-170898 A

  In the conventional technique, the output terminal can be used as an input terminal for testing, thereby shifting to the test mode without adding a dedicated test terminal. However, in order to evaluate the characteristics of the internal element of the VR, it is necessary to provide at least one sense terminal for applying a probe from the outside to the internal element evaluation circuit that operates in response to the test mode signal. That is, in Patent Document 1, it is necessary to provide a sense terminal in the test mode control means, and in Patent Document 2, an input terminal and an output terminal connected to other circuits are used as sense terminals. It will be.

  In the present invention, in a VR with a small number of terminals, it is possible to carry out a high-accuracy test without adding a terminal for sensing internal element characteristics as well as a terminal for shifting to a test mode. An object of the present invention is to provide a simple test circuit.

  In order to solve the above problems, the present invention provides a voltage regulator equipped with a function of testing the characteristics of an internal element, a voltage dividing circuit connected between an output terminal and a ground terminal, a reference voltage circuit, An output of the reference voltage circuit is connected to the inverting input terminal, an error amplifier in which the first output of the voltage dividing circuit is connected to the non-inverting input terminal, a gate is connected to the output of the error amplifier, and a source is connected to the power supply terminal An output transistor having a drain connected to the output terminal; a voltage detector to which a second output of the voltage dividing circuit is input; and opening and closing controlled by an output of the voltage detector; and the output terminal and the ground A first switch provided between the output terminal and the ground terminal, and is provided in series with the first switch. An element to be evaluated whose electrical characteristics are evaluated by using the output terminal and the ground terminal by opening and closing the circuit, and between the power supply terminal and the gate of the transistor whose opening and closing is controlled by the output of the voltage detector. The second switch, the source is connected to the output terminal, the gate and the drain are connected to the second switch, the transistor from which the current from the output terminal is cut off by opening and closing the second switch, A voltage regulator is provided.

  According to the present invention, since the output terminal can be used as a test terminal, the electrical characteristics of the evaluation target element can be tested without providing a dedicated test terminal.

  An embodiment is shown in FIG. First, the circuit configuration will be described. A voltage dividing circuit 13 is connected between the output terminal 3 and the ground terminal 2. The output of the error amplifier 12 in which the reference voltage 4 is connected to the inverting input terminal and the voltage dividing node 5 is connected to the non-inverting input terminal is connected to the gate of the output transistor 11. The source of the output transistor 11 is connected to the power supply terminal 1, and the drain is connected to the output terminal 3. The voltage dividing node 6 is connected to the input of the voltage detector 14, and the switch 15 and the switch 16 are controlled by its output. The switch 15 and the evaluation target element 19 are connected in series between the output terminal 3 and the ground terminal 2. The switch 16 and the fuse 17 are connected in series between the power supply terminal 1 and the gate of the PMOS 18. The source of the PMOS 18 is connected to the output terminal 3, and the internal circuit 20 is connected between the drain and gate of the PMOS 18 and the ground terminal 2.

  Next, circuit operation will be described. When the error amplifier 12 controls the output transistor 11 so that the voltage of the voltage dividing node 5 of the output voltage 3 matches the reference voltage 4, the output voltage 3 becomes constant. The PMOS 18 and the internal circuit 20 perform functions such as overcurrent control and phase compensation. Here, since the voltage dividing circuit 13, the PMOS 18, and the internal circuit 20 are connected between the output terminal 3 and the ground terminal 2, a current flows from the output terminal 3 to the ground terminal 2, and an error occurs during the test. .

  A more specific example is shown in FIGS. In the configuration of the internal circuit 20 shown in FIG. 3, the source of the PMOS 21 is connected to the power supply terminal 1, the gate is connected to the output of the error amplifier 12, and the drain is connected to the source of the PMOS 22. The gate of the PMOS 22 is connected to the gate of the PMOS 18, and the drain is connected to the ground terminal 2 via the resistance element 23. A constant current source 24 is connected between the drain of the PMOS 18 and the ground terminal 2. That is, the current flowing through the constant current source 24 flows from the output terminal 3 to the ground terminal 2.

  The content of the present invention is a part constituted by the voltage dividing node 6, the voltage detector 14, the switch 15, the evaluation target element 19, the switch 16 and the fuse 17. As in the prior art, the output logic of the voltage detector 14 is switched by the voltage of the voltage dividing node 6. For example, when a high voltage is applied to the output terminal 3, the voltage at the voltage dividing node 6 also increases, and when the voltage at the voltage dividing node 6 is equal to or higher than a specified voltage, the output of the voltage detector 14 becomes low. On the other hand, when a low voltage is applied to the output terminal 3, the voltage at the voltage dividing node 6 is also lowered. When the voltage at the voltage dividing node 6 is less than the specified voltage, the output of the voltage detector 14 becomes high. When the voltage detector 14 is a comparator, the specified voltage is a bias voltage generated by an internal circuit that satisfies the above-described logic. Further, as will be described with reference to FIG. 2, when the voltage detector 14 uses the inverting amplification operation of the MOS, the specified voltage becomes the MOS threshold voltage. Further, in a test in which a voltage different from the voltage normally output from the output terminal 3 is applied, the VR is in the test mode regardless of whether the applied voltage is high or low. Therefore, the evaluation target element 19 and the elements in the voltage dividing circuit 13 can be evaluated.

Next, the switch 15 and the switch 16 are opened and closed based on the output of the voltage detector 14. At this time, the switch 15 determines whether or not to connect the evaluation target element 19 between the output terminal 3 and the ground terminal 2. Therefore, when the switch 15 is turned on, the user can evaluate the voltage-current characteristics of the evaluation target element 19 by applying a measurement probe to the output terminal 3 and the ground terminal 2 from the outside. The current flowing through the PMOS 18 and the current flowing through the voltage dividing circuit 13 are errors. Therefore, the switch 16 switches between a normal mode in which a current is supplied to the PMOS 18 and a test mode in which no current is supplied. Further, here, the impedance between the evaluation target element 19 and the element in the voltage dividing circuit 13 has a magnitude relationship. The element having the higher impedance is greatly affected by an error due to the current flowing in the PMOS 18 because the current flowing when the voltage is applied to the output terminal 3 becomes small. Therefore, when evaluating the voltage-current characteristics of the high impedance element among the evaluation target element 19 and the elements in the voltage dividing circuit 13, the user turns on the switch 16 and enters a test mode in which no current flows through the PMOS 18. Will do. In the example of FIG. 1, the element in the voltage dividing circuit 13 has a higher impedance than the evaluation target element 19, and the voltage-current characteristics of the elements in the voltage dividing circuit 13 are turned off by turning off the switch 15. At the time of evaluation, the switch 16 is on. When the user evaluates the voltage-current characteristics of the evaluation target element 19, the current flowing through the voltage dividing circuit 13 is calculated by the following equation, and the current is calculated from the current flowing between the output terminal 3 and the ground terminal 2. By subtracting, the evaluation target element 19 can be evaluated with higher accuracy. Here, I2 ′ is a current flowing through the evaluation target element 19 (after correction), I2 is an actual measured value (before correction) of a current flowing between the output terminal 3 and the ground terminal 2, and I1 flows into the voltage dividing circuit 13. V2 is a voltage applied to the output terminal 3 when testing the evaluation target element 19 (switch 15 is on), V1 is a voltage applied to the output terminal 3 when testing the voltage dividing circuit 13 (switch 15 is off). Given the applied voltage,
I2 ′ = I2− {I1 × (V2 / V1)}
Is established.

  The fuse 17 is disconnected after the end of the test so that a test mode in which no current flows through the PMOS 18 at the output voltage during normal operation is prevented. After the evaluation of the evaluation target element 19 and the elements in the voltage dividing circuit 13, the fuse 17 is cut, and another evaluation of VR may be performed in this state.

  According to such a voltage regulator, the power supply terminal 1, the ground terminal 2, and the output terminal 3 that are originally present in the VR are added without newly adding a test mode transition terminal and a sense terminal of the evaluation target element 19. And the voltage-current characteristics of the evaluation target element 19 and the elements in the voltage dividing circuit 13 are evaluated. Further, since the switch 16 for stopping the current flowing in the internal circuit 20 and the switch 15 for connecting the evaluation target element 19 between the output terminal 3 and the ground 2 are provided, the evaluation is performed based on the voltage applied to the output terminal 3. The voltage-current characteristics of the target element 19 and the elements in the voltage dividing circuit 13 are evaluated with higher accuracy.

  FIG. 2 specifically shows the voltage detector 14, the switch 15, and the switch 16.

  First, as a configuration of the voltage detector 14, the gate of the NMOS 34 is connected to the voltage dividing node 6, the source is connected to the ground terminal 2, and the drain is connected to the power supply terminal 1 via the fuse 38 and the pull-up resistor 31. Yes. One end of the fuse 38 is connected to the input of an inverter composed of a PMOS 32 and an NMOS 33. The output of the inverter is connected to the gate of the PMOS 36 (switch 16) and the gate of the NMOS 35 (switch 15). The source of the PMOS 36 is connected to the power supply terminal 1, and the drain is connected to the fuse 17. The fuse 37, the evaluation target element 19, and the NMOS 35 are connected in series between the output terminal 3 and the ground terminal 2. Note that the evaluation target element 19 and the NMOS 35 are in no particular order. The fuse 37 is not shown in FIG.

  Next, circuit operation will be described. When the voltage at the voltage dividing node 6 becomes higher than the threshold voltage of the NMOS 34, the NMOS 34 is turned on and the drain voltage of the NMOS 34 becomes low. As a result, the output of the inverter composed of the PMOS 32 and the NMOS 33 becomes high, the NMOS 35 is turned on, and the PMOS 36 is turned off. Therefore, a current flows through the evaluation target element 19, and the voltage-current characteristics of the evaluation target element 19 are evaluated using the two terminals of the output terminal 3 and the ground terminal 2. On the other hand, when the voltage at the voltage dividing node 6 becomes lower than the threshold voltage of the NMOS 34, the NMOS 34 is turned off and the drain voltage of the NMOS 34 becomes high, so that the output of the inverter becomes low. As a result, the NMOS 35 is turned off, the PMOS 36 is turned on, and no current flows through the evaluation target element 19 and the PMOS 18, whereby the voltage-current characteristics of the elements in the voltage dividing circuit 13 are evaluated. Note that the PMOS 36 is on in this state, assuming that the elements in the voltage dividing circuit 13 have a higher impedance than the evaluation target element 19. Since the output voltage 3 is not higher than the power supply voltage 1, the gate voltage of the PMOS 18 becomes higher than the source voltage, and the PMOS 18 is turned off. In addition, a current flows from the power supply terminal 1 through the PMOS 36 to the internal circuit 20, but this current does not affect the measurement system connected between the output terminal 3 and the ground terminal 2. The fuse 17, the fuse 38, and the fuse 37 are disconnected after the test is completed, so that the loss of the function of the PMOS 18 that occurs when the PMOS 36 is turned on during the normal operation of the VR is prevented. Not flowing.

  Further, when the logical relationship between the voltage level applied to the output terminal 3 and the opening / closing of the switch 15 and the switch 16 is changed, the inverter composed of the PMOS 32 and the NMOS 33 is removed, or the NMOS 34 and the pull-up resistor 31 are replaced. Further, a PMOS having a source connected to the output terminal 3 and a pull-down resistor are provided, and the polarities of the channels of the NMOS 35 and the PMOS 36 are changed.

Next, the configuration of the voltage dividing circuit 13 will be described with reference to FIGS. 4 and 5. Assuming that the voltage of the voltage dividing node 5 becomes the same potential as the reference voltage 4 and the inversion level of the voltage dividing node 6 becomes the threshold voltage of the NMOS 34, the voltage of the voltage dividing node 5 is divided as shown in FIG. It becomes higher than the voltage of the voltage node 6. However, it may be possible to divide the reference voltage 4 as necessary while the required specification of the output voltage 3 is lowered, and the first divided voltage may be lower than the second divided voltage. I can't even say I don't. Further, the voltage dividing circuit 13 shown in FIG. 5 may be used. The voltage dividing circuit 13 shown in FIG. 5 includes a resistor 41 (Ra), a resistor 42 (Rb) that can be trimmed, a resistor 43 (Rc), and a resistor 44 (Rd). Immediately after the IC is manufactured, since the resistor 42 is short-circuited by the fuse 45, the voltage dividing ratio n1 of the voltage dividing node 5 and the voltage dividing ratio n2 of the voltage dividing node 6 are
n1 = (Rc + Rd) / (Ra + Rc + Rd)
n2 = Rd / (Ra + Rc + Rd)
It becomes. After the initial evaluation, when the fuse is cut and trimming is performed, the voltage dividing ratio n1 ′ of the voltage dividing node 5 and the voltage dividing ratio n2 ′ of the voltage dividing node 6 are
n1 ′ = (Rc + Rd) / (Ra + Rb + Rc + Rd)
n2 ′ = Rd / (Ra + Rb + Rc + Rd)
It becomes. Here, when the maximum value of the output voltage 3 is Vmax and the inversion level of the voltage detector 14 is Vth, the value of each resistor is set so that the following equation is established. Then, the user can test the evaluation target element 19 and the elements in the voltage dividing circuit 13, and in the VR after trimming adjustment, the PMOS 36 can be turned on during normal operation to prevent the loss of the function of the PMOS 18. The current in the path of the NMOS 34 does not flow.
Vmax × n2>Vth> Vmax × n2 ′
For example, when Vmax = 5.0V and Vth = 0.5V, n2> 1/10,
Since n2 ′ <1/10, when Rd = 1, the values of the resistors may be determined so that Ra + Rc + Rd <10 and Ra + Rb + Rc + Rd> 10.
From the above, the voltage dividing ratio of the voltage dividing node 6 is about 1/10.

It is a circuit diagram which shows a voltage regulator. It is a circuit diagram which shows a voltage detector. It is a figure of an internal circuit. It is a figure of a voltage dividing circuit. It is a figure of a voltage dividing circuit.

Explanation of symbols

1 power supply terminal 2 ground terminal 3 output terminal 4 reference voltage 5 voltage dividing node 6 voltage dividing node 11 output transistor 12 error amplifier 13 voltage dividing circuit 14 voltage detector 15, 16 switch 17, 38, 37, 45 fuse 19 evaluation target element 20 Internal circuit 23 Resistance element 24 Constant current source 31 Pull-up resistor 33, 34, 35 NMOS
41, 42, 43, 44 Resistors 18, 32, 36, 21, 22 PMOS

Claims (1)

In a voltage regulator equipped with a function to test the characteristics of internal elements,
A voltage dividing circuit connected between the output terminal and the ground terminal;
A reference voltage circuit;
An error amplifier in which an output of the reference voltage circuit is connected to an inverting input terminal, and a first output of the voltage dividing circuit is connected to a non-inverting input terminal;
An output transistor having a gate connected to the output of the error amplifier, a source connected to a power supply terminal, and a drain connected to the output terminal;
A voltage detector to which a second output of the voltage dividing circuit is input;
A first switch provided between the output terminal and the ground terminal, the opening and closing of which is controlled by the output of the voltage detector;
An evaluation target element provided in series with the first switch between the output terminal and the ground terminal, the electrical characteristics of which are evaluated using the output terminal and the ground terminal by opening and closing the first switch; ,
A second switch provided between the power supply terminal and the gate of the transistor, the opening and closing of which is controlled by the output of the voltage detector;
A source connected to the output terminal, a gate and a drain connected to the second switch, and the transistor from which current from the output terminal is cut off by opening and closing the second switch;
A voltage regulator characterized by comprising:

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