JP2006170898A - Test circuit of semiconductor device - Google Patents

Test circuit of semiconductor device Download PDF

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JP2006170898A
JP2006170898A JP2004366177A JP2004366177A JP2006170898A JP 2006170898 A JP2006170898 A JP 2006170898A JP 2004366177 A JP2004366177 A JP 2004366177A JP 2004366177 A JP2004366177 A JP 2004366177A JP 2006170898 A JP2006170898 A JP 2006170898A
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voltage
semiconductor device
test
regulator
circuit
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JP5004418B2 (en
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Tadayoshi Ueda
忠義 植田
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Ricoh Co Ltd
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Ricoh Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a test circuit of a semiconductor device for entering into a test mode for testing a mounted function without a dedicated test terminal. <P>SOLUTION: In the semiconductor device for mounting a regulator 1, a voltage detector 2 is provided and detects a voltage higher than a predetermined voltage at a constant voltage output terminal of the regulator 1, and the test circuit of the semiconductor device is constituted and uses an output from the voltage detector 2 as a test mode signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置において、専用のテスト端子を設けることなくテストモードの設定を行う、半導体装置を検査するための半導体装置のテスト回路に関する。   The present invention relates to a test circuit for a semiconductor device for inspecting a semiconductor device, which sets a test mode without providing a dedicated test terminal in the semiconductor device.

近年、半導体装置における多ピン化、高機能化、高集積化が顕著である。このような半導体装置は、回路機能を設定されたテストパターンによって、その回路動作状態を評価する必要がある。よって、論理演算等を実行する通常の動作モードに加えて、集積回路自体の機能の良否を判定するためのテストモードを備えており、テストモード設定用のテスト端子が設けられている。   In recent years, the increase in the number of pins, high functionality, and high integration in a semiconductor device have been remarkable. Such a semiconductor device needs to evaluate the circuit operation state based on a test pattern in which a circuit function is set. Therefore, in addition to a normal operation mode for executing a logical operation or the like, a test mode for determining the quality of the integrated circuit itself is provided, and a test terminal for setting the test mode is provided.

一方、半導体装置の端子数には限りがあり、特に高密度実装の機器に搭載される半導体装置の要求には１本でも端子数を減らし、端子数を最小限にしなければならないという現状がある。このような状況の下、特許文献１には、複数のテスト端子を設けるのではなく、ゲート用のテスト端子のみで多数のテストモードを設定可能とする技術が開示されている。
特開平６−２０１７９４号公報 On the other hand, the number of terminals of a semiconductor device is limited. In particular, the demand for a semiconductor device mounted on a high-density mounting device requires that the number of terminals be reduced and the number of terminals must be minimized. . Under such circumstances, Patent Document 1 discloses a technique that enables setting of a large number of test modes using only gate test terminals instead of providing a plurality of test terminals.
JP-A-6-201794

しかし、特許文献１に開示されている技術においても、半導体装置において専用のテスト端子が設置される必要がある。   However, even in the technique disclosed in Patent Document 1, it is necessary to install a dedicated test terminal in the semiconductor device.

本発明は、上記のような問題点に鑑み、搭載された機能をテストするためのテストモードへの移行を専用のテスト端子を用いることなく行うことができるようにする半導体装置のテスト回路を提供することを目的とする。   SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a test circuit for a semiconductor device that enables a transition to a test mode for testing a mounted function without using a dedicated test terminal. The purpose is to do.

請求項１記載の発明は、レギュレータを搭載した半導体装置であって、前記レギュレータの定電圧出力端子電圧が規定電圧よりも高くなったことを検出する電圧ディテクタを具備し、前記電圧ディテクタの出力をテストモード信号として使用する半導体装置のテスト回路としたことを特徴とする。   The invention described in claim 1 is a semiconductor device equipped with a regulator, comprising a voltage detector for detecting that the constant voltage output terminal voltage of the regulator is higher than a specified voltage, and outputting the output of the voltage detector. The semiconductor device test circuit is used as a test mode signal.

請求項２記載の発明は、複数のレギュレータに対し、それぞれ電圧ディテクタを設け、その論理和信号をテストモード信号として使用する請求項１記載の半導体装置のテスト回路としたことを特徴とする。   According to a second aspect of the present invention, there is provided a test circuit for a semiconductor device according to the first aspect in which a voltage detector is provided for each of the plurality of regulators and the logical sum signal is used as a test mode signal.

請求項３記載の発明は、前記レギュレータと前記電圧ディテクタにおいて、分圧抵抗及び基準電圧の少なくとも一方を共通化した請求項１又は２に記載の半導体装置のテスト回路としたことを特徴とする。   According to a third aspect of the present invention, there is provided a test circuit for a semiconductor device according to the first or second aspect, wherein the regulator and the voltage detector share at least one of a voltage dividing resistor and a reference voltage.

本発明によれば、搭載された機能をテストするためのテストモードへの移行を専用のテスト端子を用いることなく行うことができるようにする半導体装置のテスト回路を実現することができる。   According to the present invention, it is possible to realize a test circuit for a semiconductor device that can shift to a test mode for testing a mounted function without using a dedicated test terminal.

本発明を実施するための最良の形態は、レギュレータを搭載した半導体装置において、上記レギュレータの定電圧出力端子電圧が規定電圧よりも高くなったことを検出する電圧ディテクタを設けて、この電圧ディテクタの出力をテストモード信号として使用する半導体装置のテスト回路を構成する。   The best mode for carrying out the present invention is to provide a voltage detector for detecting that the constant voltage output terminal voltage of the regulator is higher than a specified voltage in a semiconductor device equipped with a regulator. A test circuit of a semiconductor device that uses an output as a test mode signal is configured.

以下に、本発明の好適な実施形態を添付図面に基づいて詳細に説明する。尚、以下に述べる実施形態は本発明の好適な具体例であるから、技術的に好ましい種々の限定が付されているが、本発明の範囲は、以下の説明において特に本発明を限定する旨の記載がない限り、これらの実施形態に限られるものではない。   Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. The embodiments described below are preferable specific examples of the present invention, and thus various technically preferable limitations are given. However, the scope of the present invention is particularly limited in the following description. Unless otherwise described, the present invention is not limited to these embodiments.

（第１の実施形態）
図１に、本実施形態の半導体テスト回路の回路構成を示す。レギュレータ１と、その定電圧出力端子の電圧を検出する電圧ディテクタ２があり、電圧ディテクタ２の検出信号を他の回路３のテストモード信号としている。
図２に、レギュレータ１の出力電圧と電圧ディテクタ２の検出電圧の関係を示す。
レギュレータ１の出力電圧は電源電圧がある電圧以上では一定となる。電圧ディテクタ２の検出電圧は、その電圧よりも高い電圧としてあり、通常の使用状態では電圧ディテクタ２が、レギュレータ１の出力電圧を検出することはない。 (First embodiment)
FIG. 1 shows a circuit configuration of the semiconductor test circuit of the present embodiment. There is a regulator 1 and a voltage detector 2 for detecting the voltage at its constant voltage output terminal. The detection signal of the voltage detector 2 is used as a test mode signal for another circuit 3.
FIG. 2 shows the relationship between the output voltage of the regulator 1 and the detection voltage of the voltage detector 2.
The output voltage of the regulator 1 is constant above the power supply voltage. The detection voltage of the voltage detector 2 is higher than that voltage, and the voltage detector 2 does not detect the output voltage of the regulator 1 in a normal use state.

本実施形態によれば、レギュレータ１の低電圧出力端子から強制的に電圧ディテクタ２の検出電圧以上の電圧を印加することにより、電圧ディテクタ２が電圧を検出し、検出信号を出力する。これをテストモード信号として使用する。
本実施形態の構成により、レギュレータ１の出力端子をテストモードへの移行に使用するため、専用のテスト端子を設けることなく、テストモードへの移行が可能となる。 According to the present embodiment, the voltage detector 2 detects a voltage and outputs a detection signal by forcibly applying a voltage higher than the detection voltage of the voltage detector 2 from the low voltage output terminal of the regulator 1. This is used as a test mode signal.
With the configuration of the present embodiment, since the output terminal of the regulator 1 is used for shifting to the test mode, it is possible to shift to the test mode without providing a dedicated test terminal.

（第２の実施形態）
図３に、本実施形態の半導体テスト回路の回路構成を示す。ここで、レギュレータの定電圧出力端子から強制的に電圧を印加すると、そのレギュレータはテストモードでテストすることができなくなる。
よって、図３に示すように、複数のレギュレータ４、５の出力に対し、電圧ディテクタ６、７を設け、それらの出力をテストモード信号として使用する。具体的には、テストしたいレギュレータと異なるレギュレータの出力に電圧を強制印加することにより、全てのレギュレータ４、５をテストモードでテストすることが可能となる。
本実施形態の構成により、テストモードへの移行により使用できなくなるレギュレータが無くなり、全ての回路をテストモードでテストすることが可能となる。 (Second Embodiment)
FIG. 3 shows a circuit configuration of the semiconductor test circuit of the present embodiment. Here, if a voltage is forcibly applied from the constant voltage output terminal of the regulator, the regulator cannot be tested in the test mode.
Therefore, as shown in FIG. 3, voltage detectors 6 and 7 are provided for the outputs of a plurality of regulators 4 and 5, and these outputs are used as test mode signals. Specifically, it is possible to test all the regulators 4 and 5 in the test mode by forcibly applying a voltage to the output of a regulator different from the regulator to be tested.
According to the configuration of the present embodiment, there is no regulator that cannot be used by shifting to the test mode, and all circuits can be tested in the test mode.

（第３の実施形態）
図４に、本実施形態の半導体テスト回路の回路構成を示す。レギュレータ９とディテクタ１０は、出力電圧を分圧して基準電圧と比較するという点では共通している。そのため、分圧抵抗、及び、基準電圧を共通化して回路規模を小さくすることが可能である。図４に示す本実施形態の構成により、テストモードへの移行に必要な追加回路の規模を最小限に抑えることが可能となる。 (Third embodiment)
FIG. 4 shows a circuit configuration of the semiconductor test circuit of the present embodiment. The regulator 9 and the detector 10 are common in that the output voltage is divided and compared with a reference voltage. For this reason, it is possible to reduce the circuit scale by sharing the voltage dividing resistor and the reference voltage. The configuration of the present embodiment shown in FIG. 4 makes it possible to minimize the scale of additional circuits necessary for shifting to the test mode.

第１の実施形態の半導体テスト回路の回路構成を示す図である。It is a figure which shows the circuit structure of the semiconductor test circuit of 1st Embodiment. 第１の実施形態の半導体テスト回路におけるレギュレータの出力電圧と電圧ディテクタの検出電圧の関係を示す図である。It is a figure which shows the relationship between the output voltage of a regulator and the detection voltage of a voltage detector in the semiconductor test circuit of 1st Embodiment. 第２の実施形態の半導体テスト回路の回路構成を示す図である。It is a figure which shows the circuit structure of the semiconductor test circuit of 2nd Embodiment. 第３の実施形態の半導体テスト回路の回路構成を示す図である。It is a figure which shows the circuit structure of the semiconductor test circuit of 3rd Embodiment.

符号の説明Explanation of symbols

１ レギュレータ
２ 電圧ディテクタ
３ その他の回路
４ レギュレータ
５ レギュレータ
６ 電圧ディテクタ
７ 電圧ディテクタ
８ その他の回路
９ レギュレータ
１０ 電圧ディテクタ DESCRIPTION OF SYMBOLS 1 Regulator 2 Voltage detector 3 Other circuit 4 Regulator 5 Regulator 6 Voltage detector 7 Voltage detector 8 Other circuit 9 Regulator 10 Voltage detector

Claims (3)

レギュレータを搭載した半導体装置であって、
前記レギュレータの定電圧出力端子電圧が規定電圧よりも高くなったことを検出する電圧ディテクタを具備し、
前記電圧ディテクタの出力をテストモード信号として使用することを特徴とする半導体装置のテスト回路。 A semiconductor device equipped with a regulator,
A voltage detector for detecting that the constant voltage output terminal voltage of the regulator is higher than a specified voltage;
A test circuit for a semiconductor device, wherein the output of the voltage detector is used as a test mode signal. 複数のレギュレータに対し、それぞれ電圧ディテクタを設け、その論理和信号をテストモード信号として使用することを特徴とする請求項１記載の半導体装置のテスト回路。   2. The test circuit for a semiconductor device according to claim 1, wherein a voltage detector is provided for each of the plurality of regulators, and the logical sum signal is used as a test mode signal. 前記レギュレータと前記電圧ディテクタにおいて、分圧抵抗及び基準電圧の少なくとも一方を共通化したことを特徴とする請求項１又は２に記載の半導体装置のテスト回路。   3. The test circuit for a semiconductor device according to claim 1, wherein at least one of a voltage dividing resistor and a reference voltage is shared by the regulator and the voltage detector.
JP2004366177A 2004-12-17 2004-12-17 Semiconductor device test circuit Expired - Fee Related JP5004418B2 (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008140113A (en) * 2006-12-01 2008-06-19 Seiko Instruments Inc Voltage regulator
WO2008120488A1 (en) * 2007-03-29 2008-10-09 Kyushu Institute Of Technology Electronic circuit device
JP2009198247A (en) * 2008-02-20 2009-09-03 Mitsumi Electric Co Ltd Multifunction semiconductor integrated circuit with built-in timer
JP2009257897A (en) * 2008-04-16 2009-11-05 Mitsumi Electric Co Ltd Semiconductor integrated circuit with built-in timer
JP2021056030A (en) * 2019-09-27 2021-04-08 株式会社ケーヒン Current detector and data write method

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Publication number Priority date Publication date Assignee Title
JPH05232197A (en) * 1992-02-18 1993-09-07 Nippon Telegr & Teleph Corp <Ntt> Integrated circuit and testing method for same
JPH09304481A (en) * 1996-05-17 1997-11-28 Nissan Motor Co Ltd Onboard screening apparatus
JPH11224500A (en) * 1998-02-06 1999-08-17 Mitsubishi Electric Corp Semiconductor memory
JPH11283400A (en) * 1998-03-31 1999-10-15 Sanyo Electric Co Ltd Nonvolatile memory and microcomputer incorporating it
JP2000266817A (en) * 1999-03-17 2000-09-29 Rohm Co Ltd Semiconductor integrated-circuit device with test function
JP2000308251A (en) * 1999-04-19 2000-11-02 Ricoh Co Ltd Apparatus for monitoring overcurrent of control circuit element
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008140113A (en) * 2006-12-01 2008-06-19 Seiko Instruments Inc Voltage regulator
WO2008120488A1 (en) * 2007-03-29 2008-10-09 Kyushu Institute Of Technology Electronic circuit device
JP2008250576A (en) * 2007-03-29 2008-10-16 Kyushu Institute Of Technology Electronic circuit device
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JP2009198247A (en) * 2008-02-20 2009-09-03 Mitsumi Electric Co Ltd Multifunction semiconductor integrated circuit with built-in timer
JP2009257897A (en) * 2008-04-16 2009-11-05 Mitsumi Electric Co Ltd Semiconductor integrated circuit with built-in timer
JP2021056030A (en) * 2019-09-27 2021-04-08 株式会社ケーヒン Current detector and data write method
JP7175867B2 (en) 2019-09-27 2022-11-21 日立Astemo株式会社 Current detection device and data writing method

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