CN114705904A - High-precision overcurrent detection circuit - Google Patents

High-precision overcurrent detection circuit Download PDF

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Publication number
CN114705904A
CN114705904A CN202210379145.1A CN202210379145A CN114705904A CN 114705904 A CN114705904 A CN 114705904A CN 202210379145 A CN202210379145 A CN 202210379145A CN 114705904 A CN114705904 A CN 114705904A
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switch tube
switching tube
tube
current
sampling
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CN114705904B (en
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不公告发明人
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Suzhou Baker Microelectronics Co Ltd
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Suzhou Baker Microelectronics Co Ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16566—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
    • G01R19/16571—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 comparing AC or DC current with one threshold, e.g. load current, over-current, surge current or fault current
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/30—Structural combination of electric measuring instruments with basic electronic circuits, e.g. with amplifier

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Measurement Of Current Or Voltage (AREA)

Abstract

The application comprises a high-precision overcurrent detection circuit, and particularly relates to the technical field of current detection. The circuit comprises a power switch tube, a sampling switch tube, a target comparator and a cascode current mirror; the source electrode of the power switch tube is connected with the power supply input end; the drain electrode of the power switch tube is connected with the inverting input end of the target comparator; the source electrode of the sampling switch tube is connected with the power supply input end; the drain electrode of the sampling switch tube is connected with the non-inverting input end of the target comparator; the grid electrode of the sampling switch tube is connected with the grid electrode of the power switch tube; the power supply input end is grounded through the active end of the cascode current mirror; the drain electrode of the sampling switch tube is grounded through the passive end of the cascode current mirror. The circuit avoids the mirror current proportion maladjustment caused by overlarge voltage difference between the drain voltages of the sampling switch tube and the power switch tube, and improves the accuracy of overcurrent detection.

Description

High-precision overcurrent detection circuit
Technical Field
The invention relates to the technical field of current detection, in particular to a high-precision overcurrent detection circuit.
Background
In a circuit structure in the prior art, it is generally necessary to detect a current and generate a control signal according to a detection result of the current to control a circuit, so as to ensure stable operation of the circuit.
As shown in FIG. 1, an overcurrent detection device commonly used in an integrated circuit chip is characterized in that Mp1 is a power tube responsible for outputting current, Ms1 is a sampling tube, k1 is the width ratio of Mp1 to Ms1, and k1 is the width ratio of Mp1 to Ms1>>1，Io1And Vo1Respectively an output current and an output voltage, Is1And Vs1Respectively a sampled current and a sampled voltage. In thatIn the detection process, the output current is sampled firstly, and the obtained sampling current is is1Then let the sampling current isFlows into the sampling resistor rs to generate a sampling voltage Vs1Then the voltage V is sampleds1A positive input terminal of the comparator, and a reference voltage V connected to the negative input terminal of the comparatorref1Comparing, the output voltage of the comparator is Vc1Is a logic signal; if Io1Is very large and can result in Is1And Vs1Is also very large when Vs1Exceeds Vref1When, Vc1And when the voltage is high, the power supply circuit can be turned off, so that the power supply circuit and the following electrical appliances are protected from being burnt out.
However, in the above scheme, the drain voltages of Mp1 and Ms1 are different and are respectively Vo1And Vs1The voltage difference between the two is large and uncontrollable, so that the mirror current proportion of Mp1 and Ms1 is not completely equal to k1:1, and the detection accuracy of the current is low.
Disclosure of Invention
The embodiment of the application provides a high-precision overcurrent detection circuit, which improves the overcurrent detection precision and comprises a power switch tube, a sampling switch tube, a target comparator and a cascode current mirror;
the source electrode of the power switch tube is connected with the power supply input end; the drain electrode of the power switch tube is connected with the inverted input end of the target comparator;
the source electrode of the sampling switch tube is connected with the power supply input end; the drain electrode of the sampling switch tube is connected with the non-inverting input end of the target comparator; the grid electrode of the sampling switch tube is connected with the grid electrode of the power switch tube;
the power supply input end is grounded through an active end of the cascode current mirror;
and the drain electrode of the sampling switch tube is grounded through the passive end of the cascode current mirror.
In one possible implementation manner, the passive end of the cascode current mirror includes a first switching tube and a third switching tube; and the drain electrode of the first switching tube is connected with the source electrode of the third switching tube.
In one possible implementation manner, the active end of the cascode current mirror includes a reference current source, a second switching tube and a fourth switching tube; and the drain electrode of the second switch tube is connected with the source electrode of the fourth switch tube.
In a possible implementation manner, the grid electrode of the second switching tube is connected with the grid electrode of the first switching tube; the grid electrode of the second switching tube is connected with the drain electrode of the second switching tube;
the grid electrode of the fourth switching tube is connected with the grid electrode of the third switching tube; and the grid electrode of the fourth switching tube is connected with the drain electrode of the fourth switching tube.
In one possible implementation, the power supply input is grounded through an active terminal of the cascode current mirror, and the power supply input includes:
and the source electrode of the second switch tube is grounded, so that the power supply input end is grounded through the reference current source, the fourth switch tube and the second switch tube in sequence.
In one possible implementation, the drain of the sampling switch tube is grounded through the passive end of the cascode current mirror, and the method includes:
the drain electrode of the sampling switch tube is connected to the drain electrode of the third switch tube, and the source electrode of the first switch tube is grounded, so that the drain electrode of the sampling switch tube is grounded through the third switch tube and the first switch tube in sequence.
In one possible implementation manner, the channel width ratio of the power switch tube to the sampling switch tube is k, and k is greater than 1.
In a possible implementation manner, the power switch tube and the sampling switch tube are PMOS tubes.
In a possible implementation manner, the circuit further includes a first current source and a fifth switching tube;
the power supply input end is connected to the drain electrode of the fourth switching tube sequentially through the first current source and the fifth switching tube;
and the grid electrode of the fifth switching tube is connected with the output end of the target comparator.
In a possible implementation manner, the power input terminal is connected to the drain of the fourth switching tube sequentially through the first current source and the fifth switching tube, and the method includes:
the power input end is connected to a source electrode of the fifth switching tube through a first current source, and a drain electrode of the fifth switching tube is connected with a drain electrode of the fourth switching tube, so that the power input end is connected to the drain electrode of the fourth switching tube through the first current source and the fifth switching tube in sequence;
and the fifth switch tube is a PMOS tube.
The technical scheme provided by the application can comprise the following beneficial effects:
in the current detection circuit, through the characteristics of the target comparator, the cascode current mirror structure and the cascode amplifier structure formed by the passive end in the cascode current mirror and the sampling switch tube, the value of the sampling voltage is accurately equal to the value of the output voltage in a critical state, therefore, the ratio of the sampling current to the output current is accurately equal to the ratio of the mirror image current, meanwhile, the current value of the active end in the cascode current mirror can be accurately copied to the passive end, and the current flowing through the passive end is equal to the sampling current on the sampling switch tube, thereby the value of the sampling current is accurately controlled, therefore, the circuit structure ensures that the drain voltage of the sampling switch tube is accurately equal to the drain voltage of the power switch tube in the critical state in the current detection process, and avoids the mirror image current ratio imbalance caused by overlarge voltage difference between the drain voltage of the sampling switch tube and the drain voltage of the power switch tube, the accuracy of overcurrent detection is improved; in addition, the delay control circuit is added in the judgment of over-current and no over-current, so that the oscillation of the circuit is reduced, and the accuracy of current detection is further improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of an overcurrent detection device commonly used in an integrated circuit chip.
Fig. 2 is a schematic diagram illustrating a high-precision overcurrent detection circuit according to an exemplary embodiment of the present application.
Fig. 3 is a schematic diagram illustrating a high-precision overcurrent detection circuit according to an exemplary embodiment of the present application.
Detailed Description
The technical solutions of the present application will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the embodiments of the present application, the term "correspond" may indicate that there is a direct correspondence or an indirect correspondence between the two, may also indicate that there is an association between the two, and may also indicate and be indicated, configure and configured, and so on.
Fig. 2 is a schematic diagram of a high-precision overcurrent detection circuit according to an exemplary embodiment of the application. As shown in fig. 2, the circuit includes a power switch tube Mp, a sampling switch tube Ms, a target comparator a1, and a cascode current mirror;
the source electrode of the power switch tube Mp is connected with the power supply input end; the drain electrode of the power switching tube Mp is connected with the inverting input end of the target comparator A1;
the source electrode of the sampling switch tube Ms is connected with the power supply input end; the drain electrode of the sampling switch tube Ms is connected with the non-inverting input end of the target comparator A1; the grid electrode of the sampling switch tube Ms is connected with the grid electrode of the power switch tube Mp;
the power input end VddGrounding (gnd) through an active end of the cascode current mirror;
the drain electrode of the sampling switch tube Ms is grounded through the passive end of the cascode current mirror.
Optionally, as shown in fig. 2, the passive end of the cascode current mirror includes a first switching tube M1 and a third switching tube M3; the drain of the first switching tube M1 is connected to the source of the third switching tube M3.
Optionally, as shown in fig. 2, the active end of the cascode current mirror includes a reference current source IrefA second switch tube M2 and a fourth switch tube M4; the drain of the second switching tube M2 is connected to the source of the fourth switching tube M4.
Optionally, as shown in fig. 2, the gate of the second switching tube M2 is connected to the gate of the first switching tube M1; the grid electrode of the second switch tube M2 is connected with the drain electrode of the second switch tube M2;
the grid electrode of the fourth switching tube M4 is connected with the grid electrode of the third switching tube M3; the gate of the fourth switching tube M4 is connected to the drain of the fourth switching tube M4.
Optionally, as shown in fig. 2, the source of the second switch M2 is grounded, so that the power input terminal V is connected to groundddSequentially passes through the reference current source IrefThe fourth switching tube M4 and the second switching tube M2 are grounded.
Optionally, as shown in fig. 2, the drain of the sampling switch tube Ms is connected to the drain of the third switch tube, and the source of the first switch tube M1 is grounded, so that the drain of the sampling switch tube Ms is grounded through the third switch tube M3 and the first switch tube M1 in sequence.
Optionally, as shown in fig. 2, a channel width ratio of the power switching tube Mp to the sampling switching tube Ms is k, and k is greater than 1.
Optionally, as shown in fig. 2, the power switch tube Mp and the sampling switch tube Ms are PMOS tubes.
The operation principle of the overcurrent detection circuit shown in fig. 2 is explained below.
In one aspectWhen the current in the power switch tube in the overcurrent detection circuit is in the non-overcurrent state, as shown in fig. 2, the gate control voltage V on the power switch tube Mp and the sampling switch tube Ms is the same as the gate control voltage V on the power switch tube MpgEqual to the power supply input voltage VddThe voltage V between the power switch tube Mp and the grid source of the sampling switch tube Msgs1All 0, the power switch tube Mp and the sampling switch tube Ms are in cut-off state, and the current I on the power switch tube at the momentoAnd sampling the current I on the switch tubesSatisfy Io＝IsWhen the voltage V is equal to 0, the drain currents of the third switching tube M3 and the first switching tube M1 are also zero, so the voltage V at the drain of the sampling switching tube Ms is zerosIs necessarily 0, otherwise current must flow in the cascode current mirror, due to VsIs 0, so when VsWhen the output signal is inputted to the non-inverting input terminal of the target comparator A1, the output of the target comparator A1, i.e., the output signal V of the overcurrent detection circuitcLow, it means that the output current in the power switch tube Mp is not over-current.
On the other hand, when the current in the power switching tube Mp in the overcurrent detection circuit is in a critical state, i.e., when the gate control voltage V is appliedgFrom the mains input voltage VddWhen the voltage is reduced, the voltage between the Mp grid source of the power switch tube is increased, so that the output current I on the power switch tube is increasedoIncreasing, so that the sampling current I on the sampling switch tubesAlso increases; meanwhile, the fourth switching tube M4 and the second switching tube M2 are connected with the reference current source IrefThe current flowing through the fourth switching tube M4 and the second switching tube M2 is constant and is always the reference current source IrefSo that the voltage V between the gate and the source of the fourth switching tube M4 and the second switching tube M2gs2The grid voltages of the fourth switching tube M4 and the second switching tube M2 are also unchanged all the time, and the grid voltages of the third switching tube M3 and the first switching tube M1 are also unchanged all the time because the third switching tube M3 is connected with the grid of the fourth switching tube M4 and the first switching tube M1 is connected with the grid of the second switching tube M2;
so as to sample the current IsWhen added, there are several possibilities:
1. if the voltage V is sampledsThe gate voltages of the third switching tube M3 and the first switching tube M1 are not changed, so that the current flowing through the third switching tube M3 and the first switching tube M1 is also not changed; meanwhile, since the non-inverting input terminal and the inverting input terminal of the comparator cannot flow current, the sampling current IsAll flow into the third switch tube M3 and the first switch tube M1, so that the current I is sampledsCurrent I flowing through the third switching tubem3And a current I flowing through the first switching tubem1Satisfy Is＝Im3＝Im1It is obviously not possible to sample the current IsIncreasing the current flowing through the third switch tube M3 and the first switch tube M1;
2. if the voltage V is sampledsThe gate voltages of the third switching tube M3 and the first switching tube M1 are always unchanged, so that the current flowing through the third switching tube M3 and the first switching tube M1 is reduced at this time; meanwhile, as the non-inverting input end and the inverting input end of the comparator can not flow current, the sampling current IsAll flow into the third switch tube M3 and the first switch tube M1, so that the sampling current IsCurrent I flowing through the third switching tubem3And a current I flowing through the first switch tubem1Satisfy Is＝Im3＝Im1It is obviously not possible to sample the current IsThe current flowing through the third switch tube M3 and the first switch tube M1 is increased, but decreased;
3. if the voltage V is sampledsThe gate voltages of the third switching tube M3 and the first switching tube M1 are always unchanged, so that the current flowing through the third switching tube M3 and the first switching tube M1 is increased; meanwhile, since the non-inverting input terminal and the inverting input terminal of the comparator cannot flow current, the sampling current IsAll flow into the third switch tube M3 and the first switch tube M1, so that the current I is sampledsCurrent I flowing through the third switching tubem3And a current I flowing through the first switching tubem1Satisfy Is＝Im3＝Im1It is apparent that, at this time, the current is sampledIsAnd the current flowing through the third switching tube M3 increases simultaneously with the current flowing through the first switching tube M1.
As can be seen from the above analysis, the first switching tube M1, the second switching tube M2, the third switching tube M3, and the fourth switching tube M4 together form a cascode current mirror structure, and the sampling switching tube Ms, the third switching tube M3, and the first switching tube M1 form a common-source amplifier structure, so that the gate control voltage V is enabled to be controlledgDecrease, output current IoWhile increasing, the current I is sampledsIncreasing, sampling voltage VsAnd also increases.
When sampling voltage VsIncrease to an output voltage VoSampling current I in time sampling switch tube MssCan be very accurately equal to the output current Io1/k of (I)s＝IoK is; and at this time, due to Vs＝VoAnd assume V at this timeo(e.g. V)o>0.5V) can make the four MOS transistors (the first switching transistor M1, the second switching transistor M2, the third switching transistor M3 and the fourth switching transistor M4) of the cascode current mirror all work in the saturation region, so that the reference current source I is in this caserefThe current value can be very accurately copied to the third switching tube M3, and the current I flowing through the third switching tube M3m3Equal to the sampling current I on the sampling switch tube MssThus sampling the current IsCurrent I flowing through the third switching tubem3And a current I flowing through the first switching tubem1Satisfy Is＝Im3＝Iref；
In summary, in the critical state, Vs＝Vo，Iref＝IoK, the critical voltage of the gate control voltage is Vg0；
Therefore, if the gate control voltage V is appliedgFrom the critical voltage Vg0Increase, output current IoWhile reducing, sampling the current IsReducing, sampling voltage VsIs also reduced; if the gate control voltage V is appliedgFrom the critical voltage Vg0Decrease, output current IoAt the time of increase, sampling current IsIncreasing, sampling voltage VsAnd also increases.
On the other hand, when the current in the power switch tube in the overcurrent detection circuit is in an overcurrent state, namely when the grid control voltage VgContinuously decrease to output current IoWhile continuing to increase, the current I is sampledsAlso continues to increase, sampling voltage VsThe increase is also continued; therefore, at this time, Vs>VoThe output of the target comparator A1, i.e. the output signal V of the overcurrent detection circuitcHigh represents that the output current in the power switch tube Mp is in an overcurrent state.
In particular, assume Iref20mA, k is 20; therefore, when Io＝k*IrefWhen 400mA, Vo＝VsThe gate control voltage has a threshold voltage of Vg0；
When I isoBelow 400mA, VgGreater than the critical voltage Vg0In addition, since the first switching tube M1, the second switching tube M2, the third switching tube M3 and the fourth switching tube M4 jointly form a cascode current mirror structure, and the sampling switching tube Ms, the third switching tube M3 and the first switching tube M1 form a common source amplifier structure, V is a voltage source of the cascode current mirror structuregIs increased to result in VsIs reduced, so that, Vs<VoOutput signal V of the overcurrent detection circuitcLow, no overcurrent in the circuit;
when I isoAbove 400mA, VgLess than the critical voltage Vg0In addition, since the first switching tube M1, the second switching tube M2, the third switching tube M3 and the fourth switching tube M4 jointly form a cascode current mirror structure, and the sampling switching tube Ms, the third switching tube M3 and the first switching tube M1 form a cascode amplifier structure, V is a voltage source of the cascode amplifiergIs reduced to result in VsSo that at this time, Vs>VoOutput signal V of the overcurrent detection circuitcHigh, the circuit is over-current.
In summary, in the current detection circuit, through the characteristics of the target comparator, the cascode current mirror structure, and the cascode amplifier structure formed by the passive end of the cascode current mirror and the sampling switch tube, the value of the sampling voltage is accurately equal to the value of the output voltage in the critical state, so that the ratio of the sampling current to the output current is accurately equal to the ratio of the mirror current, meanwhile, the current value of the active end of the cascode current mirror can be accurately copied to the passive end, and the current flowing through the passive end is equal to the sampling current on the sampling switch tube, so that the value of the sampling current is accurately controlled, therefore, in the current detection process, in the critical state, the drain voltage of the sampling switch tube is accurately equal to the drain voltage of the power switch tube, and the mirror current ratio imbalance caused by the overlarge voltage difference between the drain voltage of the sampling switch tube and the drain voltage of the power switch tube is avoided, the accuracy of overcurrent detection is improved.
Fig. 3 is a schematic diagram illustrating a high-precision overcurrent detection circuit according to an exemplary embodiment of the present application. As shown in FIG. 3, the circuit includes a first current source I in addition to the structure of the high-precision overcurrent detecting circuit shown in FIG. 2hAnd a fifth switching tube M5;
the power input end passes through the first current source I in turnhThe fifth switching tube M5 is connected to the drain of the fourth switching tube M4;
the gate of the fifth switch transistor M5 is connected to the output terminal of the target comparator a 1.
Optionally, the power input terminal is connected to the first current source IhIs connected to the source of the fifth switching transistor M5, and the drain of the fifth switching transistor M5 is connected to the drain of the fourth switching transistor M4, so that the power input terminal passes through the first current source I in sequencehThe fifth switching tube M5 is connected to the drain of the fourth switching tube M4;
the fifth switch tube is a PMOS tube.
As can be seen from the description of the embodiment shown in FIG. 2, the high-precision overcurrent detection circuit shown in FIG. 2 has k × I for overcurrent or overcurrent of the output currentrefIs determined by the boundary, so that when the output current reaches k × IrefWhen nearby, the overcurrent detection circuit is caused to switch between outputting the overcurrent signal and outputting the overcurrent signal, so that the output current is at k × IrefNearby oscillation occurs to affect over-current detectionThe precision of the measurement circuit;
therefore, in this case, the high-precision overcurrent detection circuit shown in fig. 3 can be formed by adding a delay control circuit to the high-precision overcurrent detection circuit shown in fig. 2, so as to improve the oscillation of the output current and improve the detection accuracy;
the operation principle of the high-precision overcurrent detection circuit shown in fig. 3 is as follows:
1. when the output current of the circuit is not over-current, the output signal V of the over-current detection circuitcAt low, the delay controls the conduction of the fifth switch transistor M5, and the first current source IhFlows into the fourth switch tube M4, so the current flowing through the fourth switch tube M4 is Iref+IhTherefore, when the current I is outputoTo k (I)ref+Ih) The overcurrent detection circuit only judges the overcurrent, and the output signal V of the overcurrent detection circuitcGo high;
2. when the output current of the circuit is over-current, the output signal V of the over-current detection circuitcGoes high, the delay control fifth switch tube M5 is turned off, and the first current source IhCannot flow into the fourth switching tube M4, so the current flowing through the fourth switching tube M4 is IrefSo as to output a current IoIs lower than k x IrefWhen the overcurrent is detected, the overcurrent detection circuit judges that the overcurrent is not generated, and the output signal V of the overcurrent detection circuitcGo low;
from the above analysis, it can be known that the delay control circuit is added in the judgment of over-current and no-over-current, so that the oscillation of the circuit is reduced, and the detection accuracy is improved.
In summary, in the current detection circuit, through the characteristics of the target comparator, the cascode current mirror structure, and the cascode amplifier structure formed by the passive end of the cascode current mirror and the sampling switch tube, the value of the sampling voltage is accurately equal to the value of the output voltage in the critical state, so that the ratio of the sampling current to the output current is accurately equal to the ratio of the mirror current, meanwhile, the current value of the active end of the cascode current mirror can be accurately copied to the passive end, and the current flowing through the passive end is equal to the sampling current on the sampling switch tube, so that the value of the sampling current is accurately controlled, therefore, in the current detection process, in the critical state, the drain voltage of the sampling switch tube is accurately equal to the drain voltage of the power switch tube, and the mirror current ratio imbalance caused by the overlarge voltage difference between the drain voltage of the sampling switch tube and the drain voltage of the power switch tube is avoided, the accuracy of overcurrent detection is improved; in addition, the delay control circuit is added in the judgment of over-current and no over-current, so that the oscillation of the circuit is reduced, and the accuracy of current detection is further improved.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (10)

1. The high-precision overcurrent detection circuit is characterized by comprising a power switch tube, a sampling switch tube, a target comparator and a cascode current mirror;
the source electrode of the power switch tube is connected with the power supply input end; the drain electrode of the power switch tube is connected with the inverted input end of the target comparator;
the source electrode of the sampling switch tube is connected with the power supply input end; the drain electrode of the sampling switch tube is connected with the non-inverting input end of the target comparator; the grid electrode of the sampling switch tube is connected with the grid electrode of the power switch tube;
the power supply input end is grounded through an active end of the cascode current mirror;
and the drain electrode of the sampling switch tube is grounded through the passive end of the cascode current mirror.
2. The circuit of claim 1, wherein the passive end of the cascode current mirror comprises a first switching tube and a third switching tube; and the drain electrode of the first switching tube is connected with the source electrode of the third switching tube.
3. The circuit of claim 2, wherein the active terminal of the cascode current mirror comprises a reference current source, a second switching tube and a fourth switching tube; and the drain electrode of the second switching tube is connected with the source electrode of the fourth switching tube.
4. The circuit of claim 3, wherein the gate of the second switch tube is connected to the gate of the first switch tube; the grid electrode of the second switching tube is connected with the drain electrode of the second switching tube;
the grid electrode of the fourth switching tube is connected with the grid electrode of the third switching tube; and the grid electrode of the fourth switching tube is connected with the drain electrode of the fourth switching tube.
5. The circuit of claim 4, wherein the power supply input is grounded through an active terminal of the cascode current mirror, comprising:
and the source electrode of the second switch tube is grounded, so that the power supply input end is grounded through the reference current source, the fourth switch tube and the second switch tube in sequence.
6. The circuit of claim 4, wherein the drain of the sampling switch tube is grounded through the passive end of the cascode current mirror, and the sampling switch tube comprises:
the drain electrode of the sampling switch tube is connected to the drain electrode of the third switch tube, and the source electrode of the first switch tube is grounded, so that the drain electrode of the sampling switch tube is grounded through the third switch tube and the first switch tube in sequence.
7. The circuit of any one of claims 1 to 6, wherein the channel width ratio of the power switch tube to the sampling switch tube is k, and k is greater than 1.
8. The circuit of claim 7, wherein the power switch tube and the sampling switch tube are PMOS tubes.
9. The circuit according to any one of claims 1 to 6, wherein the circuit further comprises a first current source and a fifth switching tube;
the power supply input end is connected to the drain electrode of the fourth switching tube sequentially through the first current source and the fifth switching tube;
and the grid electrode of the fifth switching tube is connected with the output end of the target comparator.
10. The circuit of claim 9, wherein the power input terminal is connected to the drain of the fourth switching tube sequentially through the first current source and the fifth switching tube, and the circuit comprises:
the power input end is connected to a source electrode of the fifth switching tube through a first current source, and a drain electrode of the fifth switching tube is connected with a drain electrode of the fourth switching tube, so that the power input end is connected to the drain electrode of the fourth switching tube through the first current source and the fifth switching tube in sequence;
and the fifth switch tube is a PMOS tube.
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CN114705904B CN114705904B (en) 2023-05-16

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CN115528787A (en) * 2022-11-29 2022-12-27 苏州贝克微电子股份有限公司 Control loop accelerating circuit
CN116047147A (en) * 2023-01-28 2023-05-02 苏州贝克微电子股份有限公司 High-precision current detecting circuit
CN116207949A (en) * 2023-04-25 2023-06-02 拓尔微电子股份有限公司 Current sampling circuit and DC-DC converter
CN117783643A (en) * 2024-02-27 2024-03-29 无锡力芯微电子股份有限公司 Load current detection system

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Publication number Priority date Publication date Assignee Title
CN115528787A (en) * 2022-11-29 2022-12-27 苏州贝克微电子股份有限公司 Control loop accelerating circuit
CN116047147A (en) * 2023-01-28 2023-05-02 苏州贝克微电子股份有限公司 High-precision current detecting circuit
CN116207949A (en) * 2023-04-25 2023-06-02 拓尔微电子股份有限公司 Current sampling circuit and DC-DC converter
CN116207949B (en) * 2023-04-25 2023-07-11 拓尔微电子股份有限公司 Current sampling circuit and DC-DC converter
CN117783643A (en) * 2024-02-27 2024-03-29 无锡力芯微电子股份有限公司 Load current detection system

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