CN116047147B - High-precision current detecting circuit - Google Patents
High-precision current detecting circuit Download PDFInfo
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- CN116047147B CN116047147B CN202310042265.7A CN202310042265A CN116047147B CN 116047147 B CN116047147 B CN 116047147B CN 202310042265 A CN202310042265 A CN 202310042265A CN 116047147 B CN116047147 B CN 116047147B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
Abstract
The application includes a high accuracy current detection circuit, concretely relates to current detection technical field. In the circuit, a power supply voltage is connected to a current output end through a power switch tube to output a target current; the power supply voltage is also connected to the first node through a sampling switch tube; the power supply voltage is also connected to the second node through a first controllable current source; the power switch tube is connected with the control end of the sampling switch tube; the first node is grounded through a first branch of the first current mirror and a third switching tube in sequence; the second node is grounded through a second branch of the first current mirror and a fourth switching tube in sequence; the control end of the third switching tube and the control end of the fourth switching tube are respectively connected with target voltages; the second node is connected to the output end of the high-precision current detection circuit through an inverter. The circuit sets the drain voltages of the first switching tube and the second switching tube in a basically equal state, so that the error between the sampling current and the second current is greatly reduced, and the accuracy of the current detection circuit is improved.
Description
Technical Field
The invention relates to the technical field of current detection, in particular to a high-precision current detection circuit.
Background
Fig. 1 shows a current detection circuit in the prior art, as shown in fig. 1, in which Mp is a power switch tube, a current io to be detected flows through the power switch tube Mp, ms is a sampling switch tube, k is the width-to-length ratio of the power switch tube Mp and the sampling switch tube Ms, and k >1, is and vs are a sampling current and a sampling voltage respectively, and when io < k×iref, the output vc of the current detection circuit is at a low level, which indicates that the current io to be detected does not flow excessively; when io > k×iref, the output vc of the current detection circuit is at high level, which indicates that the current io to be detected flows excessively.
However, the current detection circuit shown in fig. 1 has at least two technical problems: (1) Since the drain voltages of the first switching tube M1 and the second switching tube M2 are different, when the sampling current is mirrored as the second current i2, an error between the sampling current is and the second current i2 is larger; (2) Since the drain voltages of the power switch Mp and the sampling switch Ms are different and are vo and vs, respectively, the mirror current ratio of the power switch Mp and the sampling switch Ms is not completely equal to 1:k, so that the sampling current is not completely equal to io/k.
Disclosure of Invention
The embodiment of the application provides a high-precision current detection circuit, which improves the precision of the current detection circuit, wherein the circuit comprises a power switch tube, a sampling switch tube, a third switch tube, a fourth switch tube, an inverter, a first controllable current source and a first current mirror;
the power supply voltage is connected to the current output end through the power switch tube so as to output target current; the power supply voltage is also connected to a first node through the sampling switch tube; the power supply voltage is also connected to a second node through the first controllable current source; the power switch tube is connected with the control end of the sampling switch tube;
the first node is grounded through the third switching tube and a first branch of the first current mirror in sequence; the second node is grounded through the fourth switching tube and a second branch of the first current mirror in sequence; the control end of the third switching tube and the control end of the fourth switching tube are respectively connected with target voltages;
the second node is connected to the output end of the high-precision current detection circuit through the inverter.
In one possible implementation, a first branch of the first current mirror includes a first switching tube, and a second branch of the first current mirror includes a second switching tube;
the first node is grounded through the third switch tube and the first switch tube in sequence; the second node sequentially passes through the fourth switch tube and the second switch tube to be grounded.
In one possible implementation manner, the first switching tube, the second switching tube, the third switching tube and the fourth switching tube are NPN triodes; the power switch tube and the sampling switch tube are PNP triodes;
or the first switching tube, the second switching tube, the third switching tube and the fourth switching tube are NMOS tubes; the power switch tube and the sampling switch tube are PMOS tubes.
In one possible implementation, the width-to-length ratio of the power switch tube to the sampling switch tube is k, and k is more than 1;
the parameters of the first switching tube and the second switching tube are the same; the parameters of the third switching tube and the fourth switching tube are the same.
In one possible implementation, the circuit further includes a target voltage source; the positive electrode of the target voltage source is respectively connected to the control end of the third switching tube and the control end of the fourth switching tube; and the negative electrode of the target voltage source is grounded.
In a possible implementation manner, the circuit further comprises a first follower;
the input end of the first follower is connected to the current output end; an output of the first follower is connected to the first node.
In one possible implementation, the first follower includes a first operational amplifier;
the non-inverting input end of the first operational amplifier is connected to the current output end; the inverting input end of the first operational amplifier is connected to the output end of the first operational amplifier; an output of the first operational amplifier is connected to the first node.
In one possible implementation, the circuit further includes a first resistor, a second follower, a third follower, a second resistor, a seventh switching tube, an eighth switching tube, and a second current mirror;
the output end of the first operational amplifier is connected to the first node through the first resistor;
an inverting input of the first operational amplifier is connected to the first node;
the output end of the first operational amplifier is connected to the input end of the second follower; the output end of the second follower is grounded through a second resistor, a seventh switching tube and a first branch of the second current mirror in sequence;
the first node is connected to the input of the third follower; the output end of the third follower is grounded through the eighth switching tube and the second branch of the second current mirror in sequence;
the first node is also grounded through a third leg of the second current mirror.
In a possible implementation manner, the seventh switching tube is connected with the control end of the eighth switching tube; the output end of the second follower is connected to the control end of the seventh switching tube through the second resistor and the seventh switching tube in sequence.
In one possible implementation manner, the first branch of the second current mirror includes a fifth switching tube, the second branch of the second current mirror includes a sixth switching tube, and the third branch of the second current mirror includes a ninth switching tube;
the output end of the second follower sequentially passes through the second resistor, the seventh switching tube and the fifth switching tube to be grounded;
the output end of the third follower sequentially passes through the eighth switching tube and the sixth switching tube to be grounded;
the first node is grounded through the ninth switch tube.
In one possible implementation manner, the fifth switching tube, the sixth switching tube and the ninth switching tube are NPN triodes with the same parameters;
or the fifth switching tube, the sixth switching tube and the ninth switching tube are NMOS tubes with the same parameters.
In one possible implementation manner, the seventh switching tube and the eighth switching tube are PNP transistors with the same parameters;
or the seventh switching tube and the eighth switching tube are PMOS tubes with the same parameters.
In one possible implementation, the first resistor and the second resistor have the same resistance value.
The technical scheme that this application provided can include following beneficial effect:
in the circuit related to the application, a power supply voltage is connected to a current output end through a power switch tube to output a target current; the power supply voltage is also connected to the first node through a sampling switch tube; the power supply voltage is also connected to the second node through a first controllable current source; the power switch tube is connected with the control end of the sampling switch tube; the first node is grounded through a first branch of the first current mirror and a third switching tube in sequence; the second node is grounded through a second branch of the first current mirror and a fourth switching tube in sequence; the control end of the third switching tube and the control end of the fourth switching tube are respectively connected with target voltages; the second node is connected to the output end of the high-precision current detection circuit through an inverter. In the circuit, the drain voltages of the first switching tube and the second switching tube are set to be in the basically equal state by adding the third switching tube and the fourth switching tube, so that the error between the sampling current and the second current is greatly reduced, and the accuracy of the current detection circuit is improved;
in the circuit, the proportion of mirror currents of the power switch tube and the sampling switch tube can be ensured to be equal to 1:k completely by arranging the first follower; at this time, the drainage circuit formed by the second follower, the third follower, the second resistor, the seventh switching tube, the eighth switching tube and the second current mirror is arranged, so that the error between the sampling current and the second current is greatly reduced on the basis that the mirror current proportion of the power switching tube and the sampling switching tube is completely equal to 1:k, and the accuracy of the current detection circuit is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 shows a current sensing circuit of the prior art.
Fig. 2 is a schematic diagram illustrating a high-precision current detection circuit according to an exemplary embodiment of the present application.
Fig. 3 is a schematic diagram of a high-precision current detection circuit according to an exemplary embodiment of the present application.
Fig. 4 shows a schematic structural diagram of a current-guiding circuit according to an embodiment of the present application.
Fig. 5 shows a high-precision current detection circuit according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Fig. 2 is a schematic diagram illustrating a high-precision current detection circuit according to an exemplary embodiment of the present application.
The circuit comprises a power switch tube Mp, a sampling switch tube Ms, a third switch tube M3, a fourth switch tube M4, an inverter inv1, a first controllable current source iref and a first current mirror;
the power supply voltage is connected to the current output end through the power switch tube Mp to output a target current io; the power supply voltage is also connected to a first node through the sampling switch tube Ms; the supply voltage is also connected to a second node through the first controllable current source iref; the power switch tube Mp is connected with the control end of the sampling switch tube Ms;
the first node is grounded through the third switching tube M3 and the first branch of the first current mirror in turn; the second node is grounded through the fourth switching tube M4 and a second branch of the first current mirror in sequence; the control end of the third switching tube M3 and the control end of the fourth switching tube M4 are respectively connected with target voltages;
the second node is connected to the output end of the high-precision current detection circuit through the inverter inv 1.
In one possible implementation, a first branch of the first current mirror includes a first switching tube M1, and a second branch of the first current mirror includes a second switching tube M2;
the first node is grounded through the third switching tube M3 and the first switching tube M1 in turn; the second node is grounded through the fourth switching tube M4 and the second switching tube M2 in turn.
In one possible implementation manner, the first switching tube M1, the second switching tube M2, the third switching tube M3, and the fourth switching tube M4 are NPN transistors; the power switch tube Mp and the sampling switch tube Ms are PNP triodes;
or the first switching tube M1, the second switching tube M2, the third switching tube M3 and the fourth switching tube M4 are NMOS tubes; the power switch tube Mp and the sampling switch tube Ms are PMOS tubes.
In one possible implementation, the width-to-length ratio of the power switch tube Mp to the sampling switch tube Ms is k, k > 1;
the parameters of the first switching tube M1 and the second switching tube M2 are the same; the third switching tube M3 and the fourth switching tube M4 have the same parameters.
In a possible implementation, the circuit further includes a target voltage source vm; the positive electrode of the target voltage source vm is connected to the control end of the third switching tube M3 and the control end of the fourth switching tube M4 respectively, so as to provide a target voltage for the control end of the third switching tube M3 and the control end of the fourth switching tube M4; the negative pole of the target voltage source vm is grounded.
That is, the circuit structure shown in fig. 2 is that, based on the circuit structure shown in fig. 1, a third switching tube M3, a fourth switching tube M4 and a target voltage source vm are added, where the first switching tube M1 and the second switching tube M2 are switching tubes with identical parameters, the third switching tube M3 and the fourth switching tube M4 are switching tubes with identical parameters, and the working principle of the circuit structure shown in fig. 2 is as follows, where each switching tube in the high-precision current detection circuit shown in fig. 2 is a MOS tube:
as known from the background art, after the circuit works normally, the voltage vs of the first node and the voltage vx of the second node have errors, so that the currents flowing through the third switching tube M3 and the fourth switching tube M4 are different at this time; meanwhile, due to the characteristics of the switching tube, when the current flowing through the switching tube is different, the gate-source voltage of the switching tube only fluctuates in a small range (0.5V-0.7V), so the gate-source voltage vgs of the third switching tube M3 M3 With the gate-source voltage vgs of the fourth switching tube M4 M4 Substantially the same; in addition, the drain voltage of the first switching tube M1 is vm-vgs due to the presence of the third switching tube M3 and the fourth switching tube M4 M3 The drain voltage of the second switch tube M2 is vm-vgs M4 Therefore, the drain voltage of the first switching tube M1 is substantially equal to that of the second switching tube M2, and thus compared with the prior art, the sampling voltage is greatly reducedThe error between the current is and the second current i2 improves the accuracy of the current detection circuit.
In summary, in the circuit related to the present application, the power supply voltage is connected to the current output end through the power switch tube to output the target current; the power supply voltage is also connected to the first node through a sampling switch tube; the power supply voltage is also connected to the second node through a first controllable current source; the power switch tube is connected with the control end of the sampling switch tube; the first node is grounded through a first branch of the first current mirror and a third switching tube in sequence; the second node is grounded through a second branch of the first current mirror and a fourth switching tube in sequence; the control end of the third switching tube and the control end of the fourth switching tube are respectively connected with target voltages; the second node is connected to the output end of the high-precision current detection circuit through an inverter. In the circuit, the drain voltages of the first switching tube and the second switching tube are set to be in the basically equal state by adding the third switching tube and the fourth switching tube, so that the error between the sampling current and the second current is greatly reduced, and the accuracy of the current detection circuit is improved.
Fig. 3 is a schematic diagram of a high-precision current detection circuit according to an exemplary embodiment of the present application. The voltage of the first node in the circuit configuration shown in FIG. 1 is clamped to vgs M1 In the improved circuit structure shown in fig. 2, since the third switching tube M3 is disposed between the voltage vs of the first node and the first switching tube M1, the voltage vs of the first node is not clamped, and at this time, the voltage vs of the first node can be adjusted to be equal to the voltage vo at the current output end by setting the adjusting circuit, so as to solve the detection error caused by the difference of the drain voltages of the power switching tube Mp and the sampling switching tube Ms, and therefore, as shown in fig. 3, the circuit further comprises a first follower on the basis of the high-precision current detecting circuit shown in fig. 2;
the input end of the first follower is connected to the current output end; the output of the first follower is connected to the first node.
The circuit structure shown in fig. 3 is that, on the basis of the circuit structure shown in fig. 2, a first operational amplifier A1 is added, and an inverting input terminal of the first operational amplifier A1 is connected with an output terminal thereof to form a first follower, so that the voltage vs of the first node is finally adjusted to be equal to the voltage vo;
at this time, as can be seen from fig. 3, although the voltage vo at the current output terminal and the voltage vs of the first node are very close, the first follower will output the current ia, so that the error between the second current i2 and the sampling current is increased, that is, the second current i2 at this time is equal to the sum of the sampling current is and the current ia, and therefore, a current-guiding circuit needs to be added to guide the current ia from the output terminal of the first follower to GND.
In one possible implementation, the first follower comprises a first operational amplifier;
the non-inverting input end of the first operational amplifier is connected to the current output end; the inverting input end of the first operational amplifier is connected to the output end of the first operational amplifier; the output end of the first operational amplifier is connected to the first node.
Referring to fig. 4, a schematic structural diagram of a current-guiding circuit according to an embodiment of the present application is shown. As shown in fig. 4, the circuit further includes a first resistor ra, a second follower, a third follower, a second resistor rb, a seventh switching tube M7, an eighth switching tube M8, and a second current mirror;
the output end of the first operational amplifier A1 is connected to the first node through the first resistor ra;
the inverting input end of the first operational amplifier A1 is connected to the first node;
the output end of the first operational amplifier A1 is connected to the input end of the second follower; the output end of the second follower is grounded through a second resistor rb, a seventh switching tube M7 and a first branch of the second current mirror in sequence;
the first node is connected to the input end of the third follower; the output end of the third follower is grounded through the eighth switching tube M8 and the second branch of the second current mirror in sequence;
the first node is also coupled to ground through a third leg of the second current mirror.
In one possible implementation, the seventh switching tube M7 is connected to the control terminal of the eighth switching tube M8; the output end of the second follower is connected to the control end of the seventh switching tube M7 through the second resistor rb and the seventh switching tube M7 in sequence.
In one possible implementation, the first branch of the second current mirror includes a fifth switching tube M5, the second branch of the second current mirror includes a sixth switching tube M6, and the third branch of the second current mirror includes a ninth switching tube M9;
the output end of the second follower is grounded through the second resistor rb, the seventh switching tube M7 and the fifth switching tube M5 in sequence;
the output end of the third follower is grounded through the eighth switching tube M8 and the sixth switching tube M6 in sequence;
the first node is grounded through the ninth switching transistor M9.
In one possible implementation manner, the fifth switching tube M5, the sixth switching tube M6 and the ninth switching tube M9 are NPN triodes with the same parameters;
alternatively, the fifth switching tube M5, the sixth switching tube M6 and the ninth switching tube M9 are NMOS tubes with the same parameters.
In one possible implementation manner, the seventh switching tube M7 and the eighth switching tube M8 are PNP transistors with the same parameters;
or, the seventh switching tube M7 and the eighth switching tube M8 are PMOS tubes with the same parameters.
In one possible implementation, the first resistor ra and the second resistor rb have the same resistance.
The operating principle of the drainage circuit in fig. 4 is as follows:
a first resistor ra is arranged between the output end of the first operational amplifier A1 and the third switching tube M3, and at the moment, the current ia flows through the first resistor ra; at the same time, the second and third followers copy the voltage va and the voltage vs as voltages respectively
And voltage->
I.e. at this point->
=va，/>
=vs; meanwhile, the fifth switching tube M5, the sixth switching tube M6 and the ninth switching tube M9 are switching tubes with the same parameters, and the three switching tubes form a current mirror, so that the current i5 flowing through the fifth switching tube M5 is equal to the current i6 flowing through the sixth switching tube M6, and the current i9 flowing through the ninth switching tube M9 is equal to the current i6 flowing through the seventh switching tube M6, at this time, since the seventh switching tube M7 is connected in series with the fifth switching tube M5, the eighth switching tube M8 is connected in series with the sixth switching tube M6, the current flowing through the seventh switching tube M7 is equal to the current flowing through the eighth switching tube M8, and since the seventh switching tube M7 and the eighth switching tube M8 are switching tubes with the same parameters, the gate source voltage of the seventh switching tube M7 is equal to the gate source voltage of the eighth switching tube M8, and since the gates of the seventh switching tube M7 and the eighth switching tube M8 are connected, the voltage of the seventh switching tube M7 and the eighth switching tube M8 is equal, i.e. the source voltage of the seventh switching tube M7 is equal to the gate voltage of the seventh switching tube M8 is =>
=vs, at which point: />
Therefore, when the resistance values of the first resistor ra and the second resistor rb are designed to be equal, +.>
；
As can be seen from the above analysis, by providing a current-draining circuit, the current ia is drained from the first node to GND through the ninth switching tube M9.
At this time, the high-precision current detection circuit shown in fig. 5 is obtained by combining fig. 3 and fig. 4. In the high-precision current detection circuit shown in fig. 5, vo=vs, thereby ensuring is=io/k; meanwhile, since the drain voltages of the first switching tube M1 and the second switching tube M2 are the same, and the current ia is conducted from the first node to GND through the ninth switching tube M9, it is ensured that the sampling current is can be perfectly mirrored as the second current i2.
In summary, in the circuit related to the present application, the power supply voltage is connected to the current output end through the power switch tube to output the target current; the power supply voltage is also connected to the first node through a sampling switch tube; the power supply voltage is also connected to the second node through a first controllable current source; the power switch tube is connected with the control end of the sampling switch tube; the first node is grounded through a first branch of the first current mirror and a third switching tube in sequence; the second node is grounded through a second branch of the first current mirror and a fourth switching tube in sequence; the control end of the third switching tube and the control end of the fourth switching tube are respectively connected with target voltages; the second node is connected to the output end of the high-precision current detection circuit through an inverter. In the circuit, the drain voltages of the first switching tube and the second switching tube are set to be in a basically equal state by adding the third switching tube and the fourth switching tube, so that the error between the sampling current is and the second current i2 is greatly reduced, and the accuracy of the current detection circuit is improved;
in the circuit, the proportion of mirror currents of the power switch tube and the sampling switch tube can be ensured to be equal to 1:k completely by arranging the first follower; at this time, the drainage circuit formed by the second follower, the third follower, the second resistor, the seventh switching tube, the eighth switching tube and the second current mirror is arranged, so that the error between the sampling current and the second current is greatly reduced on the basis that the mirror current proportion of the power switching tube and the sampling switching tube is completely equal to 1:k, and the accuracy of the current detection circuit is improved.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (12)
1. The high-precision current detection circuit is characterized by comprising a power switch tube, a sampling switch tube, a third switch tube, a fourth switch tube, an inverter, a first controllable current source and a first current mirror;
the power supply voltage is connected to the current output end through the power switch tube so as to output target current; the power supply voltage is also connected to a first node through the sampling switch tube; the power supply voltage is also connected to a second node through the first controllable current source; the power switch tube is connected with the control end of the sampling switch tube;
the first node is grounded through the third switching tube and a first branch of the first current mirror in sequence; the second node is grounded through the fourth switching tube and a second branch of the first current mirror in sequence; the control end of the third switching tube and the control end of the fourth switching tube are respectively connected with target voltages;
the second node is connected to the output end of the high-precision current detection circuit through the phase inverter; a first branch of the first current mirror comprises a first switching tube, and a second branch of the first current mirror comprises a second switching tube;
the first node is grounded through the third switch tube and the first switch tube in sequence; the second node sequentially passes through the fourth switch tube and the second switch tube to be grounded.
2. The circuit of claim 1, wherein the first, second, third, and fourth switching transistors are NPN transistors; the power switch tube and the sampling switch tube are PNP triodes;
or the first switching tube, the second switching tube, the third switching tube and the fourth switching tube are NMOS tubes; the power switch tube and the sampling switch tube are PMOS tubes.
3. The circuit of claim 2, wherein the aspect ratio of the power switching tube to the sampling switching tube is k, k > 1;
the parameters of the first switching tube and the second switching tube are the same; the parameters of the third switching tube and the fourth switching tube are the same.
4. The circuit of claim 1, further comprising a target voltage source therein; the positive electrode of the target voltage source is respectively connected to the control end of the third switching tube and the control end of the fourth switching tube; and the negative electrode of the target voltage source is grounded.
5. The circuit of any one of claims 1 to 4, further comprising a first follower;
the input end of the first follower is connected to the current output end; an output of the first follower is connected to the first node.
6. The circuit of claim 5, wherein the first follower comprises a first operational amplifier;
the non-inverting input end of the first operational amplifier is connected to the current output end; the inverting input end of the first operational amplifier is connected to the output end of the first operational amplifier; an output of the first operational amplifier is connected to the first node.
7. The circuit of claim 6, further comprising a first resistor, a second follower, a third follower, a second resistor, a seventh switching tube, an eighth switching tube, and a second current mirror;
the output end of the first operational amplifier is connected to the first node through the first resistor;
an inverting input of the first operational amplifier is connected to the first node;
the output end of the first operational amplifier is connected to the input end of the second follower; the output end of the second follower is grounded through a second resistor, a seventh switching tube and a first branch of the second current mirror in sequence;
the first node is connected to the input of the third follower; the output end of the third follower is grounded through the eighth switching tube and the second branch of the second current mirror in sequence;
the first node is also grounded through a third leg of the second current mirror.
8. The circuit of claim 7, wherein the seventh switching tube is connected to the control terminal of the eighth switching tube; the output end of the second follower is connected to the control end of the seventh switching tube through the second resistor and the seventh switching tube in sequence.
9. The circuit of claim 7, wherein a first leg of the second current mirror comprises a fifth switching tube, a second leg of the second current mirror comprises a sixth switching tube, and a third leg of the second current mirror comprises a ninth switching tube;
the output end of the second follower sequentially passes through the second resistor, the seventh switching tube and the fifth switching tube to be grounded;
the output end of the third follower sequentially passes through the eighth switching tube and the sixth switching tube to be grounded;
the first node is grounded through the ninth switch tube.
10. The circuit of claim 9, wherein the fifth switching tube, the sixth switching tube and the ninth switching tube are NPN triodes with the same parameters;
or the fifth switching tube, the sixth switching tube and the ninth switching tube are NMOS tubes with the same parameters.
11. The circuit of claim 7, wherein the seventh switching transistor and the eighth switching transistor are PNP transistors having the same parameters;
or the seventh switching tube and the eighth switching tube are PMOS tubes with the same parameters.
12. The circuit of claim 7, wherein the first resistor has the same resistance as the second resistor.
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| CN116318049B (en) * | 2023-05-17 | 2023-08-11 | 苏州贝克微电子股份有限公司 | High-precision resistor circuit |
| CN116338297B (en) * | 2023-05-29 | 2023-08-08 | 苏州贝克微电子股份有限公司 | High-precision current detection circuit capable of reducing chip layout area |
| CN116400130B (en) * | 2023-06-06 | 2023-08-11 | 苏州贝克微电子股份有限公司 | Voltage sampling circuit for outputting current signal |
| CN116505948B (en) * | 2023-06-27 | 2023-08-25 | 苏州贝克微电子股份有限公司 | Voltage difference sampling circuit |
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|---|---|---|---|---|
| US7365559B2 (en) * | 2005-05-03 | 2008-04-29 | Potentia Semiconductor Inc. | Current sensing for power MOSFETs |
| CN102208802B (en) * | 2010-06-29 | 2013-11-13 | 上海山景集成电路股份有限公司 | Power switching tube overcurrent detection and overcurrent protection circuit |
| CN103546021B (en) * | 2013-10-31 | 2016-04-13 | 矽力杰半导体技术(杭州)有限公司 | Current feedback method and current feedback circuit and drive circuit and Switching Power Supply |
| CN107290581B (en) * | 2017-06-30 | 2023-07-25 | 杰华特微电子（张家港）有限公司 | Current detection circuit of switch circuit and switch circuit |
| CN114047798B (en) * | 2022-01-12 | 2022-04-29 | 苏州贝克微电子股份有限公司 | High-precision current detection device inside integrated circuit chip |
| CN115248341A (en) * | 2022-04-08 | 2022-10-28 | 杰华特微电子股份有限公司 | Current detection circuit of switching device and switching power supply using same |
| CN114705904B (en) * | 2022-04-12 | 2023-05-16 | 苏州贝克微电子股份有限公司 | High-precision overcurrent detection circuit |
| CN114545063B (en) * | 2022-04-22 | 2022-07-12 | 苏州贝克微电子股份有限公司 | High-precision interval current detection circuit |
-
2023
- 2023-01-28 CN CN202310042265.7A patent/CN116047147B/en active Active
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| CN116047147A (en) | 2023-05-02 |
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