CN115184663B - Bidirectional high-precision NMOS power tube current sampling circuit and method - Google Patents

Bidirectional high-precision NMOS power tube current sampling circuit and method Download PDF

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CN115184663B
CN115184663B CN202210986642.8A CN202210986642A CN115184663B CN 115184663 B CN115184663 B CN 115184663B CN 202210986642 A CN202210986642 A CN 202210986642A CN 115184663 B CN115184663 B CN 115184663B
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tube
nmos
voltage
terminal
sampling
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CN115184663A (en
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李响
蔡胜凯
董渊
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Shanghai Ziying Microelectronics Co ltd
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Shanghai Ziying Microelectronics Co ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention relates to a bidirectional high-precision NMOS power tube current sampling circuit and a bidirectional high-precision NMOS power tube current sampling method. It comprises the following steps: sampling connection part comprising NMOS power tube M P For duplicating NMOS power tube M P Status sampling tube M SNS Error amplificationA section for sampling tube M SNS The voltage at the source terminal is loop controlled so that the sampling tube M SNS Voltage V of source terminal SNS And NMOS power tube M P Voltage V of source terminal 2 Keeping consistency; a current output part which is connected with the error amplifying part in an adapting way, and the error amplifying part is based on the voltage V 1 And voltage V 2 Status providing sampling tube M SNS The current output section provides a sampling tube M based on the error amplifying section SNS The desired sampling current is output in the direction current state of (a). The invention can realize the sampling of current in positive and negative directions without introducing extra off-chip resistor, and has wide application range, safety and reliability.

Description

Bidirectional high-precision NMOS power tube current sampling circuit and method
Technical Field
The invention relates to a current sampling circuit and a method, in particular to a bidirectional high-precision NMOS power tube current sampling circuit and a method.
Background
With the development of sensing technology, more and more sensor systems use microelectronic chips as a way of sensing physical quantities; when the sensor systems work, the physical quantity is firstly converted into a voltage signal or a current signal, then the microelectronic chip is used for sampling the electric signal, and finally the electric signal is output to the terminal.
Among the electrical signals obtained by the conversion, the voltage signal can be directly collected by the ADC, and the current signal is needed to be sampled by the current first, so that the current outside the chip is converted into a signal which can be directly perceived by the chip. In practice, there are various methods for implementing current sampling, and resistors can be directly connected in series on an off-chip signal path, but the method has power consumption loss, and is not suitable for a power supply system. In order to reduce power loss, in some systems, parasitic resistance of the inductor, i.e., RDC sampling, is utilized, but such current sampling is only suitable for systems with inductive participation.
In FIG. 1, a current sampling implementation without off-chip resistors is shown, in FIG. 1M P Is NMOS power tube, M SNS For sampling tubes, I SNS For sampling current, NMOS power tube M P Gate terminal of (c) and sampling tube M SNS The gate terminals of (2) are connected to the voltage V G_HS NMOS power tube M P Is connected with the sampling tube M SNS The drain terminals of (a) are connected with the voltage V 1 NMOS powerTube M P Source terminal voltage V of (2) 2 。
The current sampling shown in fig. 1 is performed by replicating an NMOS power transistor M P Through the sampling tube M SNS The current can be converted into the inside of the chip in an equal proportion, and the current path does not need an extra resistor. However, the main disadvantage of the current sampling is that it can only work for one direction of current, and if the direction of current changes, the current sampling circuit cannot work normally.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a bidirectional high-precision NMOS power tube current sampling circuit and method, which can realize current sampling in positive and negative directions without introducing extra off-chip resistors, and have wide application range, safety and reliability.
According to the technical scheme provided by the invention, the bidirectional high-precision NMOS power tube current sampling circuit comprises:
sampling connection part comprising NMOS power tube M P For duplicating NMOS power tube M P Status sampling tube M SNS Sampling tube M SNS Drain terminal of (2), NMOS power tube M P The drain terminals of (a) are connected with the voltage V 1 NMOS power tube M P Source terminal voltage V of (2) 2 ；
Error amplifying part and NMOS power tube M in sampling connecting part P Is provided, and a sampling tube M SNS For adapting the source terminal of the sampling tube M SNS The voltage at the source terminal is loop controlled so that the sampling tube M SNS Voltage V of source terminal SNS And NMOS power tube M P Voltage V of source terminal 2 Keeping consistency;
a current output part which is connected with the error amplifying part in an adapting way, and the error amplifying part is based on the voltage V 1 And voltage V 2 Status providing sampling tube M SNS The current output section provides a sampling tube M based on the error amplifying section SNS Outputting a required sampling current in a direction current state; wherein the error amplifying part provides a sampling tube M SNS Is the directional current of (a)And flow through NMOS tube M P The current direction of (a) is uniform.
The error amplifying section includes a DC bias power supply, a first loop control current supply circuit, and a second loop control current supply circuit,
the first loop control current supply circuit and the second loop control current supply circuit are adaptively and electrically connected with the direct current bias power supply;
voltage V 1 Greater than voltage V 2 When the first loop control current supply circuit controls the sampling tube M SNS Voltage V of source terminal SNS And NMOS power tube M P Voltage V of source terminal 2 Maintain uniformity and provide a slave voltage V 1 Flow direction sampling tube M SNS A directional current at the source terminal;
voltage V 1 Less than voltage V 2 When the second loop control current supply circuit controls the sampling tube M SNS Voltage V of source terminal SNS And NMOS power tube M P Voltage V of source terminal 2 Maintain uniformity and provide a sample tube M SNS Source terminal current-to-voltage V 1 Is a directional current of (a).
The direct-current bias power supply comprises a PMOS tube M P3 PMOS tube M P4 PMOS tube M P5 PMOS tube M P6 PMOS tube M P7 PMOS tube M P8 Wherein, the method comprises the steps of, wherein,
PMOS tube M P3 Source terminal of (P-channel metal oxide semiconductor) PMOS tube M P4 Source terminal of (P-channel metal oxide semiconductor) PMOS tube M P6 PMOS tube M P7 The source terminal of (C) is connected with the floating voltage V FLY_VDD Connected with PMOS tube M P3 Gate terminal of (C), PMOS tube M P3 Drain terminal of PMOS tube M P6 Gate terminal of (d) and PMOS transistor M P7 Through the grid terminal of the current source I 2 And NMOS tube M N6 Drain terminal of (2), NMOS tube M N6 Gate terminal of (d) and NMOS transistor M N7 Is connected with the grid end of the transistor;
PMOS tube M P4 Gate terminal of (c) and PMOS tube M P4 Drain terminal of PMOS tube M P5 Is connected with the source terminal of the PMOS tube M P5 Gate terminal of (c) and PMOS tube M P5 Drain terminal of (2), NMOS tube M N7 Drain terminal of (d) and PMOS tube M P8 Is connected with the grid end of the transistor;
PMOS tube M P6 Drain terminal of (2) and NMOS transistor M N9 Drain terminal of (2), NMOS tube M N9 Gate terminal of (d) and NMOS transistor M N12 Is connected with the gate terminal of NMOS tube M N9 Source terminal of (2) and NMOS transistor N M8 Drain terminal of (d) and NMOS transistor M N8 Is connected with the grid end of the transistor;
PMOS tube M P7 Drain terminal of (2) and PMOS tube M P8 Source terminal of (2), NMOS transistor M N12 Is connected with the drain terminal of the first loop control current supply circuit in an adapting way, and is a PMOS tube M P8 Drain terminal of (2), NMOS tube M N12 Source terminal of (2) and NMOS transistor M N11 Is adapted to be connected to the drain terminal of the second loop control current supply circuit;
NMOS tube M N11 Gate terminal of (2) and NMOS transistor M N10 Gate terminal of (2), NMOS transistor M N10 Is connected to the drain terminal of (d) and to the current source I 3 Is connected with the output end of the current source I 3 Voltage terminal and floating voltage V of (2) FLY_VDD Connecting;
NMOS tube M N6 Source terminal of (2), NMOS transistor M N7 Source terminal of (2), NMOS transistor M N8 Source terminal of (d) and NMOS transistor M N11 The source terminal of (C) is connected to the voltage V 2 And (5) connection.
The first loop control current supply circuit comprises a PMOS tube M P12 High-voltage PMOS tube M HVP2 NMOS tube M N2 NMOS tube M N1 High-voltage NMOS tube M HVN1 Wherein, the method comprises the steps of, wherein,
PMOS tube M P12 Is connected with a floating voltage V FLY_VDD PMOS tube M P12 Drain terminal of (C) and high-voltage PMOS tube M HVP2 Is connected with the source terminal of the high-voltage PMOS tube M HVP2 Gate termination voltage V of (2) 2 High-voltage PMOS tube M HVP2 Drain terminal of (2) and NMOS transistor M N2 Drain terminal of (2), NMOS tube M N2 Gate terminal of (2), NMOS transistor M N1 Is adaptively connected with the gate terminal and the current output part;
NMOS tube M N1 Source terminal of (d) and NMOS transistor M N2 The source electrode of (a) is grounded, NMOS tube M N1 Drain terminal of (d) and high voltageNMOS tube M HVN1 Is connected with the source terminal of the high-voltage NMOS tube M HVN1 Is connected with the sampling tube M SNS Source terminal of (d) and NMOS transistor M N10 Is connected with the source terminal of the high-voltage NMOS tube M HVN1 Gate termination voltage V of (2) DD 。
The second loop control current supply circuit comprises a PMOS tube M P13 PMOS tube M P14 PMOS tube M P15 NMOS tube M N16 PMOS tube M P16 High-voltage PMOS tube M HVP1 Wherein, the method comprises the steps of, wherein,
PMOS tube M P13 Source terminal of (P-channel metal oxide semiconductor) PMOS tube M P14 Source terminal of (d) and PMOS tube M P15 The source terminal of (C) is connected with the floating voltage V FLY_VDD Connected with PMOS tube M P13 Gate terminal of (c) and PMOS tube M P13 Drain terminal of (2), NMOS tube M N16 Drain terminal of PMOS tube M P14 Gate terminal of (d) and PMOS transistor M P15 Is connected with the grid end of the transistor;
PMOS tube M P14 Drain terminal of (2) and PMOS tube M P16 Is connected with the source terminal of the PMOS tube M P15 Drain terminal of (C) and high-voltage PMOS tube M HVP1 Is connected with the source terminal of NMOS tube M N16 Gate terminal of (2) and NMOS transistor M N12 Source terminal of (2), NMOS transistor M N11 Drain terminal of (d) and PMOS tube M P8 Is connected with the drain end of the transistor;
NMOS tube M N16 Source terminal of (P-channel metal oxide semiconductor) PMOS tube M P16 Gate termination voltage V of (2) 2 PMOS tube M P16 Is connected with the sampling tube M SNS Source terminal of (2), NMOS transistor M N10 Is connected with the source terminal of the high-voltage PMOS tube M HVP1 Is connected to the current output section.
The circuit output part comprises a PMOS tube M P1 PMOS tube M P2 PMOS tube M P1d PMOS tube M P2d Wherein, the method comprises the steps of, wherein,
PMOS tube M P1 Source terminal of (P-channel metal oxide semiconductor) PMOS tube M P2 Source terminal of (P-channel metal oxide semiconductor) PMOS tube M P1d Source terminal of (d) and PMOS tube M P2d The source terminal of (C) is connected to the voltage V DD Connected with PMOS tube M P1 Gate terminal of (c) and PMOS tube M P1 Drain terminal of (2), NMOS tube M N3 Drain terminal of PMOS tube M P2 Is connected with the grid end of the PMOS tube M P2 Drain terminal of (2) and NMOS transistor M N4 Is connected with the drain terminal of the PMOS tube M P2 Drain terminal of (2) and NMOS transistor M N4 Is connected with each other to form a sampling current I SNS1 A current first sampling output terminal of (a);
NMOS tube M N4 Gate terminal of (2) and NMOS transistor M N5 Gate terminal of (2), NMOS transistor M N5 Is connected with the drain terminal of the high-voltage PMOS tube M HVP1 Drain terminal of (2), NMOS tube M N3d Connected with PMOS tube M P1d Gate terminal of (c) and PMOS tube M P1d Drain terminal of (2), NMOS tube M N3d Drain terminal of (d) and PMOS tube M P2d Is connected with the grid end of the PMOS tube M P2d Drain terminal of (2) and NMOS transistor M N4d Is connected with the drain terminal of the PMOS tube M P2d Drain terminal of (2) and NMOS transistor M N4d Is connected with each other to form a sampling current I SNSN2 A current second sampling output terminal of (a);
NMOS tube M N4d Gate terminal of (2) and NMOS transistor M N1 Gate terminal of (2), NMOS transistor M N3 Gate terminal of (2), NMOS transistor M N2 Gate terminal of (2), NMOS transistor M N2 Drain terminal of (d) and high-voltage PMOS tube M HVP2 Is connected with the drain end of the transistor;
NMOS tube M N3 Source terminal of (2), NMOS transistor M N4 Source terminal of (2), NMOS transistor M N5 Source terminal of (2), NMOS transistor M N3d Source terminal of (d) and NMOS transistor M N4d The source terminals of (a) are grounded.
Also comprises an NMOS tube M N17 NMOS tube M N17 Source terminal voltage V of (2) 2 NMOS tube M N17 Is connected with the sampling tube M at the drain end SNS Source terminal of (d) and NMOS transistor M N10 Is connected with the source terminal of the transistor;
NMOS tube M N17 The gate terminal of (a) is connected with the enable inversion signal ENN, and the NMOS tube M is enabled by the enable inversion signal ENN during current sampling N17 In the off state.
Sampling tube M SNS Through a current source I 1 And (5) grounding.
NMOS power tube M P And samplingTube M SNS The width-to-length ratio of the corresponding conduction channel is X:1, X > 1.
Bidirectional high-precision NMOS power tube current sampling method for any NMOS power tube M P The current sampling circuit performs the required current sampling.
The invention has the advantages that: for NMOS power tube M P By means of sampling tubes M SNS Duplicating NMOS power tube M P The state of the (2) is realized by utilizing the matching of the error amplifying part and the current output part, and no extra off-chip device is needed; floating voltage V in error amplifying section FLY_VDD The floating power supply in the high-end NMOS power tube can be reused, the cost is not increased, and the use is convenient. Loop control and providing sampling tube M by error amplifying part SNS The required current can realize the sampling of positive current and negative current, reduce the number of sampling tubes, optimize the chip area, reduce the cost of the internal sampling of the chip and improve the reliability of the internal sampling of the chip.
Drawings
Fig. 1 is a schematic diagram of current sampling of a conventional NMOS power transistor.
Fig. 2 is a schematic circuit diagram of the present invention.
FIG. 3 shows the floating voltage V of the present invention FLY_VDD Is a circuit schematic.
FIG. 4 shows the voltage V 1 Voltage V 2 A waveform diagram of bi-directional current sampling is performed.
Detailed Description
The invention will be further described with reference to the following specific drawings and examples.
As shown in fig. 2: in order to realize sampling of current in positive and negative directions under the condition of additionally introducing off-chip resistor, the bidirectional high-precision NMOS power tube current sampling circuit comprises:
sampling connection part comprising NMOS power tube M P For duplicating NMOS power tube M P Status sampling tube M SNS Sampling tube M SNS Drain terminal of (2), NMOS power tube M P The drain terminals of (a) are connected with the voltage V 1 NMOS powerTube M P Source terminal voltage V of (2) 2 ；
Error amplifying part and NMOS power tube M in sampling connecting part P Is provided, and a sampling tube M SNS For adapting the source terminal of the sampling tube M SNS The voltage at the source terminal is loop controlled so that the sampling tube M SNS Voltage V of source terminal SNS And NMOS power tube M P Voltage V of source terminal 2 Keeping consistency;
a current output part which is connected with the error amplifying part in an adapting way, and the error amplifying part is based on the voltage V 1 And voltage V 2 Status providing sampling tube M SNS The current output section provides a sampling tube M based on the error amplifying section SNS Outputting a required sampling current in a direction current state; wherein the error amplifying part provides a sampling tube M SNS Directional current and flow through NMOS tube M P The current direction of (a) is uniform.
Specifically, it flows through NMOS tube M P I.e. the current to be sampled. Sampling tube M SNS Is also NMOS tube, NMOS power tube M P And sampling tube M SNS The aspect ratio of the corresponding conductive channel is X:1, X is more than 1; the specific value of X can be selected according to the requirement, so that the current sampling requirement can be met. In the sampling connection part, NMOS power tube M P Gate terminal of (d) and sampling tube M SNS The gate terminal of (a) is connected with the voltage V G_HS Connection, voltage V G_HS Can be selected according to the requirement, and can meet the working requirement of current sampling.
Error amplifying part and NMOS power tube M P Is provided, and a sampling tube M SNS Is connected with the source terminal of NMOS power tube M P Source terminal voltage V of (2) 2 Sampling tube M SNS Is V SNS The method comprises the steps of carrying out a first treatment on the surface of the In specific implementation, the error amplifying part is used for providing negative feedback control, namely, the voltage V is used 2 And voltage V SNS The voltage difference between them is subjected to negative feedback control to make the sampling tube M after the negative feedback control SNS Voltage V of source terminal SNS And voltage V 2 Hold oneCausing; i.e. after loop control, the voltage V is made SNS And voltage V 2 Equal.
In particular, when the voltage V SNS And voltage V 2 After equality, according to NMOS power tube M in FIG. 2 P And sampling tube M SNS The connection relation between the sample tube M and the sample tube M can be known SNS Gate terminal, NMOS power tube M P The corresponding voltages at the gate terminals are all V G_HS Sampling tube M SNS Source terminal, NMOS power tube M P The corresponding voltages of the source terminals are all the voltage V 2 Sampling tube M SNS Drain terminal, NMOS power tube M P The corresponding voltages of the drain terminals are V 1 Therefore, it flows through the NMOS power tube M P Current through NMOS tube M SNS The ratio of the currents is X.
Sampling tube M is amplified by error amplifying unit SNS Voltage V of source terminal SNS And NMOS power tube M P Voltage V of source terminal 2 After keeping consistent, at voltage V 1 And voltage V 2 When the corresponding sizes are different, the current flows through the NMOS power tube M P The current direction of (a) is different and flows through the NMOS power tube M P Is always along voltage V 1 And voltage V 2 The larger voltage of (1) pointing in the direction of the smaller voltage, e.g. voltage V 1 Greater than voltage V 2 When it flows through NMOS power tube M P Is along voltage V 1 Pointing voltage V 2 Is a direction of (2). In particular, when the voltage V 1 Greater than voltage V 2 Then will flow through NMOS power tube M P Is set to positive current, voltage V 1 Less than voltage V 2 Will flow through NMOS power tube M P Is set to a negative current. For NMOS power tube M P The current sampling in positive and negative directions is specifically along voltage V 1 Pointing to V 2 Current sampling in the direction, or, along voltage V 2 Pointing voltage V 1 And (5) current sampling in the direction.
In order to realize current sampling in positive and negative directions, the error amplifying part is based on voltage V 1 And voltage V 2 Status providing sampling tube M SNS Is provided with a sampling tube M by an error amplifying part SNS Directional current and flow through NMOS tube M P The current direction of the two electrodes is consistent; such as through NMOS power tube M P Is the voltage V 1 Pointing voltage V 2 In this case, the sampling tube M provided by the error amplifying section SNS Is the directional current of (V) 1 Pointing voltage V SNS Is a direction of (2); such as through NMOS power tube M P Is the voltage V 2 Pointing voltage V 1 In the direction of (2), the sampling tube M provided by the error amplifying part SNS Is the directional current of (V) SNS Pointing voltage V 1 Is a direction of (2).
In the embodiment of the invention, the current output part provides the sampling tube M based on the error amplifying part SNS The sampling current required by the directional current state output of (a) is provided by the error amplifying part SNS After the directional current of (a), the current output part outputs the current according to the provided sampling tube M SNS Corresponding sampled currents are outputted from the directional current of (a).
Further, the error amplifying section includes a DC bias power supply, a first loop control current supply circuit, and a second loop control current supply circuit, wherein,
the first loop control current supply circuit and the second loop control current supply circuit are adaptively and electrically connected with the direct current bias power supply;
voltage V 1 Greater than voltage V 2 When the first loop control current supply circuit controls the sampling tube M SNS Voltage V of source terminal SNS And NMOS power tube M P Voltage V of source terminal 2 Maintain uniformity and provide a slave voltage V 1 Flow direction sampling tube M SNS A directional current at the source terminal;
voltage V 1 Less than voltage V 2 When the second loop control current supply circuit controls the sampling tube M SNS Voltage V of source terminal SNS And NMOS power tube M P Voltage V of source terminal 2 Maintain uniformity and provide a sample tube M SNS Source terminal current-to-voltage V 1 Is a directional current of (a).
In the embodiment of the invention, a direct current bias power supply is used for providing direct current bias, and a first loop is used for controlling a current supply circuit to realize the voltage V 1 Greater than voltage V 2 Loop control and current supply in state, implemented at voltage V by second loop control current supply circuit 1 Less than voltage V 2 Loop control and current supply in state. The loop control is the formed negative feedback control.
Further, the DC bias power supply comprises a PMOS tube M P3 PMOS tube M P4 PMOS tube M P5 PMOS tube M P6 PMOS tube M P7 PMOS tube M P8 Wherein, the method comprises the steps of, wherein,
PMOS tube M P3 Source terminal of (P-channel metal oxide semiconductor) PMOS tube M P4 Source terminal of (P-channel metal oxide semiconductor) PMOS tube M P6 PMOS tube M P7 The source terminal of (C) is connected with the floating voltage V FLY_VDD Connected with PMOS tube M P3 Gate terminal of (C), PMOS tube M P3 Drain terminal of PMOS tube M P6 Gate terminal of (d) and PMOS transistor M P7 Through the grid terminal of the current source I 2 And NMOS tube M N6 Drain terminal of (2), NMOS tube M N6 Gate terminal of (d) and NMOS transistor M N7 Is connected with the grid end of the transistor;
PMOS tube M P4 Gate terminal of (c) and PMOS tube M P4 Drain terminal of PMOS tube M P5 Is connected with the source terminal of the PMOS tube M P5 Gate terminal of (c) and PMOS tube M P5 Drain terminal of (2), NMOS tube M N7 Drain terminal of (d) and PMOS tube M P8 Is connected with the grid end of the transistor;
PMOS tube M P6 Drain terminal of (2) and NMOS transistor M N9 Drain terminal of (2), NMOS tube M N9 Gate terminal of (d) and NMOS transistor M N12 Is connected with the gate terminal of NMOS tube M N9 Source terminal of (2) and NMOS transistor N M8 Drain terminal of (d) and NMOS transistor M N8 Is connected with the grid end of the transistor;
PMOS tube M P7 Drain terminal of (2) and PMOS tube M P8 Source terminal of (2), NMOS transistor M N12 Is connected with the drain terminal of the first loop control current supply circuit in an adapting way, and is a PMOS tube M P8 Drain terminal of (2), NMOS tube M N12 Source terminal of (2) and NMOS transistor M N11 Is adapted to be connected to the drain terminal of the second loop control current supply circuit;
NMOS tube M N11 Gate terminal of (2) and NMOS transistor M N10 Gate terminal of (2), NMOS transistor M N10 Is connected to the drain terminal of (d) and to the current source I 3 Is connected with the output end of the current source I 3 Voltage terminal and floating voltage V of (2) FLY_VDD Connecting;
NMOS tube M N6 Source terminal of (2), NMOS transistor M N7 Source terminal of (2), NMOS transistor M N8 Source terminal of (d) and NMOS transistor M N11 The source terminal of (C) is connected to the voltage V 2 And (5) connection.
In particular, a floating power supply is used to generate a floating voltage V FLY_VDD In a power supply system with high-end NMOS power tubes, a floating power supply is an indispensable part, and no additional circuit is needed. The invention utilizes the floating power supply to ensure the NMOS power tube M P Can be acquired without increasing the cost of current sampling.
In FIG. 3, the generation of a floating voltage V is shown FLY_VDD In one specific implementation of the NMOS power tube M P Is connected with a voltage source V BOOST And a capacitor C1, wherein the NMOS power tube M P Source terminal of (2) and voltage source V BOOST Is connected with one end of a capacitor C1, and is provided with a voltage source V BOOST The positive electrode output end of the capacitor C1 is connected with the other end of the capacitor C1 to generate floating voltage V FLY_VDD 。
For NMOS power tube M P When NMOS power tube M P When turned on, the power is loaded to the NMOS power tube M P Gate terminal and sampling tube M SNS Voltage V at gate terminal G_HS Is V (V) 2 +V BOOST . Voltage source V BOOST The output voltage V BOOST The voltage is in most applications equal to the voltage V DD Or a voltage V DD Minus one diode drop. Voltage V DD The internal power supply voltage of the chip is generally 3.3V/5V.
In particular, sampling tube M SNS Through a current source I 1 And (5) grounding. General purpose medicineOvercurrent source I 1 A bias may be provided.
In FIG. 2, I 1 And I 3 The current sources with the same output current are used for ensuring that the direct current bias of the circuit is correct. Of course, in the practical implementation, a certain error can be set, namely the current source I 1 The output current is not equal to the current source I 3 The output current is at this time, and there is a fixed offset (offset) when the dc bias power is outputted. Due to PMOS tube M P3 And PMOS tube M P7 Form a current mirror, a PMOS tube M P7 Is defined by M P3 Mirror image is obtained, and the PMOS tube M can be used for implementation P7 Is set to be with current source I 1 And a current source I 3 The same output current, at this time, the current source I 1 Current source I 2 Current source I 3 The output currents are all the same.
The following is a current source I 1 Current source I 2 Current source I 3 The case where the output currents are the current I will be specifically explained.
Further, the first loop control current supply circuit includes a PMOS tube M P12 High-voltage PMOS tube M HVP2 NMOS tube M N2 NMOS tube M N1 High-voltage NMOS tube M HVN1 Wherein, the method comprises the steps of, wherein,
PMOS tube M P12 Is connected with a floating voltage V FLY_VDD PMOS tube M P12 Drain terminal of (C) and high-voltage PMOS tube M HVP2 Is connected with the source terminal of the high-voltage PMOS tube M HVP2 Gate termination voltage V of (2) 2 High-voltage PMOS tube M HVP2 Drain terminal of (2) and NMOS transistor M N2 Drain terminal of (2), NMOS tube M N2 Gate terminal of (2), NMOS transistor M N1 Is adaptively connected with the gate terminal and the current output part;
NMOS tube M N1 Source terminal of (d) and NMOS transistor M N2 The source electrode of (a) is grounded, NMOS tube M N1 Drain terminal of (d) and high voltage NMOS transistor M HVN1 Is connected with the source terminal of the high-voltage NMOS tube M HVN1 Is connected with the sampling tube M SNS Source terminal of (d) and NMOS transistor M N10 Is connected with the source terminal of the high-voltage NMOS tube M HVN1 Gate termination of (C)Voltage V DD 。
Specifically, when the voltage V 1 Greater than voltage V 2 In the case of (C) when sampling tube M SNS The voltage at the source terminal is higher than the voltage V 2 When it flows through NMOS tube M N11 The current is larger than I, so that the PMOS tube M P12 Is increased by NMOS tube M N16 Is reduced to 0. At the same time, PMOS tube M P12 Is mirrored to NMOS tube M N1 So that the sampling tube M SNS Voltage V of source terminal SNS The voltage drops and negative feedback is formed.
When sampling tube M SNS Voltage V of source terminal SNS Below voltage V 2 The above analysis process is reversed and eventually negative feedback is also formed. In particular, when sampling tube M SNS Voltage V of source terminal SNS Below voltage V 2 When flowing through NMOS tube M N11 The current of (2) is smaller than the current I, and flows through the PMOS tube M P12 Is reduced and flows through NMOS tube M N16 Is increased when the NMOS tube M N1 Current provided and current source I 1 The sum of the supplied currents is smaller than the current source I 3 The supplied current and the PMOS tube M P16 When the sum of the supplied currents, a pair of sampling tubes M can be formed SNS Voltage V of source terminal SNS Voltage pull-up and sampling tube M SNS Voltage V of source terminal SNS The voltage rises until the sampling tube M SNS Voltage V of source terminal SNS Voltage and voltage V 2 And are consistent.
In summary, the loop mechanism ensures that the voltage V is ensured in the actual work SNS Equal to voltage V 2 . Due to voltage V 1 Greater than voltage V 2 Flows through NMOS power tube M P Is positive in current direction and V 2 ＝V SNS Therefore, flows through the sampling tube M SNS Is the direction current of slave voltage V 1 Flow direction voltage V SNS At this time, through NMOS tube M 1 Tube providing sampling tube M SNS Is a directional current of (a).
Further, the second loop control current supply circuit includes a PMOS tube M P13 PMOS tube M P14 PMOS tube M P15 NMOS tube M N16 PMOS tube M P16 High-voltage PMOS tube M HVP1 Wherein, the method comprises the steps of, wherein,
PMOS tube M P13 Source terminal of (P-channel metal oxide semiconductor) PMOS tube M P14 Source terminal of (d) and PMOS tube M P15 The source terminal of (C) is connected with the floating voltage V FLY_VDD Connected with PMOS tube M P13 Gate terminal of (c) and PMOS tube M P13 Drain terminal of (2), NMOS tube M N16 Drain terminal of PMOS tube M P14 Gate terminal of (d) and PMOS transistor M P15 Is connected with the grid end of the transistor;
PMOS tube M P14 Drain terminal of (2) and PMOS tube M P16 Is connected with the source terminal of the PMOS tube M P15 Drain terminal of (C) and high-voltage PMOS tube M HVP1 Is connected with the source terminal of NMOS tube M N16 Gate terminal of (2) and NMOS transistor M N12 Source terminal of (2), NMOS transistor M N11 Drain terminal of (d) and PMOS tube M P8 Is connected with the drain end of the transistor;
NMOS tube M N16 Source terminal of (P-channel metal oxide semiconductor) PMOS tube M P16 Gate termination voltage V of (2) 2 PMOS tube M P16 Is connected with the sampling tube M SNS Source terminal of (2), NMOS transistor M N10 Is connected with the source terminal of the high-voltage PMOS tube M HVP1 Is connected to the current output section.
Specifically, at voltage V 1 Less than voltage V 2 In the case of (C) when sampling tube M SNS Voltage V of source terminal SNS Less than voltage V 2 Then flows through NMOS tube M N11 The current is smaller than the current I, so that the PMOS tube M P12 The current of (2) is reduced to 0, NMOS tube M N16 Is increased. Flows through NMOS tube M N16 Is mirrored to PMOS tube M P14 So that the voltage V SNS Rising to form negative feedback, ensuring voltage V in actual work SNS Voltage is equal to voltage V 2 。
When sampling tube M SNS Voltage V of source terminal SNS Above voltage V 2 The analysis is reversed in the above-described process, and the analysis is performed by the NMOS transistor M N1 The current flowing through and the current source I 1 The supplied current forms a pull down such that the sampling tube M SNS Voltage at source terminalV SNS Descending until the sampling tube M SNS Voltage V of source terminal SNS Equal to voltage V 2 . Finally, negative feedback control is also formed, so that a loop mechanism is utilized to ensure the voltage V in actual operation SNS Equal to voltage V 2 。
At voltage V 1 Less than voltage V 2 When flowing through NMOS power tube M P Is a negative current and V 2 ＝V SNS Through the sampling tube M SNS The current is the slave voltage V SNS Flow direction voltage V 1 At this time, pass through the PMOS tube M P14 Tube providing sampling tube M SNS Is a directional current of (a).
Further, the circuit output part comprises a PMOS tube M P1 PMOS tube M P2 PMOS tube M P1d PMOS tube M P2d Wherein, the method comprises the steps of, wherein,
PMOS tube M P1 Source terminal of (P-channel metal oxide semiconductor) PMOS tube M P2 Source terminal of (P-channel metal oxide semiconductor) PMOS tube M P1d Source terminal of (d) and PMOS tube M P2d The source terminal of (C) is connected to the voltage V DD Connected with PMOS tube M P1 Gate terminal of (c) and PMOS tube M P1 Drain terminal of (2), NMOS tube M N3 Drain terminal of PMOS tube M P2 Is connected with the grid end of the PMOS tube M P2 Drain terminal of (2) and NMOS transistor M N4 Is connected with the drain terminal of the PMOS tube M P2 Drain terminal of (2) and NMOS transistor M N4 Is connected with each other to form a sampling current I SNS1 A current first sampling output terminal of (a);
NMOS tube M N4 Gate terminal of (2) and NMOS transistor M N5 Gate terminal of (2), NMOS transistor M N5 Is connected with the drain terminal of the high-voltage PMOS tube M HVP1 Drain terminal of (2), NMOS tube M N3d Connected with PMOS tube M P1d Gate terminal of (c) and PMOS tube M P1d Drain terminal of (2), NMOS tube M N3d Drain terminal of (d) and PMOS tube M P2d Is connected with the grid end of the PMOS tube M P2d Drain terminal of (2) and NMOS transistor M N4d Is connected with the drain terminal of the PMOS tube M P2d Drain terminal of (2) and NMOS transistor M N4d Is connected with each other to form a sampling current I SNSN2 A current second sampling output terminal of (a);
NMOS tube M N4d Gate terminal of (2) and NMOS transistor M N1 Gate terminal of (2), NMOS transistor M N3 Gate terminal of (2), NMOS transistor M N2 Gate terminal of (2), NMOS transistor M N2 Drain terminal of (d) and high-voltage PMOS tube M HVP2 Is connected with the drain end of the transistor;
NMOS tube M N3 Source terminal of (2), NMOS transistor M N4 Source terminal of (2), NMOS transistor M N5 Source terminal of (2), NMOS transistor M N3d Source terminal of (d) and NMOS transistor M N4d The source terminals of (a) are grounded.
Specifically, as can be seen from the above description, at voltage V 1 Greater than voltage V 2 In the case of (C), if the sampling tube M SNS Voltage V of source terminal SNS Greater than voltage V 2 When flowing through the PMOS tube M P12 Is increased and flows through NMOS tube M N16 The current of (2) will decrease to 0 when sampling tube M SNS Voltage V of source terminal SNS Equal to voltage V 2 When flowing through the PMOS tube M P12 Is kept maximum, flows through NMOS tube M N16 Is 0; then, as can be seen from fig. 2, the sampled current I is output through the current first sampling output terminal after mirroring the current mirror SNS1 Will increase to a stable state to obtain a sampling current I output by the second sampling output end SNSN2 Will decrease to 0. When sampling tube M SNS Voltage V of source terminal SNS And voltage V 2 When the sampling currents are equal, the sampling current I output by the second sampling output end of the current SNSN2 Is 0, the sampling current I output by the current first sampling output end SNS1 The required stable sampling current is obtained.
At voltage V 1 Greater than voltage V 2 In the case of (a), sampling tube M SNS Voltage V of source terminal SNS Less than voltage V 2 Reference may be made to the above description for specific details, and details are not repeated here.
Further, as can be seen from the above description, at voltage V 1 Less than voltage V 2 In the case of (C), if the sampling tube M SNS Voltage V of source terminal SNS Less than voltage V 2 When flowing through the PMOS tube M P12 Will gradually decrease to0, flow through NMOS tube M N16 Is increased when the current of the sampling tube M SNS Voltage V of source terminal SNS Equal to voltage V 2 When flowing through the PMOS tube M P12 Current flowing through NMOS tube M N16 Is kept at a maximum; then, as can be seen from fig. 2, the sampled current I is output through the current first sampling output terminal after mirroring the current mirror SNS1 Will gradually decrease to 0, and the sampling current I output by the second sampling output end of the current SNSN2 And the current is increased to be stable, and the sampling current is obtained. When sampling tube MSNS source terminal voltage V SNS And voltage V 2 When the sampling currents are equal, the sampling current I output by the first sampling output end of the current SNSN1 Is 0, the sampling current I output through the current second sampling output end SNS2 The required stable sampling current is obtained.
At voltage V 1 Less than voltage V 2 In the case of (a), sampling tube M SNS Voltage V of source terminal SNS Greater than voltage V 2 Reference may be made to the above description for specific details, and details are not repeated here.
For ease of description, assume that all current mirror ratios are 1:1 is provided with I MP2 ＝I MN4d ＝I MN1 ，I MN4 ＝I MP2d ＝I MP14 The method comprises the steps of carrying out a first treatment on the surface of the At this time, it is possible to obtain:
Figure BDA0003802191120000101
as can be taken from the above description and fig. 4 of the specification, at voltage V 1 >Voltage V 2 At the time of current sampling, I SNS2 =0; at voltage V 1 <Voltage V 2 At the time of current sampling, I SNS1 =0. In FIG. 4, I POWER For flowing through NMOS power tube M P Is set in the above-described range). In FIG. 4, ΔV is the voltage V 1 And voltage V 2 Is a difference in (c).
In specific implementation, the specific proportion of the current mirror can be selected according to actual practice, and after the proportion of the current mirror is determined, the corresponding sampling current situation can be obtained according to the above description, and the specific description is omitted here.
In using the sampling tube M SNS For flowing through NMOS power tube M P Sampling tube M during current sampling SNS Is formed by NMOS power tube M P Is obtained by current mirror of (2), so that the whole circuit can respond to the voltage V 1 And voltage V 2 Based on the relation between the sampling currents I SNSN1 Or sampling current I SNS2 I.e. to form the desired stable sampling current.
Further, the device also comprises an NMOS tube M N17 NMOS tube M N17 Source terminal voltage V of (2) 2 NMOS tube M N17 Is connected with the sampling tube M at the drain end SNS Source terminal of (d) and NMOS transistor M N10 Is connected with the source terminal of the transistor;
NMOS tube M N17 The gate terminal of (a) is connected with the enable inversion signal ENN, and the NMOS tube M is enabled by the enable inversion signal ENN during current sampling N17 In the off state.
In the embodiment of the invention, when current sampling work is performed, an enable inversion signal ENN is 0; when the non-current application is in operation, the enable inversion signal ENN is high.
To sum up, the bidirectional high-precision NMOS power tube current sampling method of the invention can be obtained, specifically, for any NMOS power tube M P And performing required current sampling based on the current sampling circuit.
In specific implementation, the method and process for sampling current by using the current sampling circuit can refer to the above description, and will not be repeated here.
For NMOS power tube M P The invention utilizes a sampling tube M SNS Duplicating NMOS power tube M P The state of the (2) is realized by utilizing the matching of the error amplifying part and the current output part, and no extra off-chip device is needed; floating voltage V in error amplifying section FLY_VDD The floating power supply in the high-end NMOS power tube can be reused, the cost is not increased, and the use is convenient. Loop control and providing sampling tube M by error amplifying part SNS The required current can realize the sampling of positive current and negative current, reduce the number of sampling tubes and optimize the chip surfaceThe product reduces the cost of the chip internal sampling and improves the reliability of the chip internal sampling.

Claims (8)

1. A bidirectional high-precision NMOS power tube current sampling circuit is characterized by comprising:
sampling connection part comprising NMOS power tube M P For duplicating NMOS power tube M P Status sampling tube M SNS Sampling tube M SNS Drain terminal of (2), NMOS power tube M P The drain terminals of (a) are connected with the voltage V 1 NMOS power tube M P Source terminal voltage V of (2) 2 ；
Error amplifying part and NMOS power tube M in sampling connecting part P Is provided, and a sampling tube M SNS For adapting the source terminal of the sampling tube M SNS The voltage at the source terminal is loop controlled so that the sampling tube M SNS Voltage V of source terminal SNS And NMOS power tube M P Voltage V of source terminal 2 Keeping consistency;
a current output part which is connected with the error amplifying part in an adapting way, and the error amplifying part is based on the voltage V 1 And voltage V 2 Status providing sampling tube M SNS The current output section provides a sampling tube M based on the error amplifying section SNS Outputting a required sampling current in a direction current state; wherein the error amplifying part provides a sampling tube M SNS Directional current and flow through NMOS tube M P The current direction of the two electrodes is consistent;
the error amplifying section includes a DC bias power supply, a first loop control current supply circuit, and a second loop control current supply circuit,
the first loop control current supply circuit and the second loop control current supply circuit are adaptively and electrically connected with the direct current bias power supply;
voltage V 1 Greater than voltage V 2 When the first loop control current supply circuit controls the sampling tube M SNS Voltage V of source terminal SNS And NMOS power tube M P Voltage V of source terminal 2 Maintain uniformity and provide a slave voltage V 1 Flow direction sampling tube M SNS A directional current at the source terminal;
voltage V 1 Less than voltage V 2 When the second loop control current supply circuit controls the sampling tube M SNS Voltage V of source terminal SNS And NMOS power tube M P Voltage V of source terminal 2 Maintain uniformity and provide a sample tube M SNS Source terminal current-to-voltage V 1 Is a directional current of (a);
the direct-current bias power supply comprises a PMOS tube M P3 PMOS tube M P4 PMOS tube M P5 PMOS tube M P6 PMOS tube M P7 PMOS tube M P8 Wherein, the method comprises the steps of, wherein,
PMOS tube M P3 Source terminal of (P-channel metal oxide semiconductor) PMOS tube M P4 Source terminal of (P-channel metal oxide semiconductor) PMOS tube M P6 PMOS tube M P7 The source terminal of (C) is connected with the floating voltage V FLY_VDD Connected with PMOS tube M P3 Gate terminal of (C), PMOS tube M P3 Drain terminal of PMOS tube M P6 Gate terminal of (d) and PMOS transistor M P7 Through the grid terminal of the current source I 2 And NMOS tube M N6 Drain terminal of (2), NMOS tube M N6 Gate terminal of (d) and NMOS transistor M N7 Is connected with the grid end of the transistor;
PMOS tube M P4 Gate terminal of (c) and PMOS tube M P4 Drain terminal of PMOS tube M P5 Is connected with the source terminal of the PMOS tube M P5 Gate terminal of (c) and PMOS tube M P5 Drain terminal of (2), NMOS tube M N7 Drain terminal of (d) and PMOS tube M P8 Is connected with the grid end of the transistor;
PMOS tube M P6 Drain terminal of (2) and NMOS transistor M N9 Drain terminal of (2), NMOS tube M N9 Gate terminal of (d) and NMOS transistor M N12 Is connected with the gate terminal of NMOS tube M N9 Source terminal of (2) and NMOS transistor M N8 Drain terminal of (d) and NMOS transistor M N8 Is connected with the grid end of the transistor;
PMOS tube M P7 Drain terminal of (2) and PMOS tube M P8 Source terminal of (2), NMOS transistor M N12 Is connected with the drain terminal of the first loop control current supply circuit in an adapting way, and is a PMOS tube M P8 Drain terminal of (2), NMOS tube M N12 Source terminal of (2) and NMOS transistor M N11 Drain terminal of (2) and second ringThe circuit control current supply circuit is connected in a adapting way;
NMOS tube M N11 Gate terminal of (2) and NMOS transistor M N10 Gate terminal of (2), NMOS transistor M N10 Is connected to the drain terminal of (d) and to the current source I 3 Is connected with the output end of the current source I 3 Voltage terminal and floating voltage V of (2) FLY_VDD Connecting;
NMOS tube M N6 Source terminal of (2), NMOS transistor M N7 Source terminal of (2), NMOS transistor M N8 Source terminal of (d) and NMOS transistor M N11 The source terminal of (C) is connected to the voltage V 2 And (5) connection.
2. The bidirectional high-precision NMOS power tube current sampling circuit of claim 1, characterized by: the first loop control current supply circuit comprises a PMOS tube M P12 High-voltage PMOS tube M HVP2 NMOS tube M N2 NMOS tube M N1 High-voltage NMOS tube M HVN1 Wherein, the method comprises the steps of, wherein,
PMOS tube M P12 Is connected with a floating voltage V FLY_VDD PMOS tube M P12 Drain terminal of (C) and high-voltage PMOS tube M HVP2 Is connected with the source terminal of the high-voltage PMOS tube M HVP2 Gate termination voltage V of (2) 2 High-voltage PMOS tube M HVP2 Drain terminal of (2) and NMOS transistor M N2 Drain terminal of (2), NMOS tube M N2 Gate terminal of (2), NMOS transistor M N1 Is adaptively connected with the gate terminal and the current output part;
NMOS tube M N1 Source terminal of (d) and NMOS transistor M N2 The source electrode of (a) is grounded, NMOS tube M N1 Drain terminal of (d) and high voltage NMOS transistor M HVN1 Is connected with the source terminal of the high-voltage NMOS tube M HVN1 Is connected with the sampling tube M SNS Source terminal of (d) and NMOS transistor M N10 Is connected with the source terminal of the high-voltage NMOS tube M HVN1 Gate termination voltage V of (2) DD 。
3. The bidirectional high-precision NMOS power tube current sampling circuit of claim 2, characterized by: the second loop control current supply circuit comprises a PMOS tube M P13 PMOS tube M P14 PMOS tube M P15 NMOS tube M N16 PMOS tube M P16 High-voltage PMOS tube M HVP1 Wherein, the method comprises the steps of, wherein,
PMOS tube M P13 Source terminal of (P-channel metal oxide semiconductor) PMOS tube M P14 Source terminal of (d) and PMOS tube M P15 The source terminal of (C) is connected with the floating voltage V FLY_VDD Connected with PMOS tube M P13 Gate terminal of (c) and PMOS tube M P13 Drain terminal of (2), NMOS tube M N16 Drain terminal of PMOS tube M P14 Gate terminal of (d) and PMOS transistor M P15 Is connected with the grid end of the transistor;
PMOS tube M P14 Drain terminal of (2) and PMOS tube M P16 Is connected with the source terminal of the PMOS tube M P15 Drain terminal of (C) and high-voltage PMOS tube M HVP1 Is connected with the source terminal of NMOS tube M N16 Gate terminal of (2) and NMOS transistor M N12 Source terminal of (2), NMOS transistor M N11 Drain terminal of (d) and PMOS tube M P8 Is connected with the drain end of the transistor;
NMOS tube M N16 Source terminal of (P-channel metal oxide semiconductor) PMOS tube M P16 Gate termination voltage V of (2) 2 PMOS tube M P16 Is connected with the sampling tube M SNS Source terminal of (2), NMOS transistor M N10 Is connected with the source terminal of the high-voltage PMOS tube M HVP1 Is connected to the current output section.
4. The bidirectional high-precision NMOS power tube current sampling circuit of claim 2, characterized by: the circuit output part comprises a PMOS tube M P1 PMOS tube M P2 PMOS tube M P1d PMOS tube M P2d Wherein, the method comprises the steps of, wherein,
PMOS tube M P1 Source terminal of (P-channel metal oxide semiconductor) PMOS tube M P2 Source terminal of (P-channel metal oxide semiconductor) PMOS tube M P1d Source terminal of (d) and PMOS tube M P2d The source terminal of (C) is connected to the voltage V DD Connected with PMOS tube M P1 Gate terminal of (c) and PMOS tube M P1 Drain terminal of (2), NMOS tube M N3 Drain terminal of PMOS tube M P2 Is connected with the grid end of the PMOS tube M P2 Drain terminal of (2) and NMOS transistor M N4 Is connected with the drain terminal of the PMOS tube M P2 Drain terminal of (2) and NMOS transistor M N4 Is connected with each other to form a sampling current I SNS1 Is (1) the current of the (a)A first sampling output;
NMOS tube M N4 Gate terminal of (2) and NMOS transistor M N5 Gate terminal of (2), NMOS transistor M N5 Is connected with the drain terminal of the high-voltage PMOS tube M HVP1 Drain terminal of (2), NMOS tube M N3d Connected with PMOS tube M P1d Gate terminal of (c) and PMOS tube M P1d Drain terminal of (2), NMOS tube M N3d Drain terminal of (d) and PMOS tube M P2d Is connected with the grid end of the PMOS tube M P2d Drain terminal of (2) and NMOS transistor M N4d Is connected with the drain terminal of the PMOS tube M P2d Drain terminal of (2) and NMOS transistor M N4d Is connected with each other to form a sampling current I SNSN2 A current second sampling output terminal of (a);
NMOS tube M N4d Gate terminal of (2) and NMOS transistor M N1 Gate terminal of (2), NMOS transistor M N3 Gate terminal of (2), NMOS transistor M N2 Gate terminal of (2), NMOS transistor M N2 Drain terminal of (d) and high-voltage PMOS tube M HVP2 Is connected with the drain end of the transistor;
NMOS tube M N3 Source terminal of (2), NMOS transistor M N4 Source terminal of (2), NMOS transistor M N5 Source terminal of (2), NMOS transistor M N3d Source terminal of (d) and NMOS transistor M N4d The source terminals of (a) are grounded.
5. The bidirectional high precision NMOS power tube current sampling circuit of any one of claims 1 to 4, characterized by: also comprises an NMOS tube M N17 NMOS tube M N17 Source terminal voltage V of (2) 2 NMOS tube M N17 Is connected with the sampling tube M at the drain end SNS Source terminal of (d) and NMOS transistor M N10 Is connected with the source terminal of the transistor;
NMOS tube M N17 The gate terminal of (a) is connected with the enable inversion signal ENN, and the NMOS tube M is enabled by the enable inversion signal ENN during current sampling N17 In the off state.
6. The bidirectional high precision NMOS power tube current sampling circuit of any one of claims 1 to 4, characterized by: sampling tube M SNS Through a current source I 1 And (5) grounding.
7. The bidirectional high precision NMOS power tube current sampling circuit of any one of claims 1 to 4, characterized by: NMOS power tube M P And sampling tube M SNS The width-to-length ratio of the corresponding conduction channel is X:1, X > 1.
8. A bidirectional high-precision NMOS power tube current sampling method is characterized in that any NMOS power tube M is subjected to P The current sampling circuit according to any one of claims 1 to 7, wherein the current sampling circuit performs a desired current sampling.
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