CN107659151B - Buck load current detection circuit and method without external sampling resistor - Google Patents
Buck load current detection circuit and method without external sampling resistor Download PDFInfo
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- CN107659151B CN107659151B CN201710272315.5A CN201710272315A CN107659151B CN 107659151 B CN107659151 B CN 107659151B CN 201710272315 A CN201710272315 A CN 201710272315A CN 107659151 B CN107659151 B CN 107659151B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/0092—Arrangements for measuring currents or voltages or for indicating presence or sign thereof measuring current only
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0009—Devices or circuits for detecting current in a converter
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The Buck converter load current detection circuit without an external sampling resistor comprises a current sampling tube (Q3), a current sampling circuit (31), a sampling and holding circuit (33) and a low-pass filter (32); when the first Buck output power tube (Q1) is conducted, the Buck converter load current detection circuit utilizes a current sampling tube (Q3) and a current sampling circuit (31) to sample and obtain the conducting current of the first Buck output power tube (Q1); when the first Buck output power tube (Q1) is closed, a sampling hold circuit (33) and a low-pass filter (32) are utilized to generate a feedback current signal, and an external load current feedback signal is simulated to control the output current of the Buck converter. According to the invention, an external sampling resistor is not needed, the design of a peripheral circuit is simplified, the energy loss is reduced, the overall efficiency is improved, and the high-precision constant-current charging same as external sampling can be realized by adopting a proper specific circuit.
Description
Technical Field
The invention relates to a direct current electric energy conversion circuit or a control device; in particular, to a Buck-conversion dc power conversion circuit, and more particularly, to a Buck-conversion dc power conversion device and method with load current detection.
Background
In a switching power supply circuit (SWITCHING REGULATOR) used in a direct current electric energy conversion circuit or a control device in the prior art, a Buck converter is an important type of a DC/DC (direct current to direct current) converter, and is mainly suitable for situations that an input voltage is higher than an output voltage, and in order to realize constant current output of the Buck converter, load current needs to be detected, that is, the load current of the Buck converter needs to be detected accurately and fed back to a control end of the Buck converter to control the Buck converter so as to keep constant current output of the Buck converter.
The existing Buck load current detection technology is to connect a small sampling resistor in series between an inductor and an output signal for detection, and aiming at the detection method, the average current flowing through the resistor is the output load current, so that the voltage at two ends of the sampling resistor is detected at any moment through a sampling detection circuit, and then amplified, and the average value is obtained, namely the voltage signal is converted into a voltage signal with a corresponding proportion of the load current; in the CC control loop, the obtained sampling voltage and the reference voltage are subjected to loop error comparison to be equal, so that the system works in a constant current output mode.
As shown in fig. 1, a block diagram of a load current detection structure in the prior art is shown, an external current sampling resistor Rsen is connected in series between an output Voltage (VOUT) output terminal and an external inductor L1, an inductor current flows through the current sampling resistor Rsen to generate a voltage drop, an internal current sampling circuit converts the voltage drop on the current sampling resistor Rsen into an internal current signal Isen, the internal current signal Isen is converted into a voltage signal Vsen representing the magnitude of the load current through an internal resistor Rs, because the voltage drop on the current sampling resistor Rsen is ripple, the internally generated voltage signal Vsen needs to pass through one or more low-pass filters to be stabilized into a feedback voltage signal vsen_fb approximate to direct current, the feedback voltage signal vsen_fb is transmitted to an error amplifier controlled by an internal CC constant current of a Buck converter, and when the Buck converter is in a CC constant current control interval, the output current is increased correspondingly until a CC loop acts and stabilizes to a target output current or maximum output current.
The existing Buck load current detection technology realizes load detection by means of an off-chip serial sampling resistor, and the scheme has the following disadvantages that 1, a PIN PIN required by current sampling is additionally required by a chip, and the method is quite unfavorable in chip application with shortage of PIN resources and compact space requirements; 2. when the external sampling resistor works normally, current flows to cause energy loss and efficiency reduction; 3. the precision requirement of the externally connected sampling resistor is high, and the high-precision resistor is increased, so that the cost of the whole application system is correspondingly increased.
Noun interpretation:
DCDC is an abbreviation of english Direct current Direct current, and chinese means that dc voltage is converted into dc voltage;
the BUCK converter means in the present application a BUCK DC/DC converter circuit employing BUCK converter mode;
CC is herein defined as constant current, i.e. constant current
NMOS is an abbreviation of Negative channel-Metal-Oxide-Semiconductor, i.e., N-type Metal Oxide Semiconductor;
PMOS is an abbreviation for Positive channel-Metal-Oxide-Semiconductor, i.e., P-type Metal Oxide Semiconductor;
PWM is an abbreviation for english Pulse Width Modulation, chinese meaning pulse width modulation; the Pulse Width Modulation (PWM) switch type voltage stabilizing circuit achieves the purpose of stabilizing output voltage by adjusting the duty ratio of the PWM switch type voltage stabilizing circuit under the condition that the output frequency of the control circuit is unchanged.
Disclosure of Invention
The invention aims to solve the technical problems of avoiding the defects of the prior art and providing a Buck converter load current detection circuit and method without an external sampling resistor, wherein the Buck Buck conversion circuit requiring constant current control realizes load current detection without the external sampling resistor, reduces chip pins and saves energy consumption and cost caused by the external resistor.
The technical scheme adopted for solving the technical problems is that the Buck converter load current detection circuit without an external sampling resistor comprises a current sampling tube for mirroring the current of a first Buck output power tube, a current sampling circuit for sampling the current output from the drain electrode of the current sampling tube, a sampling and holding circuit for sampling and holding the peak current at the closing moment of the first Buck output power tube and a low-pass filter for low-pass filtering of the output voltage signal of the sampling and holding circuit; the source electrode of the current sampling tube is electrically connected with an external input voltage source, the grid electrode of the current sampling tube is grounded, and the drain electrode of the current sampling tube is electrically connected with the first input terminal of the current sampling circuit; a second input terminal of the current sampling circuit is electrically connected with an external input voltage source; the third input terminal of the current sampling circuit is electrically connected with the drain electrode of the first Buck output power tube; the output terminal of the current sampling circuit is electrically connected with the first input terminal of the sampling hold circuit, the output terminal of the current sampling circuit is electrically connected with one end of an internal current sampling resistor, and the other end of the internal current sampling resistor is grounded; the output terminal of the sampling hold circuit is electrically connected with the input terminal of the low-pass filter, and the output signal of the output terminal of the low-pass filter is used as a load current sampling signal output by the load current detection circuit of the Buck converter.
The current sampling circuit comprises a fourth PMOS tube for obtaining sampling current from the current sampling tube, a current sampling operational amplifier for sampling the drain voltage signal of the first Buck output power tube, a first switch and a second switch for controlling input signals; the first switch receives control of a first control signal, and the second switch receives non-signal control of the first control signal; the first input terminal of the current sampling operational amplifier is electrically connected with one end of the first switch; the other end of the first switch is electrically connected with the drain electrode of the first Buck output power tube; the first input terminal of the current sampling operational amplifier is electrically connected with one end of the second switch; the other end of the second switch is electrically connected with an external input voltage source; the source electrode of the fourth PMOS tube is used as an input terminal of the current sampling circuit and is electrically connected with the drain electrode of the current sampling tube, the grid electrode of the fourth PMOS tube is electrically connected with the output terminal of the current sampling operational amplifier, the second input terminal of the current sampling operational amplifier is electrically connected with the source electrode of the fourth PMOS tube, and the drain electrode of the fourth PMOS tube is used as the output terminal of the current sampling circuit.
The sampling hold circuit comprises a sampling hold capacitor for holding the voltage of an input signal, a Buffer circuit for buffering the input signal and a third switch for controlling the input signal of the sampling hold circuit; the third switch is controlled by the first control signal; the input terminal of the Buffer circuit is electrically connected with one end of the sample-hold capacitor, and the other end of the sample-hold capacitor is grounded; the input terminal of the Buffer circuit is electrically connected with one end of the third switch, and the other end of the third switch is used as a first input terminal of the sample hold circuit and is electrically connected with the non-grounding end of the internal current sampling resistor; the output terminal of the Buffer circuit serves as the output terminal of the sample-and-hold circuit.
The low-pass filter comprises a low-pass filter resistor and a low-pass filter capacitor, and one end of the low-pass filter resistor is used as the input end of the low-pass filter and is electrically connected with the output end of the sample hold circuit; the other end of the low-pass filter resistor is used as the output end of the low-pass filter and is electrically connected with one end of the low-pass filter capacitor, and the other end of the low-pass filter capacitor is grounded.
The Buck converter load current detection circuit further comprises a reference voltage generation circuit, wherein the reference voltage generation circuit comprises a current source and a reference voltage circuit resistor; the positive electrode of the current source is electrically connected with an external input voltage source, and the negative electrode of the current source is used as an output terminal of the reference voltage generating circuit; the negative electrode of the current source is also electrically connected with one end of the reference voltage circuit resistor, and the other end of the reference voltage circuit resistor is grounded.
The Buck converter load current detection circuit further comprises an error amplifier for comparing feedback current voltage signals with reference voltage, and a first input terminal of the error amplifier is electrically connected with an output terminal of the reference voltage generation circuit; a second input terminal of the error amplifier is electrically connected to an output terminal of the low pass filter.
The current sampling operational amplifier comprises an auto-zeroing chopper operational amplifier, a low-error operational amplifier and an auto-zeroing operational amplifier.
The Buck converter load current detection circuit without the external sampling resistor further comprises a sampling compensation circuit for detecting output voltage and obtaining compensation current through the output voltage in a time period when the first Buck output power tube is closed and the second Buck output power tube is conducted; the sampling and holding circuit further comprises a second input terminal, and the second input terminal of the sampling and holding circuit is electrically connected with the output terminal of the sampling and compensating circuit; the input terminal of the sampling compensation circuit is used for being electrically connected with a voltage output terminal for outputting voltage to the outside.
The sampling hold circuit further comprises a fourth switch electrically connected with the sampling compensation circuit; the fourth switch receives the control of the non-signal of the first control signal; one end of the fourth switch is used as a second input terminal of the sampling hold circuit and is electrically connected with one end of the sampling compensation circuit; a signal input from a second input terminal of the sample hold circuit is controlled by a non-signal of a first control signal; the other end of the fourth switch is electrically connected with an input terminal of the Buffer circuit.
The sampling compensation circuit comprises a first resistor, a second resistor, a third resistor, a compensation amplifier, a fifth MOS tube, a sixth MOS tube and a seventh MOS tube; one end of the first resistor is electrically connected with an output terminal of the output voltage VOUT and is used as an input terminal of the sampling compensation circuit; the other end of the first resistor is electrically connected with the negative electrode input end of the compensation amplifier; one end of the second resistor is electrically connected with the negative electrode input end of the compensation amplifier; the other end of the second resistor is grounded; one end of the third resistor is electrically connected with an output terminal for outputting voltage; the other end of the third resistor is electrically connected with the positive electrode input end of the compensation amplifier; the positive electrode input end of the compensation amplifier is also electrically connected with the source electrode of the fifth MOS tube; the grid electrode of the fifth MOS tube is electrically connected with the output end of the compensation amplifier; the drain electrode of the fifth MOS tube is electrically connected with the drain electrode of the sixth MOS tube; the source electrode of the sixth MOS tube is electrically connected with the source electrode of the seventh MOS tube; the grid electrode of the sixth MOS tube is electrically connected with the grid electrode of the seventh MOS tube; the sixth MOS tube and the sixth MOS tube form a current mirror; the drain electrode of the seventh MOS tube is used as an output terminal of the sampling compensation circuit and is used for outputting compensation current.
The current sampling operational amplifier comprises a low-error operational amplifier, a chopper-type operational amplifier and an auto-zeroing operational amplifier. The low error op-amp, low offset operation amplifier, may be a chopper op-amp, chopping operation amplifier, or Auto-zeroed op-amp, auto-Zeroing operation amplifier. Whatever operational amplifier and its equivalent transformation form are within the protection scope of this patent.
The technical scheme adopted for solving the technical problems can also be a Buck load current detection method without an external sampling resistor based on the Buck converter load current detection circuit, comprising the following steps: step 1: the current sampling tube and a first Buck output power tube in the Buck voltage conversion circuit form a mirror image pair tube, and when the first Buck output power tube is conducted and a second Buck output power tube is closed, the current sampling tube acquires and obtains the conducting current of the first Buck output power tube, namely load current; step 2: when the first Buck output power tube is switched from the on state to the off state, the sampling and holding circuit obtains the voltage of the current sampling tube at the current moment, and the sampling and holding circuit and the low-pass filter simulate the follow current, namely the load current, when the first Buck output power tube is closed and the second Buck output power tube Q2 is conducted.
The technical scheme adopted for solving the technical problems can also be a Buck load current detection method without an external sampling resistor based on the Buck converter load current detection circuit, comprising the following steps: step 1: the current sampling tube and a first Buck output power tube in the Buck voltage conversion circuit form a mirror image pair tube, and when the first Buck output power tube is conducted and a second Buck output power tube Q2 is closed, the current sampling tube acquires and obtains the conducting current of the first Buck output power tube, namely load current; step 2: when the first Buck output power tube is switched from a conducting state to a closing state, the sampling and holding circuit obtains the voltage of the current sampling tube at the current moment, and the first Buck output power tube is jointly simulated to be closed through the sampling and holding circuit and the low-pass filter, and the follow current, namely the load current, when the second Buck output power tube is conducted; the step 2 comprises the following step 3: and during the period that the first Buck output power tube is closed and the second Buck output power tube is conducted, the sampling compensation circuit detects the output voltage of the Buck circuit and obtains compensation current through the output voltage, and the compensation current is used for compensating the follow current when the second Buck output power tube is conducted, so that the follow current is closer to the real load current.
Compared with the prior art, the invention has the beneficial effects that: 1. in the chip applying the design circuit scheme of the invention, the load current detection can be realized without connecting a sampling resistor again; 2. chip pins are saved, so that load current detection can be realized in chip application with small space and few pins, and Buck constant current control is realized; 3. the sampling resistor is not required to be externally connected again, so that the power consumption and the cost caused by an external resistor when the chip is applied are also saved; 4. through the combination of the sample hold circuit and the compensation circuit, the estimation of the inductance current is realized, the inductance current is simulated, the accuracy of load current detection is improved, and the circuit in the chip is simplified.
Drawings
FIG. 1 is a block diagram of a prior art circuit configuration of a load current detection implementation of a Buck conversion circuit;
FIG. 2 is a block diagram of the circuit configuration of one of the preferred embodiments of the present invention;
FIG. 3 is a schematic diagram of an implementation circuit of a preferred embodiment of the present invention;
FIG. 4 is a waveform timing diagram of one of the preferred embodiments of the present invention;
FIG. 5 is an electrical schematic diagram of the sample compensation circuit 34 in a preferred embodiment of the present invention;
fig. 6 is an electrical schematic diagram of the current sampling op amp 37 in a preferred embodiment of the present invention.
Detailed Description
Embodiments of the present invention are described in further detail below with reference to the drawings.
The invention aims to provide a Buck converter load current detection circuit without a sampling resistor, which solves the problem that an external sampling resistor is needed under the condition of Buck output load current detection.
In the Buck converter, the Buck is assumed to work in a CCM (continuous working mode) mode, the output load current is equal to the average value of the inductance current, under the condition that no sampling resistor exists, the current on the inductance is difficult to directly sample, only the power tube and the freewheel tube are considered to serve as paths, so that the inductance current can be indirectly detected by the current flowing on the power tube and the follow-up tube, in a conduction period T, D is the duty ratio of the Buck converter, the current flowing through the PMOS tube of the high-order power tube is equal to the current of the inductance, at the moment, the current flowing through the follow-up tube is in the period 0, 0-DT, only the current flowing through the PMOS tube needs to be detected, in the period DT-1-D, the current flowing through the follow-up tube is equal to the current of the inductance when the freewheel tube is opened, and the current flowing through the high-order PMOS tube is in the period 0, and only the current flowing through the follow-up tube needs to be detected; therefore, the inductive current can be obtained by sampling the sum of the currents flowing through the PMOS tube and the freewheel tube.
The invention relates to a Buck converter load current detection circuit without an external sampling resistor, which has the basic idea that the output load current is obtained by accurately detecting the current flowing through a power tube, the current of a high-order power tube is easy to sample, the current of a low-order power tube can be detected, an extra circuit is additionally needed to be additionally arranged, and when the external Schottky diode is used by the freewheel tube, the current of the follow-up tube is difficult to sample, so that the detection circuit is simplified and optimized, and the invention is more suitable for the situation that the Schottky diode is used by the freewheel tube.
In the specific embodiment of the present invention shown in fig. 2 and 3, the high-order power tube corresponds to the first Buck output power tube Q1, the low-order power tube corresponds to the second Buck output power tube Q2, the first Buck output power tube Q1 is a PMOS tube, and the second Buck output power tube Q2 is not an NMOS tube, although only limited embodiments are shown in the embodiment drawings, and in practical application, the type of the tube may be other types of tubes instead, so long as the switching power output of the Buck conversion circuit can be realized.
The basic block diagram of the preferred embodiment of the present invention shown in fig. 2 includes an output voltage sampling module 40, a current detection circuit 30 for detecting load current, a CC/CV error amplifier module for controlling the CC/CV loop, a ramp generation circuit 60 for generating a ramp signal, a PWM comparator 70 for comparing the ramp with the error amplifier output, a logic control module 80 for controlling the power transistor, a power transistor stage 20, an output inductance L1 and an output capacitance C8, and the rest of the circuit configuration is identical to the basic block diagram of the prior art shown in fig. 1 except for the current detection circuit 30.
As shown in fig. 2, the input signal of the output voltage sampling module 40 includes an output voltage VOUT signal, and the output voltage feedback signal VFB of the output voltage sampling module 40 is a divided voltage of the output voltage VOUT signal. The output voltage feedback signal VFB output by the output voltage sampling module 40 is connected to the CC/CV error amplifier as one of the input control signals of the CC/CV error amplifier.
As shown in fig. 2, the current detection circuit module 30 outputs a load current feedback signal vsen_fb to the CC/CV error amplifier as a second input control signal of the CC/CV error amplifier; the load current feedback signal vsen_fb is a feedback voltage signal representing the load current.
As shown in fig. 2, the input control signal of the CC/CV error amplifier further includes a reference voltage signal VBG and a CC loop reference voltage signal VREFL generated by an internal reference circuit; the output voltage feedback signal VFB, the load current feedback signal vsen_fb, the reference voltage signal VBG and the CC loop reference voltage signal VREFL are all connected to the CC/CV error amplifier block 50 and are input control signals to the CC/CV error amplifier block 50.
As shown in fig. 2, in the CC/CV error amplifier, the CC error amplifier detects a first error signal VCL of the load current feedback signal vsen_fb and the CC loop reference voltage signal VREFL; the CV error amplifier detects a second error signal VCV of the output voltage feedback signal VFB and the reference voltage signal VBG; the corresponding signal is selected from the first error signal VCL and the second error signal VCV to be used as a control signal VC of the PWM comparison controller;
as shown in fig. 2, the ramp generating circuit 60 outputs a sawtooth wave signal Vsaw to the PWM comparator; the PWM comparator 70 compares the input sawtooth wave signal Vsaw with the PWM comparison controller control signal VC, and the PWM comparator 70 outputs a logic controller control signal to the logic control module 80; the logic control module 80 outputs a high-order power tube control signal GP to the gate of the PMOS transistor Q1, which is the high-order power tube controlling the power tube stage 20; meanwhile, the logic control module 80 outputs a low-order power transistor control signal GN to the gate of the NMOS transistor Q2, which is the continuous flow transistor of the power transistor stage 20.
As shown in fig. 2, the current detection circuit 30 includes a current sampling tube Q3, a current sampling circuit 31, a sample hold circuit 33, a sample compensation circuit 34, a low-pass filter circuit 32, and an internal current sampling resistor Rs; the source electrode of the current sampling tube Q3 is electrically connected with an external input voltage source VIN, the grid electrode of the current sampling tube Q3 is grounded, and the drain electrode of the current sampling tube Q3 is electrically connected with the input terminal of the current sampling circuit 31; the current sampling tube Q3 is in a normally open state.
As shown in fig. 2, a first input terminal of the current sampling circuit 31 inputs a drain voltage signal Vs of the current sampling tube Q3, and a second input terminal of the current sampling circuit 31 inputs an external voltage input signal VIN of an external input voltage source; a voltage signal representing the magnitude of the inductor current, namely a voltage signal at a circuit node LX point, namely a drain voltage signal of the first Buck output power tube Q1 is input from a third input terminal of the current sampling circuit 31; the output terminal of the current sampling circuit 31 outputs a load current signal Isen to an internal current sampling resistor Rs to generate a load current sampling voltage signal Vsp, which is supplied to the sample-and-hold circuit 33.
As shown in fig. 2 and 3, the sampling compensation circuit 34 is electrically connected to an output voltage terminal, so that an output voltage signal VOUT becomes an input signal of the sampling compensation circuit 34, and the sampling compensation circuit 34 calculates a compensation current signal I1 according to the output voltage signal VOUTV and sends the compensation current signal I1 to the sample hold circuit 33; the sample-and-hold circuit 33 receives the voltage signal Vsp or the compensation current signal I1 at one end of the internal sampling resistor Rs, and the output signal Vsen of the sample-and-hold circuit 33 is sent to the low-pass filter 32, and the load current feedback signal vsen_fb for outputting to the CC/CV error amplifier module 50 is obtained after the low-pass filtering of the low-pass filter 32.
As shown in fig. 3, the source of the first Buck output power tube Q1 is connected to an external input voltage source VIN, the drain of the first Buck output power tube Q1 is connected to the drain of the second Buck output power tube Q2, i.e. the continuous tube Q2, the drain of the second Buck output power tube Q2 is electrically connected to one end of the external inductor, i.e. the circuit node LX, and the gate of the first Buck output power tube Q1 is connected to the logic control circuit output signal GP.
As shown in fig. 3, the drain of the second Buck output power tube Q2 is connected to the drain of the first Buck output power tube Q1 and one end of the external inductor, namely, the circuit node LX, the source of the second Buck output power tube Q2 is connected to GND, and the gate of the second Buck output power tube Q2 is connected to the output signal GN of the logic control circuit.
As shown in fig. 3, the source of the current sampling tube Q3 is electrically connected to an external input voltage source VIN, the gate of the current sampling tube Q3 is grounded, and the drain of the current sampling tube Q3 is electrically connected to the first input terminal of the current sampling circuit 31; the current sampling circuit 31 includes a fourth PMOS transistor Q4 for obtaining a sampling current from the current sampling transistor Q3, a current sampling operational amplifier 37 for sampling a drain voltage signal of the first Buck output power transistor Q1, and a first switch K1 and a second switch K2 for controlling an input signal; the first switch K1 receives a first control signal
Is controlled by the control of the (c),the second switch K2 receives the non-signal of the first control signal>
Is controlled by the control system.
As shown in fig. 3, a first input terminal of the current sampling operational amplifier 37 is electrically connected to one end of the first switch K1; the other end of the first switch K1 is electrically connected with the drain electrode of the first Buck output power tube Q1; a first input terminal of the current sampling operational amplifier 37 is electrically connected with one end of the second switch K2; the other end of the second switch K2 is electrically connected to an external input voltage source VIN.
As shown in fig. 3, the source of the fourth PMOS transistor Q4 is used as the first input terminal of the current sampling circuit 31 and is electrically connected to the drain of the current sampling tube Q3, the gate of the fourth PMOS transistor Q4 is electrically connected to the output terminal of the current sampling operational amplifier 37, the second input terminal of the current sampling operational amplifier 37 is electrically connected to the source of the fourth PMOS transistor Q4, and the drain of the fourth PMOS transistor Q4 is used as the output terminal of the current sampling circuit 31 to output the load current sampling signal Isen to the internal current sampling resistor Rs.
As shown in fig. 3, the sample-and-hold circuit 33 includes a sample-and-hold capacitor Cp for holding the input signal voltage, a Buffer circuit 36 for buffering the input signal, and a third switch K3 for controlling the input signal of the sample-and-hold circuit; the third switch K3 receives the first control signal
Is controlled by (a); an input terminal of the Buffer circuit 36 is electrically connected to one end of the sample-and-hold capacitor Cp, and the other end of the sample-and-hold capacitor Cp is grounded; an input terminal of the Buffer circuit 36 is electrically connected to one end of the third switch K3, and the other end of the third switch K3 is used as a first input terminal of the sample-and-hold circuit 33 and is electrically connected to a non-ground terminal of the internal current sampling resistor Rs; an output terminal of the Buffer circuit 36 serves as an output terminal of the sample hold circuit 33.
In the embodiment of the Buck converter load current detection circuit shown in fig. 3, the Buck converter load current detection circuit further includes a sampling compensation circuit 34 for detecting the output voltage during the on period of the freewheeling tube of the Buck circuit and obtaining a compensation current from the output voltage; the sample-and-hold circuit 33 further comprises a second input terminal, the second input terminal of the sample-and-hold circuit 33 being electrically connected to the output terminal of the sample-and-compensate circuit 34; the input terminal of the sampling compensation circuit 34 is electrically connected to an external output voltage output terminal.
As shown in fig. 3, the sample-and-hold circuit 33 further includes a fourth switch K4 for electrically connecting with the sample compensation circuit; the fourth switch K4 receives the non-signal of the first control signal
An input signal to control the second input terminal of the sample-and-hold circuit 33; an input terminal of the Buffer circuit 36 is electrically connected to one end of the fourth switch K4, and the other end of the fourth switch K4 is used as a second input terminal of the sample hold circuit 33 and is electrically connected to one end of the sample compensation circuit 34.
As shown in fig. 3, the low-pass filter 32 includes a low-pass filter resistor Rf and a low-pass filter capacitor Cf, and one end of the low-pass filter resistor Rf is used as an input end of the low-pass filter 32 and is electrically connected to an output end of the sample-and-hold circuit 33; the other end of the low-pass filter resistor Rf is used as an output end of the low-pass filter 32 and is electrically connected to one end of the low-pass filter capacitor Cf, and the other end of the low-pass filter capacitor Cf is grounded.
In the embodiment of the Buck converter load current detection circuit shown in fig. 3, the Buck converter load current detection circuit further includes an error amplifier 38 for feeding back a current-voltage signal and a reference voltage comparison operation, a first input terminal of the error amplifier 38 is electrically connected to an output terminal of the reference voltage generation circuit 90; a second input terminal of the error amplifier 38 is electrically connected to an output terminal of the low pass filter 32. The error amplifier 38 may be part of an integrated CC/CV error amplifier 50.
In the embodiment of the Buck converter load current detection circuit shown in fig. 3, the reference voltage generation circuit 90 further includes a reference voltage circuit resistor RL and a current source Iref, where the reference voltage generation circuit 90 includes a reference voltage circuit resistor RL; the positive electrode of the current source Iref is electrically connected to the partial input voltage source VIN, and the negative electrode of the current source Iref is used as the output terminal of the reference voltage generating circuit 90; the negative electrode of the current source Iref is also electrically connected with one end of the reference voltage circuit resistor RL, and the other end of the reference voltage circuit resistor RL is grounded. The reference voltage generating circuit 90 generates a reference voltage signal REFL.
As shown in fig. 3, the positive input end of the error amplifier 38, i.e., the first input terminal, is connected to the reference voltage signal REFL, the negative input end of the error amplifier 38 is connected to the output signal vsen_fb of the low-pass filter, and the output signal of the error amplifier 38 is VCL, which is an error output signal representing the feedback voltage vsen_fb corresponding to the load current and the reference voltage REFL; one end of the off-chip inductor L1 is used as a voltage output terminal for outputting a voltage VOUT, the other end of the off-chip inductor L1 outputs a voltage signal representing the magnitude of the inductor current, one end of the capacitor C8 is electrically connected with the voltage output terminal VOUT of the off-chip inductor L1, and the other end of the capacitor C8 is grounded.
In the signal timing diagram shown in fig. 4, IL is a current signal timing diagram on the off-chip inductor L1, io is an output load current, vin is an external input voltage connected to an external voltage source Vin, and Vs is a drain voltage signal of the current sampling tube Q3; vsp is the voltage signal of the non-grounding end of the internal sampling resistor Rs; vp is the voltage signal at the non-ground terminal of the sample-and-hold capacitor Cp, and vsen_fb is the output signal of the low-pass filter.
As shown in fig. 4, when the Buck conversion circuit to which the present Buck converter load current detection circuit is applied operates in the CCM mode, i.e., the continuous operation mode, two operation states are included in one operation cycle with a period T:
the first operating state is Phase1: in 0-DT time, the high-order PMOS tube Q1 is opened, the low-order NMOS tube, namely the second Buck output power tube Q2 is closed, at the moment, as the first Buck output power tube Q1, namely the high-order PMOS tube, is opened, the voltage output by the other end of the off-chip inductor L1 is instantaneously pulled up to (VIN-IL multiplied by RdQ 1), wherein VIN is the external input voltage, IL is the inductive current, and RdQ is the equivalent resistance of the high-order PMOS tube Q1 in the conducting state; at this time, the inductor current rises with a rising slope of (VIN-VOUT)/L1, where VIN is an external input voltage, VOUT is an output voltage, and L1 is an equivalent inductance value of the inductor. In this state, the inductor current flows in from the source of the high-order PMOS transistor Q1, flows out from the drain of the high-order PMOS transistor Q1, and flows into the inductor L1 and the capacitor C8 to form a current loop. DT is the time when the high-order PMOS tube Q1 is closed and the low-order NMOS tube Q2 is opened;
The second operating state is Phase2: in the DT-T time period, the high-order PMOS tube Q1 is closed, the low-order NMOS tube Q2 is opened, at this time, as Q1 is closed, the inductor has the effect of maintaining current, so that the flowing path of the inductor current is changed into a source electrode flowing into the low-order NMOS tube Q2 from the external capacitor C8, the inductor flows into the inductor L1 from the drain electrode of the low-order NMOS tube Q2, and then flows back into the capacitor C8 from the inductor to form a current loop, in this state, the inductor current is reduced, the falling slope of the inductor current is VOUT/L1, VIN is the external input voltage, VOUT is the output voltage, and L1 is the equivalent inductance value of the inductor.
As shown in fig. 4, when the current sampling circuit is in the Phase period of sampling the first working state Phase1, at this time, the high-order PMOS transistor Q1 is opened, current sampling is performed through the current sampling transistor Q3, that is, the sampling MOS transistor Q3, the switch K1 is closed, and the switch K2 is opened, at this time, the current sampling operational amplifier 37, that is, the OPA operational amplifier functions to ensure that the drain voltage signal Vs of the current sampling transistor Q3 is equal to the voltage of the connection point LX between the inductor and the drain electrode of the high-order PMOS transistor Q1, because the drain electrode of the high-order PMOS transistor Q1 is consistent with the drain voltage Vs of the current sampling transistor Q3, the current isen= (1/K) ×il sampled by the current sampling transistor Q3, where IL is the inductor current, and K is the amplification multiple of the current mirror formed by the current sampling transistor Q3 and the high-order PMOS transistor Q1, or may be the ratio of the on resistances of the current sampling transistor Q3 and the high-order PMOS transistor Q1; therefore, the voltage drop across the internal sampling resistor Rs is vsp= (1/K) ×il×rs, and at this time, the switch K3 is closed, the switch K3 of the sample-and-hold circuit is closed, the potential across the capacitor Cp is also vsp= (1/K) ×il×rs, and the sampled voltage rises synchronously with the rise of the inductor current. Assuming that the output current is Io; the ripple of the inductor current is: ((Vin-Vout)/L) ×dt, where d=vout/Vin; the low point of the inductor current is: io- ((Vin-Vout)/L) x DT; equivalent to inductor current low at Vsp: vsp= (1/K) ×rs× (Io- ((Vin-Vout)/L) ×dt); the inductor current high point is: io+ ((Vin-Vout)/L) x DT; the inductor current high point equivalent to Vsp is: vsp= (1/K) ×rs× (io+ ((Vin-Vout)/L) ×dt).
When the current sampling circuit is in a Phase period of sampling the second working state Phase2, the high-order PMOS tube Q1 is closed, the inductance current is reduced, at the moment, the current sampling is not directly used for sampling the current of the inductance, but the switch K3 is opened, so that Cp keeps the sampling voltage of the high-order PMOS tube Q1 at the moment when the high-order PMOS tube Q1 is closed, then according to the predicted reduction speed of the inductance current, the compensation current is introduced through the sampling compensation circuit to be equivalent to the introduction of the compensation current source I1, so that the capacitor Cp is slowly discharged in DT-T time, the process of reducing the inductance current is simulated, and if the process of reducing is simulated, the compensation current is supposed to be: i1 =cp×rs× (Vin-Vout) ×d×t/(k×l1× (1-D) T) =cp×rs×vout/K.
As can be seen from the above equation, the required compensation current is only a linear function of Vout, which is easily implemented in the circuit. Therefore, the potential on Vp is completely synchronous with the inductor current, and after passing through the Buffer and the low-pass filter 32 in the sample-and-hold circuit, the average voltage of Vp is vsen_fb, which is also linear relation with the output current Io, so that the load current can be well simulated.
As shown in fig. 4, the CCM of the present invention is an operation waveform diagram in the continuous operation mode. In a first working state, namely Phase1, a switching tube Q1 is opened, an inductance current rises by taking Io as a center point, a waveform corresponding to Vs follows a voltage waveform of a circuit node LX, the voltage waveform corresponding to a Vsp signal rises synchronously until a power tube Q1 is closed, a K3 switch is opened, the potential on a capacitor Cp is kept, under the action of a current compensation current I1, the analog inductance current drops correspondingly, as shown in a graph Vp signal, and a required Vsen_FB signal is obtained after the voltage waveform passes through a low-frequency filter; if the current compensation current I1 is not present, the waveform of the voltage Vp will also calculate the shadow area, the average voltage vsen_fb will become larger, i.e. the sampled voltage will become larger, the actual detected load current will become lower, and some error will be introduced, but the method can be applied to situations where the detection requirement is not very high.
As shown in fig. 5, an illustration of a sample compensation circuit implementation of the present invention is shown. The sampling compensation circuit 34 includes a first resistor R1, a second resistor R2, a third resistor R3, a compensation amplifier 345, a fifth MOS transistor Q5, a sixth MOS transistor Q6, and a seventh MOS transistor Q7; one end of the first resistor R1 is electrically connected to an output terminal of the output voltage VOUT and is used as an input terminal of the sampling compensation circuit 34; the other end of the first resistor R1 is electrically connected with the negative input end of the compensation amplifier 345; one end of the second resistor R2 is electrically connected to the negative input terminal of the compensation amplifier 345; the other end of the second resistor R2 is grounded; one end of the third resistor R3 is electrically connected with an output terminal of the output voltage VOUT; the other end of the third resistor R3 is electrically connected with the positive input end of the compensation amplifier 345; the positive input end of the compensation amplifier 345 is also electrically connected with the source electrode of the fifth MOS transistor Q5; the grid electrode of the fifth MOS transistor Q5 is electrically connected with the output end of the compensation amplifier 345; the drain electrode of the fifth MOS tube Q5 is electrically connected with the drain electrode of the sixth MOS tube Q6; the source electrode of the sixth MOS transistor Q6 is electrically connected with the source electrode of the seventh MOS transistor Q7; the grid electrode of the sixth MOS tube Q6 is electrically connected with the grid electrode of the seventh MOS tube Q7; the sixth MOS transistor Q6 and the sixth MOS transistor Q6 form a current mirror; the drain electrode of the seventh MOS transistor Q7 is used as an output terminal of the sampling compensation circuit, and is used for outputting a compensation current.
As shown in fig. 5, the voltage at the negative input end of the operational amplifier is the divided voltage of the output voltage VOUT, and then a compensation current is generated through the operational amplifier, the resistor R3 and the MOS transistor Q5, where the magnitude of the compensation current is i1=vout×r1/(rs× (r1+r2)), and according to the above-mentioned formula, cp/k=r1/(rs×rs× (r1+r2)) can be obtained, so that the formula can know that a reasonable resistance relationship is set to obtain the compensation current, obtain an analog waveform under the freewheeling period, and increase the accuracy of inductor current detection.
As shown in FIG. 6The invention relates to a specific implementation scheme of an operational amplifier OPA in a Buck load current high-precision detection circuit without a sampling resistor. Embodiments to reduce offset of operational amplifier, the chop structure is adopted, because the sampling signal is of relatively high level, the input pair tube adopts NMOS type, the current sources Ir, Q12, Q13, Q14, Q15 form mirror current sources to provide mirror current required by OPA, when the control signal is
At high level, Q10 is connected to the positive input INP of the op-amp OPA, Q11 is connected to the negative input of the op-amp OPA, Q16 is connected to Q14, Q17 is connected to Q15, assuming that the offset equivalent to the input pair is Vos, when the positive input signal INP of the op-amp opa=the negative input signal INN of the op-amp, the OUT terminal outputs current: iout=gm10×vos, where gm10 is the transconductance of Q10, vos is due to process variations, equivalent to the offset error voltage of the input pair of tubes; when- >
When the voltage is at a low level or zero level, the Q10 is connected to the inverting input terminal INN of the op-amp OPA, the Q11 is connected to the forward input terminal INP of the op-amp OPA, the Q16 is connected to the Q15, and the Q17 is connected to the Q14, and when the positive input signal INP of the op-amp=the negative input signal INN of the op-amp, the current is output from the OUT terminal: iout= -gm10 x Vos, where gm10 is the transconductance of Q10, vos is the offset error voltage equivalent to the input pair of tubes due to process variations; thus (S)>
When=1, at this time>
Is a logic high level 1, the operational amplifier output current is gm10 XVos, +.>
When=0, at this time +.>
Is a logic low level 0 which is set to a logic low level,the operational amplifier outputs current gm10 xVos which are positive and negative, and after external RC filtering, 2 signals which are positive and negative can offset errors generated by offset error voltage Vos equivalent to the input pair tube, so that the detection precision is improved.
According to the technical scheme, the Buck converter load current detection circuit without an external sampling resistor comprises a current sampling tube Q3, a current sampling circuit 31, a sampling hold circuit 33 and a low-pass filter 32; when the first Buck output power tube Q1 is conducted, the Buck converter load current detection circuit utilizes a current sampling tube Q3 and a current sampling circuit 31 to sample and obtain the conducting current of the first Buck output power tube Q1; when the first Buck output power transistor Q1 is turned off, the sample-and-hold circuit 33 and the low-pass filter are used to generate a feedback current signal, and the feedback signal of the external load current is simulated to control the output current of the Buck converter. The invention does not need an external sampling resistor, simplifies the design of a peripheral circuit, reduces energy loss, improves the overall efficiency, and can realize the same precision as the external one by adopting a proper specific circuit to realize high-precision constant-current charging.
Compared with the prior art, the invention has the beneficial effects that: 1. no extra external sampling resistor is needed, no extra pins are needed, and the periphery is simplified; 2. the energy loss caused by the sampling resistor is reduced, and the overall efficiency is improved; 3. the inductance current estimation circuit simulates an inductance current sampling signal, so that a sampling circuit is simplified, and the sampling precision is improved; 4. the sampling operational amplifier adopts a Chop structure, so that sampling offset is reduced, and sampling precision is further improved.
In addition, for convenience of description, the electronic components such as the NMOS transistor, the resistor, the capacitor, etc. are all numbered in the first order and the second order, and these order numbers do not represent the position or the limitation in order, but are only for convenience of description. The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes using the contents of the specification and drawings, or direct or indirect application in other related technical fields, are included in the scope of the invention.
Claims (9)
1. A Buck converter load current detection circuit without an external sampling resistor, comprising:
A current sampling tube (Q3) for mirroring the current of the first Buck output power tube (Q1), a current sampling circuit (31) for sampling the current output from the drain of the current sampling tube (Q3), a sample-hold circuit (33) for sampling and holding the peak current at the closing time of the first Buck output power tube (Q1) and a low-pass filter (32) for low-pass filtering the output voltage signal of the sample-hold circuit;
the source electrode of the current sampling tube (Q3) is electrically connected with an external input voltage source (VIN), the grid electrode of the current sampling tube (Q3) is grounded, and the drain electrode of the current sampling tube (Q3) is electrically connected with a first input terminal of the current sampling circuit (31); a second input terminal of the current sampling circuit (31) is electrically connected with an external input voltage source (VIN); a third input terminal of the current sampling circuit (31) is electrically connected with the drain electrode of the first Buck output power tube (Q1);
an output terminal of the current sampling circuit (31) is electrically connected with a first input terminal of the sample-and-hold circuit (33), an output terminal of the current sampling circuit (31) is electrically connected with one end of an internal current sampling resistor (Rs), and the other end of the internal current sampling resistor (Rs) is grounded;
an output terminal of the sample-and-hold circuit (33) is electrically connected with an input terminal of the low-pass filter (32), and an output signal of the output terminal of the low-pass filter (32) is used as a load current sampling signal output by a Buck converter load current detection circuit;
The sampling compensation circuit (34) is used for detecting output voltage in a period of time when the first Buck output power tube (Q1) is closed and the second Buck output power tube (Q2) is conducted and obtaining compensation current through the output voltage;
the sample-and-hold circuit (33) further comprises a second input terminal, the second input terminal of the sample-and-hold circuit (33) being electrically connected to the output terminal of the sample compensation circuit (34); an input terminal of the sampling compensation circuit (34) is electrically connected to a voltage output terminal from which a voltage is output to the outside.
2. The Buck converter load current detection circuit according to claim 1, wherein an external sampling resistor is not required,
the current sampling circuit (31) comprises a fourth PMOS tube (Q4) for obtaining sampling current from the current sampling tube (Q3), a current sampling operational amplifier (37) for sampling a drain voltage signal of the first Buck output power tube (Q1), a first switch (K1) and a second switch (K2) for controlling input signals; the first switch (K1) receives the control of the first control signal (phi 1), and the second switch (K2) receives the non-signal of the first control signal
Is controlled by (a);
a first input terminal of the current sampling operational amplifier (37) is electrically connected with one end of the first switch (K1); the other end of the first switch (K1) is electrically connected with the drain electrode of the first Buck output power tube (Q1); a first input terminal of the current sampling operational amplifier (37) is electrically connected with one end of the second switch (K2); the other end of the second switch (K2) is electrically connected with an external input voltage source (VIN);
The source electrode of the fourth PMOS tube (Q4) is used as an input terminal of the current sampling circuit (31) and is electrically connected with the drain electrode of the current sampling tube (Q3), the grid electrode of the fourth PMOS tube (Q4) is electrically connected with the output terminal of the current sampling operational amplifier (37), the second input terminal of the current sampling operational amplifier (37) is electrically connected with the source electrode of the fourth PMOS tube (Q4), and the drain electrode of the fourth PMOS tube (Q4) is used as the output terminal of the current sampling circuit (31).
3. The Buck converter load current detection circuit according to claim 1, wherein an external sampling resistor is not required,
the sample-hold circuit (33) comprises a sample-hold capacitor (Cp) for holding the voltage of the input signal, a Buffer circuit (36) for buffering the input signal, and a third switch (K3) for controlling the input signal of the sample-hold circuit; the third switch (K3) is controlled by the first control signal (phi 1);
an input terminal of the Buffer circuit (36) is electrically connected with one end of the sample-hold capacitor (Cp), and the other end of the sample-hold capacitor (Cp) is grounded; an input terminal of the Buffer circuit (36) is electrically connected with one end of the third switch (K3), and the other end of the third switch (K3) is used as a first input terminal of the sample hold circuit (33) and is electrically connected with a non-grounding end of the internal current sampling resistor (Rs);
An output terminal of the Buffer circuit (36) serves as an output terminal of the sample-and-hold circuit (33).
4. The Buck converter load current detection circuit according to claim 1, wherein an external sampling resistor is not required,
the low-pass filter (32) comprises a low-pass filter resistor (Rf) and a low-pass filter capacitor (Cf), and one end of the low-pass filter resistor (Rf) is used as the input end of the low-pass filter (32) and is electrically connected with the output end of the sample hold circuit (33); the other end of the low-pass filter resistor (Rf) is used as an output end of the low-pass filter (32) and is electrically connected with one end of the low-pass filter capacitor (Cf), and the other end of the low-pass filter capacitor (Cf) is grounded;
the Buck converter load current detection circuit further comprises a reference voltage generation circuit (90), wherein the reference voltage generation circuit (90) comprises a current source (Iref) and a reference voltage circuit Resistor (RL); the positive electrode of the current source (Iref) is electrically connected to an external input voltage source (VIN), and the negative electrode of the current source (Iref) is used as an output terminal of the reference voltage generating circuit (90); the negative electrode of the current source (Iref) is also electrically connected with one end of the reference voltage circuit Resistor (RL), and the other end of the reference voltage circuit Resistor (RL) is grounded;
The Buck converter load current detection circuit further comprises an error amplifier (38) for feeding back a current-voltage signal and a reference voltage comparison operation, wherein a first input terminal of the error amplifier (38) is electrically connected with an output terminal of the reference voltage generation circuit (90); a second input terminal of the error amplifier (38) is electrically connected to an output terminal of the low pass filter (32).
5. The Buck converter load current detection circuit according to claim 2, wherein an external sampling resistor is not required,
the current sampling operational amplifier (37) includes an auto-zeroed chopper operational amplifier, a low error operational amplifier, and an auto-zeroed operational amplifier.
6. The Buck converter load current detection circuit without external sampling resistor according to claim 3,
the sample-and-hold circuit (33) further comprises a fourth switch (K4) for electrically connecting with the sample compensation circuit (34); the fourth switch (K4) receives the non-signal of the first control signal
Is controlled by (a);
one end of the fourth switch (K4) is used as a second input terminal of the sampling hold circuit (33) and is electrically connected with one end of the sampling compensation circuit (34); non-signal by first control signal 
Controlling a signal input from a second input terminal of the sample-and-hold circuit (33); the other end of the fourth switch (K4) is electrically connected to an input terminal of the Buffer circuit (36).
7. The Buck converter load current detection circuit according to claim 1, wherein an external sampling resistor is not required,
the sampling compensation circuit (34) comprises a first resistor (R1), a second resistor (R2) and a third resistor (R3), a compensation amplifier (345), a fifth MOS tube (Q5), a sixth MOS tube (Q6) and a seventh MOS tube (Q7);
one end of the first resistor (R1) is electrically connected with an output terminal of the output Voltage (VOUT) and is used as an input terminal of the sampling compensation circuit (34); the other end of the first resistor (R1) is electrically connected with the negative electrode input end of the compensation amplifier (345); one end of the second resistor (R2) is electrically connected with the negative electrode input end of the compensation amplifier (345); the other end of the second resistor (R2) is grounded;
one end of the third resistor (R3) is electrically connected with an output terminal of the output Voltage (VOUT); the other end of the third resistor (R3) is electrically connected with the positive electrode input end of the compensation amplifier (345); the positive electrode input end of the compensation amplifier (345) is also electrically connected with the source electrode of the fifth MOS tube (Q5); the grid electrode of the fifth MOS tube (Q5) is electrically connected with the output end of the compensation amplifier (345); the drain electrode of the fifth MOS tube (Q5) is electrically connected with the drain electrode of the sixth MOS tube (Q6); the source electrode of the sixth MOS tube (Q6) is electrically connected with the source electrode of the seventh MOS tube (Q7); the grid electrode of the sixth MOS tube (Q6) is electrically connected with the grid electrode of the seventh MOS tube (Q7); the sixth MOS tube (Q6) and the sixth MOS tube (Q6) form a current mirror; the drain electrode of the seventh MOS tube (Q7) is used as an output terminal of the sampling compensation circuit and is used for outputting compensation current.
8. A Buck load current detection method based on the Buck converter load current detection circuit without an external sampling resistor according to any one of claims 1 to 5, comprising:
step 1: the current sampling tube (Q3) and a first Buck output power tube (Q1) in the Buck voltage conversion circuit form mirror image pair tubes, and when the first Buck output power tube (Q1) is conducted and a second Buck output power tube (Q2) is closed, the current sampling tube (Q3) acquires the conducting current of the first Buck output power tube (Q1), namely load current;
step 2: when the first Buck output power tube (Q1) is switched from a conducting state to a closing state, the sampling hold circuit (33) obtains the voltage of the current sampling tube (Q3) at the current moment, and the load current which is the follow current when the first Buck output power tube (Q1) is closed and the second Buck output power tube (Q2) is conducted is simulated jointly through the sampling hold circuit (33) and the low-pass filter (32).
9. A Buck load current detection method based on the Buck converter load current detection circuit without an external sampling resistor according to any one of claims 6 to 7, comprising:
step 1: the current sampling tube (Q3) and a first Buck output power tube (Q1) in the Buck voltage conversion circuit form mirror image pair tubes, and when the first Buck output power tube (Q1) is conducted and a second Buck output power tube (Q2) is closed, the current sampling tube (Q3) acquires the conducting current of the first Buck output power tube (Q1), namely load current;
Step 2: when the first Buck output power tube (Q1) is switched from a conducting state to a closing state, the sampling hold circuit (33) obtains the voltage of the current sampling tube (Q3) at the current moment, and the first Buck output power tube (Q1) is closed through the sampling hold circuit (33) and the low-pass filter (32) in a common simulation mode, and the follow current, namely the load current, when the second Buck output power tube (Q2) is conducted;
the step 2 comprises the following step 3: and during the closing of the first Buck output power tube (Q1) and the conduction of the second Buck output power tube (Q2), the sampling compensation circuit (34) detects the output voltage of the Buck circuit and obtains a compensation current through the output voltage, and the compensation current is used for compensating the follow current when the second Buck output power tube (Q2) is conducted, so that the follow current is closer to the real load current.
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